HTG12B0 4-Bit Microcontroller Features · · · · · · · · · Operating voltage: 2.4V~3.6V Eight input lines Eight input/output lines Five working registers 4K ´ 8 ´ 4 program ROM 128 ´ 4 ´ 8 (4096) bits data memory RAM Sound effect circuit 40 segment ´ 16 common, 1/4 bias LCD driver LCD output is fixed at 4.4V · · · · · · · RC oscillator & 32768Hz crystal oscillator 8-bit timer with internal or external clock source Internal timer overflow Up to 4ms instruction cycle with 1MHz system clock One level subroutine nesting Halt feature reduces power consumption 8-bit table read instruction General Description It is ideally suited for multiple LCD for time piece low power applications among which are calculators, scales, calendar and hand held LCD products. The HTG12B0 is a processor from HOLTEK¢s 4-bit stand-alone single chip microcontroller specially designed for LCD display and time piece product applications. 1 September 8, 1999 HTG12B0 Block Diagram S ta c k T im e r X IN A L U X O U T O S C I O S C O R E S T E S T 1 T E S T 2 P r o g r a m C o u n te r C o n tro l & T im in g C ir c u it T 1 D T 5 1 2 V D D T M C L K P A P A 0 P A 1 P A 2 P A 3 P B P B 0 P B 1 P B 2 P B 3 P S P S 0 P S 1 P S 2 P S 3 P M P M 0 P M 1 P M 2 P M 3 A C C R O M V S S R 0 In s tr u c tio n D e c o d e r R 1 R O M B R 2 R A M B R 3 L C D C R 4 T e m p o ra ry D a ta R A M S o u n d E ffe c t D is p la y D a ta R A M V O U V O U V O U V O U L C D D r iv e r T 3 T 4 B Z V L C V L C V L C V L C T 1 T 2 B Z 1 2 3 4 C O M 1 5 C O M 3 C O M 2 C O M 1 C O M 0 S E G 3 9 S E G 3 8 S E G 1 S E G 0 Note: ACC: Accumulator R0~R4: Working registers ROMB: ROM bank switch RAMB: RAM bank switch LCDC: LCD control register PA, PB: I/O ports PS, PM: Input ports 2 September 8, 1999 HTG12B0 Pad Assignment S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 S E G 8 S E G 9 S E G 1 0 S E G 1 1 S E G 1 2 S E G 1 3 S E G 1 4 S E G 1 5 S E G 1 6 S E G 1 7 S E G 1 8 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 4 7 1 S E G 1 9 7 0 S E G 2 0 6 9 S E G 2 1 5 P S 1 7 T M C L K 8 6 P S 0 R E S 9 3 3 P S 3 P S 2 T E S T 2 P M 0 T E S T 1 P M 1 2 P M 3 1 T 5 1 2 P M 2 9 4 6 8 S E G 2 2 6 7 S E G 2 3 6 6 S E G 2 4 6 5 S E G 2 5 6 4 S E G 2 6 6 3 S E G 2 7 6 2 S E G 2 8 6 1 S E G 2 9 6 0 S E G 3 0 5 9 S E G 3 1 5 8 S E G 3 2 S E G 3 3 9 P B 3 1 0 P B 2 1 1 P B 1 1 2 P B 0 1 3 P A 0 1 4 P A 1 1 5 P A 2 1 6 P A 3 1 7 T 1 D 1 8 (0 , 0 ) 5 7 B Z 5 6 S E G 3 4 5 5 S E G 3 5 1 9 B Z 2 0 5 4 S E G 3 6 V D D 2 1 5 3 S E G 3 7 O S C O O S C I 2 2 2 3 5 2 X O U T 2 4 5 1 S E G 3 8 S E G 3 9 X IN 2 5 V S S 2 6 5 0 C O M 0 V L C 1 V L C 2 V L C 3 V L C 4 V O U T 1 V O U T 2 V O U T 3 V O U T 4 C O M 1 5 C O M 1 4 C O M 1 3 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 C O M 1 3 7 C O M 2 3 6 C O M 3 3 5 C O M 4 3 4 C O M 5 3 3 C O M 6 3 2 C O M 7 3 1 C O M 8 C O M 9 3 0 C O M 1 0 2 9 C O M 1 1 2 8 C O M 1 2 2 7 Chip size: 3060 ´ 5140 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork. 3 September 8, 1999 HTG12B0 Pad Coordinates Unit: mm Pad No. X Y Pad No. X Y Pad No. X Y 1 -1394.56 2163.72 33 1204.48 -2436.28 65 1398.48 972.60 2 -1394.56 2043.72 34 1324.48 -2436.28 66 1398.48 1092.60 3 -1394.56 1923.72 35 1398.48 -2436.28 67 1398.48 1381.40 4 -1394.56 1803.72 36 1398.48 -2436.28 68 1398.48 1501.40 5 -1394.56 1683.72 37 1398.48 -2436.28 69 1398.48 1790.20 6 -1394.56 1563.72 38 1398.48 -2436.28 70 1398.48 1910.20 7 -1394.56 1443.72 39 1398.48 -2436.28 71 1398.48 2199.00 8 -1394.56 1323.72 40 1398.48 -2436.28 72 1327.44 2436.28 9 -1394.56 1203.72 41 1398.48 -2436.28 73 1207.44 2436.28 10 -1368.40 998.68 42 1398.48 -2436.28 74 1087.44 2436.28 11 -1368.40 749.88 43 1398.48 -2436.28 75 967.44 2436.28 847.44 2436.28 12 -1368.40 515.16 44 1398.48 -2436.28 76 13 -1368.40 266.36 45 1398.48 -2436.28 77 727.44 2436.28 14 -1368.40 31.64 46 1398.48 -2436.28 78 607.44 2436.28 15 -1368.40 -217.16 47 1398.48 -2436.28 79 487.44 2436.28 16 -1368.40 -451.88 48 1398.48 -2436.28 80 367.44 2436.28 17 -1368.40 -700.68 49 1398.48 -2436.28 81 247.44 2436.28 18 -1368.40 -935.40 50 1398.48 -2177.80 82 127.44 2436.28 1398.48 7.44 2436.28 19 -1304.07 -1189.85 51 -1889.00 83 20 -1304.07 -1344.25 52 1398.48 -1769.00 84 -112.56 2436.28 21 -1318.48 -1483.72 53 1398.48 -1480.20 85 -232.56 2436.28 22 -1355.04 -1630.76 54 1398.48 -1360.20 86 -352.56 2436.28 23 -1355.04 -1750.76 55 1398.48 -1071.40 87 -472.56 2436.28 24 -1355.04 -1885.00 56 1398.48 -951.40 88 -592.56 2436.28 25 -1355.04 -2005.00 57 1398.48 -662.60 89 -712.56 2436.28 26 -1343.84 -2164.44 58 1398.48 -542.60 90 -832.56 2436.28 27 -1315.52 -2436.28 59 1398.48 -253.80 91 -952.56 2436.28 28 -1195.52 -2436.28 60 1398.48 -133.80 92 -1072.56 2436.28 29 -1075.52 -2436.28 61 1398.48 155.00 93 -1192.56 2436.28 30 -955.52 -2436.28 62 1398.48 275.00 94 -1312.56 2436.28 31 -835.52 -2436.28 63 1398.48 563.80 32 -715.52 -2436.28 64 1398.48 683.80 4 September 8, 1999 HTG12B0 Pad Description Pad No. Pad Name I/O Mask Option Description Pull-high or None. Input pins for input only Note 2 4~7 94, 1~3 PS3~PS0 PM3~PM0 I 8 TMCLK I Pull-high or None. Note 4 9 RES I ¾ Input for TIMER clock TIMER can be clocked by an external clock or an internal frequency source. Input to reset an internal LSI Reset is active on logical low level. CMOS or NMOS with Pull-high or Input/output pins None. Note 3 17~14 10~13 PA3~PA0 PB3~PB0 19, 20 BZ, BZ O Note 1 Sound effect outputs 21 VDD I ¾ Positive power supply 23 22 OSCI OSCO I O ¾ An external resistor between OSCI and OSCO is needed for internal system clock. 25 24 XIN XOUT I O ¾ 32768Hz crystal oscillator for time base, LCD clock 26 VSS I ¾ Negative power supply, GND 27~30 VLC1~VLC4 I ¾ LCD system power 1/4 bias generated 31~34 VOUT1~VOUT4 I ¾ LCDsystemvoltageboostercondenserconnecting terminal 35~50 COM15~COM0 O ¾ Output for LCD panel common plate 51~90 SEG39~SEG0 O ¾ LCD driver outputs for LCD panel segment 93 18 92 91 T512 T1D TEST1 TEST2 O O I I I/O For test mode only TEST1 and TEST2 are left open when the chip is in normal operation (with an internal pull-high resistor). Note: 1. The system clock provides six different sources selectable by mask option to drive the sound effect clock. If the Holtek sound library is used, only 128K and 64K are acceptable. 2. Each bit of ports PM, PS can be a trigger source of the HALT interrupt, selectable by mask option. 3. Each bit of ports PA, PB can be selected as CMOS for output pin only, or as NMOS for I/O pin with pull-high resistor or none by mask option. 4. 14 internal clock sources can be selected by mask option to drive TMCLK. Note that TMCLK should not be connected to a pull high resistor if an internal source is used. 5 September 8, 1999 HTG12B0 Absolute Maximum Ratings Supply Voltage..............................-0.3V to 5.5V Input Voltage ......................VSS-0.3 to VDD+0.3 Storage Temperature.................-50°C to 125°C Operating Temperature ..................0°C to 70°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter Ta=25°C Test Conditions VDD Conditions ¾ Min. Typ. Max. Unit 2.4 3 3.6 V VDD Operating Voltage ¾ IDD Operating Current 3V No load, fSYS=512kHz ¾ 200 300 mA ISTB Standby Current, (fSYS OFF and RTC ON, LCD ON) 3V Halt mode ¾ 10 15 mA VIL Input Low Voltage 3V ¾ 0 ¾ 0.2VDD V VIH Input High Voltage 3V ¾ 0.8VDD ¾ VDD V IOL1 PA, PB, BZ and BZ Output Sink Current 3V VOL=0.3V 1.5 3 ¾ mA IOH1 PA, PB, BZ and BZ Output Source Current 3V VOH=2.7V -0.5 -1 ¾ mA IOL2 Segment Output Sink Current 3V VOL=0.44V VLCD=4.4V 100 200 ¾ mA IOH2 Segment Output Source Current 3V VOH=4.0V VLCD=4.4V 30 60 ¾ mA RPH Pull-high Resistor 3V PS, PM, RES, TMCLK 50 100 150 kW VLCD VLCD Output Voltage 3V 3.96 4.4 4.84 V ¾ 6 September 8, 1999 HTG12B0 A.C. Characteristics Symbol Parameter Ta=25°C Test Conditions VDD Conditions Min. Typ. Max. Unit 128 ¾ 1000 kHz fSYS System Clock 3V R=620kW~51kW tCY Cycle Time 3V fSYS=1MHz ¾ 4 ¾ ms fTIMER Timer I/P Frequency (TMCLK) 3V ¾ 0 ¾ 1000 kHz tRES Reset Pulse Width ¾ ¾ 5 ¾ ¾ ms fSOUND Sound Effect Clock ¾ ¾ ¾ *64 or 128 ¾ kHz *: Only these two clocking signal frequencies are supported by the Holtek sound library. Functional Description · Location 000H: (Bank 0) Program counter - PC Activating the processor RES pin causes the first instruction to be fetched from location 0. This counter addresses the program ROM and is arranged as a 12-bit binary counter from PC0 to PC11 whose contents specify a maximum of 4096 addresses. The program counter counts with an increment of 1 or 2 with each execution of an instruction. 0 0 0 H R e s e t in itia l p r o g r a m 0 0 4 H T im e r in te r r u p t s u b r o u tin e 0 0 8 H R T C in te r r u p t s u b r o u tin e 0 0 B H When executing the jump instruction (JMP, JNZ, JC, JTMR,...), a subroutine call, initial reset, internal interrupt, RTC interrupt or returning from a subroutine, the program counter is loaded with the corresponding instruction data as shown in the table. P a g e N F 0 0 H F F F H P ro g ra m R O M B a n k 0 lo o k - u p ta b le P a g e F lo o k - u p ta b le ( 2 5 6 b y te s ) 8 b its Note: P0~P11: Instruction code @: PC11 keeps current value S0~S11: Stack register bits ROMB0 and ROMB1 are set to 0 at power on reset. Program memory ROMB=XX00B 0 0 0 H 0 0 4 H Program memory - ROM 0 0 8 H The program memory is the executable memory and is arranged in a 4096´8-bit format. There are four banks for program memory in HTG12B0, each bank shown in the figure can be switched by assigning ROMB0 and ROMB1 (bit0 and bit1 of ROMB). ROMB is the ROM bank pointer and can be written only by executing ²MOV ROMB, A² instruction. Bit 2 and bit 3 of ROMB are unused bits. The address is specified by the program counter (PC). Four special locations are reserved as described next. 0 0 B H T im e r in te r r u p t s u b r o u tin e R T C in te r r u p t s u b r o u tin e P a g e N F 0 0 H F F F H P ro g ra m R O M B a n k 1 lo o k - u p ta b le P a g e F lo o k - u p ta b le ( 2 5 6 b y te s ) 8 b its Program memory ROMB=XX01B 7 September 8, 1999 HTG12B0 · Location 004H: (Bank 0~3) In the execution of an instruction, the program counter is added before the execution phase, so careful manipulation of READ MR0A and READ R4A is required in the page margin. Contains the timer interrupt resulting from a TIMER overflow. If the interrupt is enabled, the CPU begins execution at location 004H. 0 0 0 H · Location 008H: (Bank 0~3) 0 0 4 H Activating the RTC of the processor with the interrupts enabled causes the program to jump to this location. T im e r in te r r u p t s u b r o u tin e 0 0 8 H R T C · Locations n00H to nFFH: (Bank 0~3) P a g e N Each page in the program memory consists of 256 bytes. This area from n00H to nFFH and F00H to FFFH can be used as a look-up table. Instructions such as READ R4A, READ MR0A, READF R4A, READF MR0A can read the table and transfer the contents of the table to ACC and R4 or to ACC and a data memory address specified by the register pair R1,R0. However as R1,R0 can only store 8 bits, these instructions cannot fully specify the full 12 bit program memory address. For this reason a jump instruction should first be used to place the program counter in the right page. The above instructions can then be used to read the look up table data. F 0 0 H P ro g ra m R O M B a n k 2 lo o k - u p ta b le P a g e F lo o k - u p ta b le ( 2 5 6 b y te s ) F F F H 8 b its Program memory ROMB=XX10B 0 0 0 H 0 0 4 H T im e r in te r r u p t s u b r o u tin e 0 0 8 H R T C in te r r u p t s u b r o u tin e 0 0 B H P a g e N F 0 0 H Note that the page number n must be greater than zero since some locations in page 0 are reserved for specific usage. This area may function as normal program memory. P ro g ra m R O M B a n k 3 lo o k - u p ta b le P a g e F lo o k - u p ta b le ( 2 5 6 b y te s ) F F F H 8 b its Program memory ROMB=XX11B The program memory mapping is shown in the diagram. Mode in te r r u p t s u b r o u tin e 0 0 B H Program Counter PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Initial reset ROMB1 ROMB0 0 0 0 0 0 0 0 0 0 0 0 0 Internal interrupt ROMB1 ROMB0 0 0 0 0 0 0 0 0 0 1 0 0 RTC interrupt ROMB1 ROMB0 0 0 0 0 0 0 0 0 1 0 0 0 Jump, call instruction ROMB1 ROMB0 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Conditional branch ROMB1 ROMB0 @ P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Return from ROMB1 ROMB0 subroutine Program memory 8 September 8, 1999 HTG12B0 R A M B a n k 0 (R A M B = X 0 0 0 B ) 0 0 H 7 F H T e m p o ra ry D a ta A re a (1 2 8 x 4 ) 4 b its R A M B a n k 1 (R A M B = X 0 0 1 B ) 0 0 H R A M B a n k 7 (R A M B = X 1 1 1 B ) 0 0 H T e m p o ra ry D a ta A re a (1 2 8 x 4 ) 7 F H T e m p o ra ry D a ta A re a (1 2 8 x 4 ) 7 F H 4 b its 4 b its Temporary data memory 7FH of RAM bank 0~RAM bank 7. Access to the display data area is from B0H to FFH of LCD bank 0 and bank 1. Stack register The stack register is a group of registers used to save the contents of the program counter (PC) and is arranged into 13 bits ´ 1 level. One bit is used to store the carry flag. An interrupt will force the contents of the PC and the carry flag onto the stack register. A subroutine call will also cause the PC contents to be pushed onto the stack; however the carry flag will not be stored. At the end of a subroutine or an interrupt routine which is signaled by a return instruction, RET or RETI restore the program counter to its previous value from stack register. Executing ²RETI² instruction will restore the carry flag from the stack register, but ²RET² does not. There are eight banks for the temporary data memory in HTG12B0, each bank shown in the figure can be switched by assigning RAMB0~RAMB2 (bit 0~bit 2 of RAMB). RAMB is the RAM bank pointer and can be written only by executing ²MOV RAMB, A² instruction. Bit 3 of RAMB is unused bit. Each bank maps to different area of the data memory. There are two banks for displaying the data memory, each bank can be switched by the assignment of LCDC0 (bit 0 of LCDC). LCDC is a control register for LCD application and can be written only by executing ²MOV LCDC, A² instruction. Working registers - R0, R1, R2, R3, R4 When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. There are five working registers (R0, R1, R2, R3, R4) usually used to store the frequently accessed intermediate results. Using the instructions INC Rn and DEC Rn the working registers can increment (+1) or decrement (-1). The JNZ Rn (n=0, 1, 4) instruction makes efficient use of the working registers as a program loop counter. Also the register pairs R0,R1 and R2,R3 are used as a data memory pointer when the memory transfer instruction is executed. L C D B a n k 0 (L C D C = X X X 0 B ) B 0 H F F H D is p la y D a ta A r e a (8 0 x 4 ) 4 b its L C D B a n k 1 (L C D C = X X X 1 B ) Data memory - RAM B 0 H The static data memory (RAM) is arranged in 128´4-bit format and is used to store data. All of the data memory locations are indirectly addressable through the register pair R1,R0 or R3,R2; for example MOV A,[R3R2] or MOV [R3R2],A. F F H D is p la y D a ta A r e a (8 0 x 4 ) 4 b its Display data memory There are two areas in the data memory, the temporary data area and display data area. Access to the temporary data area is from 00H to 9 September 8, 1999 HTG12B0 start the timer, load the counter with the value XXH and then issue a TIMER ON instruction. Note that XX is the desired start count immediate value of the 8 bits. Once the Timer/Counter is started it increments to a maximum count of FFH and then overflows to zero (00H). It then continues to count until stopped by a TIMER OFF instruction or a reset. The locations between the temporary and display data areas are undefined and cannot be used. Accumulator - ACC The accumulator is the most important data register in the processor. It is one of the sources of input to the ALU and the destination of the results of the operations performed in the ALU. Data to and from the I/O ports and memory also passes through the accumulator. The increment from the maximum count of FFH to a zero (00H) triggers a timer flag TF and an internal interrupt request. The interrupt may be enabled or disabled by executing the EI and DI instructions. If the interrupt is enabled, the timer overflow will cause a subroutine call to location 4. The state of the timer flag can also be tested with the conditional jump instruction JTMR. The timer flag is cleared after the interrupt or the JTMR instruction is executed. Arithmetic and logic unit - ALU This circuit performs the following arithmetic and logic operations ... · Add with or without carry · Subtract with or without carry · AND, OR, Exclusive-OR If an internal source is used, the frequency is determined by the system clock and the parameter n as defined in the equation. The frequency of the internal frequency source can be selected by mask option. system clock Frequency of TIMER clock = 2n where n=0, 1, 2... 3 selectable by mask option. · Rotate right, left through carry · BCD decimal adjust for addition · Increment, decrement · Data transfers · Branch decisions The ALU not only outputs the results of data operations, but also sets the status of the carry flag (CF) in some instructions. RTC There is a real time clock (RTC) function implemented on the HTG12B0. The RTC function is used to generate an accurate time period. The RTC circuit clock source comes from the 32768Hz crystal oscillator. The block diagram is shown as follows. Timer/counter The HTG12B0 contains a programmable 8-bit count-up counter which can be used to count external events or used as a clock to generate an accurate time base. X 't a l 3 2 7 6 8 H z If the 8-bit timer clock is supplied by an external source from pin TMCLK, synchronization problems may occur when reading the data from the timer. It is therefore recommended that the timer is stopped before retrieving the data. The 8-bit counter will increment on the rising edge of the clock whether it is internally or externally generated. 1 1 1 2 8 M 2 n , n = 0 ~ 7 a s k O p tio n In te r r u p t The output of RTC can be selected by mask option. 256 , n=0~7 Frequency of RTC output = 2n The Timer/Counter may be set and read with software instructions and stopped by a hardware reset or a TIMER OFF instruction. To re- The RTC output is used to generate an interrupt signal. 10 September 8, 1999 HTG12B0 When RES is active, the internal block will be initialized as shown below: Interrupt The HTG12B0 provides both TIMER and RTC interrupt modes. The DI and EI instructions are used to disable and enable the interrupts. When the RTC is activated during enable interrupt mode and the program is not within a CALL subroutine, this causes a subroutine call to location 8 and reset the interrupt latch. Likewise when the timer flag is set in the enable interrupt mode and the program is not within a CALL subroutine, the TIMER interrupt is activated. This cause a subroutine call to location 4 and resets the timer flag. If both TIMER and RTC interrupts arrive at the same time, the RTC one will be serviced first. PC 000H TIMER Stop Timer flag Reset (low) SOUND Sound off and One sing mode Output port A High (or floating state) LCD output Enable BZ and BZ output Low level When running under a CALL subroutine or DI the interrupt acknowledge is on hold until the RET or EI instruction is invoked. The CALL instruction should not be used within an interrupt routine as unpredictable results may occur. If within a CALL subroutine both TIMER and RTC interrupt occur, no matter what order they arrive in, the RTC interrupt will be serviced first after leaving the CALL subroutine. This also applies if the two interrupt arrive at the same time. ROMB XX00B RAMB X000B LCDC 1100B HALT This is a special feature of the HTG12B0 to interrupt the chip¢s normal operation and reduce power consumption. When a HALT is executed the following happens ... · The system clock will be stopped The interrupts are disabled by a hardware reset or a DI instruction. They remain disabled until the EI instruction is executed. · The contents of the on-chip RAM and regis- Initial reset · BZ and BZ maintain low level output The HTG12B0 provides a RES pin for system initialization. This pin is equipped with an internal pull high resistor and in combination with an external 0.1m~1mF capacitor, it provides an internal reset pulse of sufficient length to guarantee a reset to all internal circuits. If the reset pulse is generated externally, the RES pin must be held low at least 5ms. The system can leave the HALT mode through initial reset or RTC interrupt or wake-up from the following entry of program counter value. ters remain unchanged · RTC oscillator keeps on running Initial reset: 00H Wake-up: next address of the HALT instruction 11 September 8, 1999 HTG12B0 When the halt status is terminated by the RTC interrupt, the following procedure takes place: Case 1: If the system is in an interrupt-disable state before entering the halt state: Holtek¢s sound library supports only sound clock frequency of 128K or 64K. To use Holtek¢s sound library the proper system clock and mask option should be selected. · The system will be awakened and returns to LCD display memory the main program instruction following the HALT command. As mentioned in the data memory section, the LCD display memory is embedded in the data memory. It can be read and written to in the same way as normal data memory. · The RTC interrupt will be held until the sys- tem receives an enable interrupt command by which the RTC interrupt will be serviced. The figure illustrates the mapping between the display memory and LCD pattern for the HTG12B0. Case 2: If the system is in an interrupt enable state: There is an ON/OFF switch for display controlled by bit 3 of LCDC (LCDC 3). The corresponding bit of the LCDC 3 represents ²ON² or ²OFF² of display of LCD display memory. · The RTC interrupt will awake the system and execute the RTC interrupt subroutine. In the HALT mode, each bit of ports PM, PS, can be used as wake-up signal by mask option to wake-up the system. This signal is active in low-going transition. The LCD display module may have any form as long as the number of commons does not exceed 16 and the number of segments is not over 40. Sound effects D IS P L A Y M E M O R Y C O M The HTG12B0 includes sound effect circuitry which offers up to 16 sounds with 3 tones, boom and noise effects. Holtek supports a sound library including melodies, alarms, machine guns etc.. If the instruction ²SOUND A² is executed, the specified sound begins. Each time ²SOUND OFF² is executed, it terminates the singing sound immediately. F E H F 8 H B 4 H B 2 H B 0 H B IT 0 1 1 2 2 3 3 F F H The frequency of the sound effect circuit can be selected by mask option. system clock Frequency of sound effect circuit = 2m ...where m=0,1,2,3,4,5. F A H 0 There are two singing modes, SONE mode and SLOOP mode activated by SOUND ONE and SOUND LOOP. In SONE mode the specified sound plays only once. In the SLOOP mode the specified sound keeps re-playing. Since sounds 0~11 contain 32 notes and sounds 12~15 include 64 notes the latter possesses better sound than the former. F C H F D H F B H F 9 H B 5 H B 3 H B 1 H 4 0 5 1 6 2 7 3 S E G M E N T 0 1 2 3 3 7 3 8 3 9 LCD display memory (LCDC0=0) 12 September 8, 1999 HTG12B0 D IS P L A Y M E M O R Y C O M F E H F C H F A H F 8 H B 4 H B 2 H B 0 H 0 9 1 1 0 2 1 1 3 Frequency of LCD clock = 8 F F H F D H F B H F 9 H B 5 H B 3 H ....where n=0~5 LCD driver output is enabled by setting LCDC3 as ²1², and disabled by setting LCDC 3 as ²0². Register Bit No. B 1 H 0 1 3 1 1 4 2 1 5 3 0 1 2 3 3 7 3 8 3 9 LCD driver output All of the LCD segments are random after an initial clear. The bias voltage circuits of the LCD display is built-in and no external resistor is required. 1 Select LCD clock source 0=RTC OSC (32768Hz) 1=System clock 2 PM3 edge latch control bit 1=Enabled 0=Disabled 3 Control LCD display 0=OFF 1=ON An example of an LCD driving waveform (1/16 duty and 1/4 bias) is shown below. 6 4 H z 1 2 3 1 3 1 4 1 5 1 2 3 4 5 1 0 2 4 H z The frequency of the LCD driving clock source can be selected from RTC OSC or system clock by accessing bit 1 of LCDC. There are many frequency division of the LCD clock which can be selected by mask option either from RTC OSC or system clock. ....where n=0~7 Select LCD bank 0=Bank 0 (Com0~7) 1=Bank 1 (Com8~15) LCDC Register The output number of the HTG12B0 LCD driver is 40´16 which can directly drive an LCD with 1/16 duty cycle and 1/4 bias. Frequency of LCD clock = Function 0 LCDC LCD display memory (LCDC0=1) · RTC OSC f SYS 64 Hz 2n LCD driver output can be enabled or disabled by setting LCDC 3 without the influence of the related memory condition. 1 2 S E G M E N T · System clock B IT 16384 Hz 2n V L 3 /4 V L C O M 0 2 /4 V L 1 /4 V L G C D C D C D C D N D V L 3 /4 V L C O M 1 2 /4 V L 1 /4 V L G C D C D C D C D N D V L 3 /4 V L S E G 0 2 /4 V L 1 /4 V L G C D C D C D C D N D VLCD is fixed at 4.4V when VDD is from 2.4V to 3.6V. 13 September 8, 1999 HTG12B0 Oscillator V D D Only one external resistor is required for the HTG12B0 system clock. W a k e -u p The system clock is also used as the reference signal of the sound effect clock or internal frequency source of the TIMER. W a k e -u p m a s k o p tio n P u ll- h ig h m a s k o p tio n Another crystal oscillator is needed for use as the reference signal of the LCD driving clock and RTC interrupt clock source. In te rn a l b u s Input ports PS, PM A machine cycle consists of a sequence of 4 states numbered T1 to T4. Each state lasts for one oscillator period. The machine cycle is 4ms if the system frequency is up to 1MHz. O S C I PM3 has a falling edge latch function selected by mask option. Once the falling edge signal is latched, it will remain in its state until the clear instruction is executed by setting bit 2 of LCDC from high to low. X IN R Input/output port - PA, PB 3 2 .7 6 8 k H z O S C O R e a d c o n tro l PA and PB can be used for input/output or output operation by selecting NMOS or CMOS mask option respectively, and each bit can be configured with or without pull-high resistor when the NMOS is selected. If the NMOS is selected, it should be noted that, before reading, data from pads should output ²1² to the related bits to disable the NMOS device. X O U T RC and RTC oscillator Interfacing The HTG12B0 microcontrollers communicate with the outside world through two input pins PS and PM and two output pins PA and PB. V D D P u ll- h ig h Input ports - PS, PM In te rn a l b u s All of the ports can have internal pull high resistors determined by mask option. Every bit of the input ports PS and PM can be specified as a trigger source for waking up the HALT interrupt by mask option. A high to low transition on one of these pins will wake up the device from a HALT status. M a s k o p tio n Q C K Q M a s k o p tio n D R e a d c o n tro l Input/output port PA, PB 14 September 8, 1999 HTG12B0 Mask options · Six kinds of sound clock frequencies: HTG12B0 provides the following mask option for different applications. · There are eight kinds of RTC interrupt fre- fSYS/2m, m=0, 1, 2, 3, 4, 5 quencies. RTC interrupt frequency=256/2n Hz, n=0~7. · Each bit of input ports PS, PM with pull-high resistor · LCD clock source division: · Each bit of input ports PS, PM function as If RTC OSC is selected, the frequency of LCD clock=16384/2n Hz, n=0~7. If system clock is selected, the frequency of f 64 Hz, n=0~5. LCD clock= SYS n 2 HALT wake-up trigger. · Each bit of input/output port PA, PB with CMOS or NMOS with pull-high or none. · 8-bit programmable TIMER with internal or external frequency sources. There are 14 internal frequency sources which can be selected as a clocking signal. If using internal frequency sources as clocking signal TMCLK cannot connect with pull-high resistor. · PM3 falling edge latch function. 15 September 8, 1999 HTG12B0 Application Circuits P A 0 P A 1 P A 2 C O M 0 I/O C O M 1 P O R T P A 3 P M 0 P M 1 P M 2 L P a (1 /4 1 /1 6 IN P U T P O R T C O M 1 5 P M 3 S E G M E N T O U T P U T P S 0 P S 1 P S 2 P S 3 X 4 0 IN P U T P O R T 0 6 / * B Z P ie z o B u z z e r B Z R * 0 .1 m F O S C I R E S V O U T 1 O S C O X 'ta V O U T 2 V O U T 3 V O U T 4 l X IN P B 0 P B 1 P B 2 C D tte rn B ia s , D u ty ) X O U T V L C 1 I/O V L C 2 V L C 3 P O R T P B 3 V L C 4 R * : D e p e n d s o n th e r e q u ir e d s y s te m c lo c k fr e q u e n c y . ( R = 6 2 0 k W ~ 5 1 k W , a t V X 't a l: R e a lt im e c lo c k f r e q u e n c y . ( X 't a l= 3 2 7 6 8 H z ) 16 D D = 3 V ) September 8, 1999 HTG12B0 Instruction Set Summary Mnemonic Description Byte Cycle CF Add data memory to ACC Add data memory with carry to ACC Subtract data memory from ACC Subtract data memory from ACC with borrow Add immediate data to ACC Subtract immediate data from ACC Decimal adjust ACC for addition 1 1 1 1 2 2 1 1 1 1 1 2 2 1 Ö Ö Ö Ö Ö Ö Ö AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 2 2 2 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Increment ACC Increment register, n=0~4 Increment data memory Increment data memory Decrement ACC Decrement register, n=0~4 Decrement data memory Decrement data memory 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ MOV ACC to ROMB MOV ACC to RAMB MOV ACC to LCDC Move register to ACC, n=0~4 Move ACC to register, n=0~4 Move data memory to ACC Move data memory to ACC Move ACC to data memory Move ACC to data memory Move immediate data to ACC Move immediate data to R1 and R0 Move immediate data to R3 and R2 Move immediate data to R4 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Arithmetic ADD A,[R1R0] ADC A,[R1R0] SUB A,[R1R0] SBC A,[R1R0] ADD A,XH SUB A,XH DAA Logic Operation AND A,[R1R0] OR A,[R1R0] XOR A,[R1R0] AND [R1R0],A OR [R1R0],A XOR [R1R0],A AND A,XH OR A,XH XOR A,XH Increment and Decrement INC A INC Rn INC [R1R0] INC [R3R2] DEC A DEC Rn DEC [R1R0] DEC [R3R2] Data Move MOV ROMB, A MOV RAMB, A MOV LCDC, A MOV A,Rn MOV Rn,A MOV A,[R1R0] MOV A,[R3R2] MOV [R1R0],A MOV [R3R2],A MOV A,XH MOV R1R0,XXH MOV R3R2,XXH MOV R4,XH 17 September 8, 1999 HTG12B0 Mnemonic Description Byte Cycle CF Rotate ACC left Rotate ACC left through carry Rotate ACC right Rotate ACC right through carry 1 1 1 1 1 1 1 1 Ö Ö Ö Ö Input port-i to ACC ,port-i=PM, PS, PA, PB Output ACC to port-i, port-i=PA, PB 1 1 1 1 ¾ ¾ Jump unconditionally Jump on carry=1 Jump on carry=0 Jump on timer overflow Jump on ACC bit n=1 Jump on ACC is zero Jump on ACC is not zero Jump on register Rn not zero, n=0,1,4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Subroutine call Return from subroutine or interrupt Return from interrupt service routine 2 1 1 2 1 1 ¾ ¾ Ö Clear carry flag Set carry flag Enable interrupt Disable interrupt No operation 1 1 1 1 1 1 1 1 1 1 0 1 ¾ ¾ ¾ Set 8 bits immediate data to TIMER Set TIMER start counting Set TIMER stop counting Move low nibble of TIMER to ACC Move high nibble of TIMER to ACC Move ACC to low nibble of TIMER Move ACC to high nibble of TIMER 2 1 1 1 1 1 1 2 1 1 1 1 1 1 ¾ ¾ ¾ ¾ ¾ ¾ ¾ Read ROM code of current page to R4 and ACC Read ROM code of current page to M(R1,R0), ACC Read ROM code of page F to R4 and ACC Read ROM code of page F to M(R1,R0), ACC 1 1 1 1 2 2 2 2 ¾ ¾ ¾ ¾ Rotate RL A RLC A RR A RRC A Input & Output IN A,Pi OUT Pi,A Branch JMP addr JC addr JNC addr JTMR addr JAn addr JZ A,addr JNZ A,addr JNZ Rn,addr Subroutine CALL addr RET RETI Flag CLC STC EI DI NOP Timer TIMER XXH TIMER ON TIMER OFF MOV A,TMRL MOV A,TMRH MOV TMRL,A MOV TMRH,A Table Read READ R4A READ MR0A READF R4A READF MR0A 18 September 8, 1999 HTG12B0 Mnemonic Description Byte Cycle CF Activate SOUND channel with ACC Turn on SOUND one cycle Turn on SOUND repeat cycle Turn off SOUND 1 1 1 1 1 1 1 1 ¾ ¾ ¾ ¾ Enter power down mode 2 2 ¾ Sound Control SOUND A SOUND ONE SOUND LOOP SOUND OFF Miscellaneous HALT 19 September 8, 1999 HTG12B0 Instruction Definition ADC A,[R1R0] Add data memory contents and carry to accumulator Machine Code 00001000 Description The contents of the data memory addressed by the register pair ²R1,R0² and the carry are added to the accumulator. Carry is affected. Operation ACC ¬ ACC+M(R1,R0)+C ADD A,XH Add immediate data to accumulator Machine Code 01000000 0000dddd Description The specified data is added to the accumulator. Carry is affected. Operation ACC ¬ ACC+XH ADD A,[R1R0] Add data memory contents to accumulator Machine Code 00001001 Description The contents of the data memory addressed by the register pair ²R1,R0² is added to the accumulator. Carry is affected. Operation ACC ¬ ACC+M(R1,R0) AND A,XH Logical AND immediate data to accumulator Machine Code 01000010 Description Data in the accumulator is logically AND with the immediate data specified by code. Operation ACC ¬ ACC ²AND² XH AND A,[R1R0] Logical AND accumulator with data memory 0000dddd Machine Code 00011010 Description Data in the accumulator is logically AND with the data memory addressed by the register pair ²R1,R0². Operation ACC ¬ ACC ²AND² M(R1,R0) AND [R1R0],A Logical AND data memory with accumulator Machine Code 00011101 Description Data in the data memory addressed by the register pair ²R1,R0² is logically AND with the accumulator Operation M(R1,R0) ¬ M(R1,R0) ²AND² ACC 20 September 8, 1999 HTG12B0 CALL address Subroutine call Machine Code 1111aaaa Description The program counter bits 0-11 are saved in the stack. The program counter is then loaded from the directly-specified address. Operation Stack ¬ PC+2 PC ¬ address CLC Clear carry flag Machine Code 00101010 Description The carry flag is reset to zero. Operation C¬0 DAA Decimal-Adjust accumulator Machine Code 00110110 Description The accumulator value is adjusted to the BCD (Binary Code Decimal) code, if the contents of the accumulator is greater, then 9 or C (Carry flag) is one. Operation If ACC>9 or CF=1 then ACC ¬ ACC+6, C ¬ 1 else ACC ¬ ACC, C ¬ C DEC A Decrement accumulator Machine Code 00111111 Description Data in the accumulator is decremented by one. Carry flag is not affected. Operation ACC ¬ ACC-1 DEC Rn Decrement register Machine Code 0001nnn1 Description Data in the working register ²Rn² is decremented by one. Carry flag is not affected. Operation Rn ¬ Rn-1; Rn=R0, R1, R2, R3, R4, for n=0,1,2,3,4 DEC [R1R0] Decrement data memory Machine Code 00001101 Description Data in the data memory specified by the register pair ²R1,R0² is decremented by one. Carry flag is not affected. Operation M(R1, R0) ¬ M(R1,R0)-1 aaaaaaaa 21 September 8, 1999 HTG12B0 DEC [R3R2] Decrement data memory Machine Code 00001111 Description Data in the data memory specified by the register pair ²R3, R2² is decremented by one. Carry flag is not affected. Operation M(R3,R2) ¬ M(R3,R2)-1 DI Disable interrupt Machine Code 00100101 Description Internal time-out interrupt and external interrupt are disabled. EI Enable interrupt Machine Code 00100101 Description Internal time-out interrupt and external interrupt are enabled. HALT Halt system clock Machine Code 00110111 00000011 00000010 00111110 Description Turn off system clock, and enter power down mode. Operation PC ¬ (PC)+1 IN A,Pi Input port to accumulator Machine Code 00101100 PA 01001000 PB 00110010 PM 00110011 PS Description The data on port ²Pi² is transferred to the accumulator. Operation ACC ¬ Pi; Pi=PA, PB, PM or PS INC A Increment accumulator Machine Code 00110001 Description Data in the accumulator is incremented by one. Carry flag is not affected. Operation ACC ¬ ACC+1 INC Rn Increment register Machine Code 0001nnn0 Description Data in the working register ²Rn² is incremented by one. Carry flag is not affected. Operation Rn ¬ Rn+1; Rn=R0,R1,R2,R3,R4 for n=0,1,2,3,4 22 September 8, 1999 HTG12B0 INC [R1R0] Increment data memory Machine Code 00001100 Description Data in the data memory specified by the register pair ²R1,R0² is incremented by one. Carry flag is not affected. Operation M(R1,R0) ¬ M(R1,R0)+1 INC [R3R2] Increment data memory Machine Code 00001110 Description Data memory specified by the register pair ²R3, R2² is incremented by one. Carry flag is not affected. Operation M(R3,R2) ¬ M(R3,R2)+1 JAn address Jump if accumulator Bit n is set Machine Code 100nnaaa Description Bits 0-10 of the program counter are replaced with the directly¢specified address, bit 11 of the program counter and PA3 of memory bank remain, if accumulator bit n is set to one. Operation PC (bit 0-10) ¬ address, if ACC bit n=1 (n = 0, 1, 2, 3) PC ¬ PC+2, if ACC bit n=0 JC address Jump if carry is set Machine Code 11000aaa Description Bits 0-10 of the program counter are replaced with the directly¢specified address, bit 11 of the program counter and PA3 of memory bank remain, if the C (Carry flag) is set to one. Operation PC (bit 0-10) ¬ address, if C=1 PC ¬ PC+2, if C=0 JMP address Direct Jump Machine Code 1110aaaa Description Bits 0-11 of the program counter are replaced with the directly¢specified address. Operation PC ¬ address JNC address Jump if carry is not set Machine Code 11001aaa Description Bits 0-10 of the program counter are replaced with the directly¢specified address, bit 11 of the program counter and PA3 of memory bank remain, if the C (Carry flag) is set to zero. Operation PC (bit 0-10) ¬ address, if C=0 PC ¬ PC+2, if C=1 aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa 23 September 8, 1999 HTG12B0 JNZ A,address Jump if accumulator is not zero Machine Code 10111aaa Description Bits 0-10 of the program counter are replaced with the directly¢specified address, bit 11 of the program counter and PA3 of memory bank remain, if the accumulator is not zero. Operation PC (bit 0-10) ¬ address, if ACC¹0 PC ¬ PC+2, if ACC=0 JNZ Rn,address Jump if register is not zero Machine Code 10100aaa aaaaaaaa R0 10101aaa aaaaaaaa R1 11011aaa aaaaaaaa R4 aaaaaaaa Description Bits 0-10 of the program counter are replaced with the directly¢specified address, bit 11 of the program counter and PA3 of memory bank remain, if the register is not zero. Operation PC (bit 0-10) ¬ address, if Rn¹0; Rn=R0, R1, R4 PC ¬ PC+2, if Rn=0 JTMR address Jump if time-out Machine Code 11010aaa Description Bits 0-10 of the program counter are replaced with the directly¢specified address, bit 11 of the program counter and PA3 of the memory bank remain, if the TF (Timer flag) is set to one. Operation PC (bit 0-10) ¬ address, if TF=1 PC ¬ PC+2, if TF=0 JZ A,address Jump if accumulator is zero Machine Code 10110aaa Description Bits 0-10 of the program counter are replaced with the directly¢specified address, bit 11 of the program counter and PA3 of the memory bank remain, if the accumulator is zero. Operation PC (bit 0-10) ¬ address, if ACC=0 PC ¬ PC+2, if ACC¹0 MOV A,Rn Move register to accumulator Machine Code 0010nnn1 Description Data in the working register ²Rn² is moved to the accumulator. Operation ACC ¬ Rn; Rn=R0, R1, R2, R3, R4, for n=0,1,2,3,4 aaaaaaaa aaaaaaaa 24 September 8, 1999 HTG12B0 MOV A,TMRH Move timer to accumulator Machine Code 00111011 Description The high nibble data of the Timer counter is loaded to the accumulator. Operation ACC ¬ TIMER (high nibble) MOV A,TMRL Move timer to accumulator Machine Code 00111010 Description The low nibble data of Timer counter is loaded to the accumulator. Operation ACC ¬ TIMER (low nibble) MOV A,XH Move immediate data to accumulator Machine Code 0111dddd Description The 4-bit data specified by code is loaded to the accumulator. Operation ACC ¬ XH MOV A,[R1R0] Move data memory to accumulator Machine Code 00000100 Description Data in the data memory specified by the register pair ²R1,R0² is moved to the accumulator. Operation ACC ¬ M(R1,R0) MOV A,[R3R2] Move data memory to accumulator Machine Code 00000110 Description Data in the data memory specified by the register pair ²R3, R2² is moved to the accumulator. Operation ACC ¬ M(R3,R2) MOV LCDC, A Move accumulator to LCDC register Machine Code 00110000 Description Data in the accumulator is moved to the LCDC register. Operation LCDC ¬ ACC MOV R1R0,XXH Move immediate data to R1 and R0 Machine Code 0101dddd Description The 8-bit data specified by code are loaded to the working registers R1 and R0, the high nibble of the data is loaded to R1, and the low nibble of the data is loaded to R0. Operation R1 ¬ XH (high nibble) R0 ¬ XH (low nibble) 0000dddd 25 September 8, 1999 HTG12B0 MOV R3R2,XXH Move immediate data to R3 and R2 Machine Code 0110dddd Description The 8-bit data specified by code are loaded to the working register R3 and R2, the high nibble of the data is loaded to the R3, and the low nibble of the data is loaded to the R2. Operation R3 ¬ XH (high nibble) R2 ¬ XH (low nibble) MOV R4,XH Move immediate data to R4 Machine Code 01000110 0000dddd 0000dddd Description The 4-bit data specified by code are loaded to the working register R4. Operation R4 ¬ XH MOV Rn,A Move accumulator to register Machine Code 0010nnn0 Description Data in the accumulator is moved to the working register ²Rn². Operation Rn ¬ ACC; Rn=R0, R1, R2, R3, R4, for n=0, 1, 2, 3, 4 MOV RAMB, A Move accumulator to RAMB register Machine Code 00110100 Description Data in the accumulator is moved to the RAMB register Operation RAMB ¬ ACC MOV ROMB, A Move accumulator to ROMB register Machine Code 00110101 Description Data in the accumulator is moved to the ROMB register Operation ROMB ¬ ACC MOV TMRH,A Move accumulator to timer Machine Code 00111101 Description The contents of accumulator is loaded to the high nibble of timer counter. Operation TIMER (high nibble) ¬ ACC MOV TMRL,A Move accumulator to timer Machine Code 00111100 Description The contents of accumulator is loaded to the low nibble of the timer counter. Operation TIMER (low nibble) ¬ ACC 26 September 8, 1999 HTG12B0 MOV [R1R0],A Move accumulator to data memory Machine Code 00000101 Description Data in the accumulator is moved to the data memory specified by the register pair ²R1,R0². Operation M(R1,R0) ¬ ACC OV [R3R2],A Move accumulator to data memory Machine Code 00000111 Description Data in the accumulator is moved to the data memory specified by the register pair ²R3, R2². Operation M(R3,R2) ¬ ACC NOP No operation Machine Code 00111110 Description Do nothing, but one instruction cycle is delayed. OR A,XH Logical OR immediate data to accumulator Machine Code 01000100 Description Data in the accumulator is logically OR with the immediate data specified by code. Operation ACC ¬ ACC ²OR² XH OR A,[R1R0] Logical OR accumulator with data memory 0000dddd Machine Code 00011100 Description Data in the accumulator is logically OR with the data memory addressed by the register pair ²R1,R0². Operation ACC ¬ ACC ²OR² M(R1,R0) OR [R1R0],A Logical OR data memory with accumulator Machine Code 00011111 Description Data in the data memory addressed by the register pair ²R1,R0² is logically OR with the accumulator. Operation M(R1,R0) ¬ M(R1,R0) ²OR² ACC OUT Pi,A Output accumulator data to port-i Machine Code 00101101 Description The data in the accumulator is transferred to the port-i and latched. Operation Pi ¬ ACC; Pi=PA or PB PA 01001001 27 PB September 8, 1999 HTG12B0 READ MR0A Read ROM code of current page to M(R1,R0) and ACC Machine Code 01001101 Description The 8-bit ROM code (current page) addressed by ACC and R4 are moved to the data memory M(R1,R0) and accumulator. The high nibble of the ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to accumulator. The address of ROM code are specified as below: Current page ® ROM code address bit 12~8 ACC ® ROM code address bit 7~4 R4 ® ROM code address bit 3~0 Operation M(R1,R0) ¬ ROM code (high nibble) ACC ¬ ROM code (low nibble) READ R4A Read ROM code of current page to R4 and accumulator Machine Code 01001100 Description The 8-bit ROM code (current page) addressed by ACC and M(R1,R0) are moved to the working register R4 and accumulator. The high nibble of the ROM code is loaded to R4 and the low nibble of the ROM code is loaded to the accumulator. The address of the ROM code are specified below: Current page ® ROM code address bit 12~8 ACC ® ROM code address bit 7~4 M(R1,R0) ® ROM code address bit 3~0 Operation R4 ¬ ROM code (high nibble) ACC ¬ ROM code (low nibble) READF MR0A Read ROM Code of page F to M(R1,R0) and ACC Machine Code 01001111 Description The 8-bit ROM code (page F) addressed by ACC and R4 are moved to the data memory M(R1,R0) and the accumulator. The high nibble of the ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to accumulator. page F ® ROM code address bit 12~8 are ²PA3 1111² ACC ® ROM code address bit 7~4 R4 ® ROM code address bit 3~0 Operation M(R1,R0) ¬ high nibble of ROM code (page F) ACC ¬ low nibble of ROM code (page F) 28 September 8, 1999 HTG12B0 READF R4A Read ROM code of page F to R4 and accumulator Machine Code 01001110 Description The 8-bit ROM code (page F) addressed by ACC and M(R1,R0) are moved to the working register R4 and accumulator. The high nibble of the ROM code is loaded to R4 and the low nibble of the ROM code is loaded to accumulator. page F ® ROM code address bit 12~8 are ²PA3 1111² ACC ® ROM code address bit 7~4 M(R1,R0) ® ROM code address bit 3~0 Operation R4 ¬ high nibble of ROM code (page F) ACC ¬ low nibble of ROM code (page F) RET Return from subroutine or interrupt Machine Code 00101110 Description The program counter bits 0~11 are restored from the stack. Operation PC ¬ Stack RETI Return from interrupt subroutine Machine Code 00101111 Description The program counter bits 0~11 are restored from the stack. The carry flag before entering interrupt service routine is restored. Operation PC ¬ Stack C ¬ C (before interrupt service routine) RL A Rotate accumulator left Machine Code 00000001 Description The contents of the accumulator are rotated one bit left. Bit 3 is rotated to bit 0 and carry flag. Operation An+1 ¬ An; An: accumulator bit n (n=0,1,2) A0 ¬ A3 C ¬ A3 RLC A Rotate accumulator left through carry Machine Code 00000011 Description The contents of the accumulator are rotated one bit left. Bit 3 replaces the carry bit; the carry bit is rotated into the bit 0 position. Operation An+1 ¬ An; An: Accumulator bit n (n=0,1,2) A0 ¬ C C ¬ A3 29 September 8, 1999 HTG12B0 RR A Rotate accumulator right Machine Code 00000000 Description The contents of the accumulator are rotated one bit right. Bit 0 is rotated to bit 3 and carry flag. Operation An ¬ An+1; An: Accumulator bit n (n=0,1,2) A3 ¬ A0 C ¬ A0 RRC A Rotate accumulator right through carry Machine Code 00000010 Description The contents of the accumulator are rotated one bit right. Bit 0 replaces the carry bit; the carry bit is rotated into the bit 3 position. Operation An ¬ An+1; An: Accumulator bit n (n=0,1,2) A3 ¬ C C ¬ A0 SBC A,[R1R0] Subtract data memory contents and carry from ACC Machine Code 00001010 Description The contents of the data memory addressed by the register pair ²R1,R0² and the carry are subtracted from the accumulator. Carry is affected. Operation ACC ¬ ACC+M(R1,R0)+CF SOUND A Active SOUND channel with accumulator Machine Code 01001011 Description The activated sound begins playing in accordance with the contents of accumulator when the specified sound channel is matched. SOUND LOOP Turn on sound repeat mode Machine Code 01001001 Description The activated sound plays repeatedly. SOUND OFF Turn off sound Machine Code 01001010 Description The singing sound will terminate immediately. SOUND ONE Turn on sound one mode Machine Code 01000101 Description The activated sound plays only one time. 00000001 00000000 30 September 8, 1999 HTG12B0 STC Set carry flag Machine Code 00101011 Description The carry flag is set to one. Operation C¬1 SUB A,XH Subtract immediate data from accumulator Machine Code 01000001 0000dddd Description The specified data is subtracted from the accumulator. Carry is affected. Operation ACC ¬ ACC+XH+1 SUB A,[R1R0] Subtract data memory contents from accumulator Machine Code 00001011 Description The contents of the data memory addressed by the register pair ²R1,R0² is subtracted from the accumulator. Carry is affected. Operation ACC ¬ ACC+M(R1,R0)+1 TIMER OFF Set timer stop counting Machine Code 00111001 Description The Timer stop counting, when the ²TIMER OFF² instruction is executed. TIMER ON Set timer start counting Machine Code 00111000 Description The Timer starts counting, when the ²TIMER ON² instruction is executed. TIMER XXH Set immediate data to timer counter Machine Code 01000111 Description The 8 bit data specified by code is loaded to the T imer counter. Operation TIMER ¬ XXH XOR A,XH Logical XOR immediate data to accumulator Machine Code 01000011 Description Data in the accumulator is Exclusive-OR with the immediate data specified by code. Operation ACC ¬ ACC ²XOR² XH dddddddd 0000dddd 31 September 8, 1999 HTG12B0 XOR A,[R1R0] Logical XOR accumulator with data memory Machine Code 00011011 Description Data in the accumulator is Exclusive-OR with the data memory addressed by the register pair ²R1,R0². Operation ACC ¬ ACC ²XOR² M(R1,R0) XOR [R1R0],A Logical XOR data memory with accumulator Machine Code 00011110 Description Data in the data memory addressed by the register pair ²R1,R0² is logically Exclusive-OR with the accumulator. Operation M(R1,R0) ¬ M(R1,R0) ²XOR² ACC 32 September 8, 1999 HTG12B0 Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Microelectronics Enterprises Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright ã 1999 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. 33 September 8, 1999