HI-8010/HI-8110 Series January 2001 GENERAL DESCRIPTION The HI-8010 & HI-8110 high voltage display drivers are constructed of MOS P Channel and N Channel enhancement mode devices in a single monolithic structure. They are designed to drive high voltage liquid crystal displays by converting low level input signals (TTL on the HI-8010 and CMOS on the HI-8110) to high voltage drive signals. Both devices can drive up to 38 segments and require minimal display-to-data source interfacing. Serial data is loaded and held in internal latches until new display data is received. The HI-8010 & HI-8110 are available in a variety of ceramic and plastic packaging including DIP; leaded and leadless chip carriers; and J-lead and gull-wing quad flat packs. PIN CONFIGURATION (Top View) LD DIN LCDØ LCDØOPT VDD S37 S38 S1 S2 S3 S4 S5 S6 2 3 4 5 6 7 8 9 10 11 12 HI-8010PQI HI-8110PQI HI-8010PQT & HI-8110PQT 52 - PIN PLASTIC QFP 39 38 37 36 35 34 33 32 31 30 29 28 S26 S25 S24 S23 S22 S21 S20 DOUT 38 N/C N/C N/C BP S19 FEATURES (See page 3-6 for additional package pin configurations) ! 5 volt input translated to 30 volts or less ! Pin-out adaptable to drive 30, 32 or 38 LCD segments ! RC oscillator or high voltage (BP) clock input ! TTL compatible inputs (HI-8010 only) FUNCTIONAL BLOCK DIAGRAM ! CMOS compatible inputs (HI-8110 only) ! Low power consumption ! Industrial (-40°C to +85°C) & Military (-55°C to +125°C) temperature ranges ! Pin for pin compatible with the Micrel MIC8010/8011 series and the AMI S4520 series drivers ! Cascadable ! Military level processing available DIN Þ CL Þ DATA IN 38 Stage Shift Register CLK CS Þ LE LD Þ LCDØ Þ LCDØ OPT Þ Oscillator Divider Voltage Translator ! Dichroic Liquid Crystal Displays Þ DOUT 38 Þ DOUT 32 Þ DOUT 30 38 Bit Latch Voltage Translators High Voltage Drivers H i g h Voltage Buffer Þ BP ! Standard Liquid Crystal Displays SEGMENTS ! Vacuum Fluorescent Displays (DS8010, Rev. C) HOLT INTEGRATED CIRCUITS 3-3 01/01 HI-8010/HI-8110 Series FUNCTIONAL DESCRIPTION Whenever a Logic "0" is applied to the Chip Select (CS) input, one bit of data is clocked into the shift register from the serial data input (DIN) with each negative transition of the Clock (CL) input. CS is internally tied to VSS on some versions. A Logic "1" present at the Load (LD) input will cause a parallel transfer of data from the shift register to the data latch. If the Load (LD) input is held high while data is clocked into the shift register, the latch will be transparent. All four logic inputs are TTL compatible on the HI-8010 and CMOS compatible on the HI-8110. on the rising edge of the Clock (CL). Clock (CL), Load (LD) and Chip Select (CS) should be tied in common with each other, respectively, between all cascaded display drivers. INTERNAL OSCILLATOR CIRCUIT To display segments, a Logic "1" is stored in the appropriate shift register bit position, and the segment output is out-ofphase with the backplane. The backplane output functions in 1 of 2 modes; externally driven or self-oscillating. When the LCDØ input is externally driven with the LCDØOPT input open circuit (Figure 2), the backplane output will be in-phase with LCDØ. Utilizing the self-oscillating mode, inputs LCDØ and LCDØOPT are tied together and connected to an RC circuit (Figure 3). A 150KW resistor with a 470pF capacitor generates an approximate backplane frequency of 100Hz. The LCDØ/LCDØOPT oscillator frequency is divided by 256 to determine the backplane output frequency. The resistor value (R) must be at least 30KW for proper self-oscillator operation. ÷ 256 Q LCDØ LCDØ OPT TO BACKPLANE TRANSLATOR AND DRIVER For displays having a number of segments greater than 38, two or more of the display drivers may be cascaded together by connecting the serial data output (DOUT) from the first driver, to the serial data input (DIN) of the following driver, etc. (See Figures 2 & 3). Data out (DOUT) will change state Figure 1 TIMING DIAGRAM CL INPUT tCL DIN INPUT VALID tDS tDH CS INPUT tCSS tLCS tCSL tCSH LD INPUT tCDO DOUT OUTPUT tLS VALID HOLT INTEGRATED CIRCUITS 3-4 tLW HI-8010/HI-8110 Series ABSOLUTE MAXIMUM RATINGS Voltages referenced to VSS = 0V Supply Voltage VDD........................ 0V to 7V VEE................VDD-35V to 0V Voltage at any input, except LCDØ..-0.3 to VDD+0.3V Voltage at LCDØ input...............VDD-35 to VDD+0.3V DC Current any input pin...................................10 mA Power Dissipation......................................................300 mW Operating Temperature Range - Industrial........-40° to +85°C Operating Temperature Range - Hi-Temp/Mil..-55° to +125°C Storage Temperature Range...........................-65° to +150°C NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYMBOL CONDITION MIN 3.0 TYP MAX UNITS 7.0 V Operating Voltage VDD Supply Current IDD Static, No Load 200 µA IEE Static, No Load fBP=100Hz 150 µA Input Low Voltage, HI-8010 (except LCDØ) VILTTL 0 0.8 V Input High Voltage, HI-8010 (except LCDØ) VIHTTL 2 VDD V Input Low Voltage, HI-8110 (except LCDØ) VILCMOS 0 0.3 VDD V Input High Voltage, HI-8110 (except LCDØ) VIHCMOS 0.7 VDD VDD V Input Low Voltage (LCDØ) VILX VEE 3 V Input High Voltage (LCDØ) VIHX 3.5 VDD V 1 µA 5 pF Input Current IIN Input Capacitance (not tested) CI VIN = 0 to 5V RSEG IL = 10µA 10,000 W Backplane Output Impedance RBP IL = 10µA 450 W Data Out Current: IDOH Source Current, VOH = 4.5V -0.6 mA IDOL Sink Current, VOL = 0.5V Segment Output Impedance 0.6 mA AC ELECTRICAL CHARACTERISTICS VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYMBOL VDD MIN TYP MAX UNITS Clock Period tCL 5V 1200 ns Clock Pulse Width tCW 5V 520 ns Data In - Setup tDS 5V 50 ns Data In - Hold tDH 5V 400 ns Chip Select - Setup to Clock tCSS 5V 200 ns Chip Select - Hold to Clock tCSH 5V 450 ns Load - Setup to Clock tLS 5V 500 ns Chip Select - Setup to Load tCSL 5V 300 ns Load Pulse Width tLW 5V 500 ns Chip Select - Hold to Load tLCS 5V 300 Data Out Valid, from Clock tCDO 5V HOLT INTEGRATED CIRCUITS 3-5 ns 800 ns HI-8010/HI-8110 Series CASCADING - EXT. OSCILLATOR CASCADING - RC OSCILLATOR LD CL CS LD CL CS CS DIN CL LD DOUT HI-8010J-85 CS DIN CL LD DOUT CS DIN HI-8010J-85 CL LD DOUT CS DIN 150KW HI-8010J-85 CL LD DOUT HI-8110PQI BP LCDØ LCDØ BP LCDØ BP LCDØ BP LCDØ OPT CS DIN CL CS DIN LD DOUT LD DOUT HI-8110PQI HI-8110PQI LCDØ CL BP LCDØ LCDØ OPT BP LCDØ OPT 470pf SEGMENTS 1 - 32 SEGMENTS BACK 33 - 64 PLANE SEGMENTS 1 - 38 SEGMENTS 65 - 96 Figure 2 SEGMENTS BACK 39 - 76 PLANE SEGMENTS 77 - 114 Figure 3 ADDITIONAL HI-8010/HI-8110 PIN CONFIGURATIONS (See page 3-3 for 52-Pin Plastic QFP) S27 S28 S29 S30 S31 S32 N/C VSS CS CL LD LCDØOPT VDD S1 S2 S3 S4 S5 S6 S7 S8 11 12 13 14 15 16 34 10 12 13 33 32 31 30 11 40 - PIN CERAMIC LCC HI-8010J-85 & HI-8110J-85 44 - PIN PLASTIC PLCC 17 35 9 38 10 7 HI-8010SM-36 & HI-8110SM-36 39 8 9 6 8 7 29 28 14 27 15 26 37 36 35 34 33 32 31 30 29 S25 S24 S23 S22 S21 S20 DOUT 30 BP S19 S18 LCDØ LCDØOPT VDD S37 S38 S1 S2 S3 S4 S5 S6 S7 S17 S16 S15 VEE S14 S13 S12 S11 S10 S9 S8 7 42 8 41 9 10 11 12 HI-8010SM-32 & HI-8110SM-32 15 16 17 18 HOLT INTEGRATED CIRCUITS 3-6 39 38 37 36 13 14 40 48 - PIN CERAMIC LCC 35 34 33 32 S28 S27 S26 S25 S24 S23 S22 S21 S20 DOUT 38 BP S19 HI-8010/HI-8110 Series ORDERING INFORMATION PART NUMBER NUMBER OF SEGMENTS MASTER /SLAVE PACKAGE DESCRIPTION TEMPERATURE BURN LEAD RANGE FLOW IN FINISH TTL Logic Inputs HI-8010J-85 HI-8010PQI 32 38 BOTH BOTH 44 PIN PLASTIC J LEAD 52 PIN PLASTIC QUAD FLAT PACK (PQFP) -40°C TO +85°C -40°C TO +85°C I I NO NO SOLDER SOLDER HI-8010PQT 38 BOTH 52 PIN PLASTIC QUAD FLAT PACK (PQFP) -55°C TO +125°C HI-8010SM-32 HI-8010SM-36 38 30 BOTH BOTH 48 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C 40 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C T NO SOLDER M M YES SOLDER YES SOLDER 32 38 38 38 30 BOTH BOTH BOTH BOTH BOTH 44 PIN PLASTIC J LEAD 52 PIN PLASTIC QUAD FLAT PACK (PQFP) 52 PIN PLASTIC QUAD FLAT PACK (PQFP) 48 PIN CERAMIC LEADLESS CHIP CARRIER 40 PIN CERAMIC LEADLESS CHIP CARRIER I I T M M NO NO NO YES YES CMOS Logic Inputs HI-8110J-85 HI-8110PQI HI-8110PQT HI-8110SM-32 HI-8110SM-36 -40°C TO +85°C -40°C TO +85°C -55°C TO +125°C -55°C TO +125°C -55°C TO +125°C SOLDER SOLDER SOLDER SOLDER SOLDER SEMI-CUSTOM PACKAGING The above part numbers represent some of the typical configurations of the HI-8010 & HI-8110 products. They can also be provided with a varied number of output segments (30, 32 and 38), with either industrial or military screening and in a wide variety of packages. Listed below are currently available packages. Please contact the Holt Sales Department for your specific requirements. PACKAGE DESCRIPTION # LEADS PLASTIC DUAL-IN-LINE (PDIP) 40 48 PLASTIC QUAD FLAT PACK (PQFP) 52 PLASTIC J-LEAD CHIP CARRIER (PLCC) 44 CERAMIC DUAL-IN-LINE (CDIP) 40 48 CERAMIC LEADLESS CHIP CARRIER (LCC) 40 48 CERAMIC J-LEAD CHIP CARRIER 44 48 CERAMIC LEADED CHIP CARRIER 40 48 HOLT INTEGRATED CIRCUITS 3-7 HI-8010/HI-8110 Series SYMBOL FUNCTION VSS POWER DESCRIPTION 0 Volts CS INPUT Logic input Chip select CL INPUT Logic input Clocks shift register on negative edge and DOUT pins on positive edge LD INPUT Logic input Segment outputs equal shift register data if Load is high DIN INPUT Logic input Shift register data input LCD0 INPUT Analog input Display clock input and is always bonded out. Can swing from VEE to VDD LCD0OPT OUTPUT Analog output Bonded out only if an RC oscillator is required VDD POWER 5 Volts VEE POWER O Volts to -30 Volts DOUT OUTPUT Logic output Selected pinout can provide shift register taps at positions 30, 32, 34, or 38 BP OUTPUT Display drive output Low resistance drive for the backplane and swings from VDD to VEE Segments OUTPUT Display drive output High resistance drive for each segment and swings from VDD to VEE HOLT INTEGRATED CIRCUITS 3-8 HI-8010/HI-8110 PACKAGE DIMENSIONS inches (millimeters) 44-PIN PLASTIC PLCC Package Type: 44J PIN NO. 1 PIN NO. 1 IDENT .045 x 45° .045 x 45° .050 ± .005 (1.27 ± .127) .690 ± .005 (17.526 ± .127) SQ. .653 ± .004 (16.586 ± .102) SQ. .031± .005 (.787 ± .127) .017 ± .004 (.432 ± .102) SEE DETAIL A .009 .011 .015 ± .002 (.381 ± .051) .172 ± .008 (4.369 ± .203) .020 MIN (.508 ΜΙΝ) R .025 .045 DETAIL A .610 ± .020 (15.494± .508) 52-PIN PLASTIC QUAD FLAT PACK Package Type: 52PQS .0256 BSC (0.65 BSC) .520 ± .010 (13.2 ± .25) SQ. .394 ± .004 (10.00 ± .10) SQ. .012 ± .003 (.30 ± .08) .035 ± .006 (.88 ± .15) .088 ± .032 (1.6 ± .175) Typ. .008 (0.20) Min. .009 ± .003R (.225 ± .075R) See Detail A .092 ± .004 (2.32 ± .12) .079 ± .002 (2.00 ± .05) .009 R typ (0.23 R typ) HOLT INTEGRATED CIRCUITS 1 0° ≤ Θ ≤ 7° DETAIL A HI-8010/HI-8110 PACKAGE DIMENSIONS inches (millimeters) 40-PIN CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE: 40S PIN 1 IDENT. .085 MAX. (2.159 MAX.) .044 ± .011 (1.118 ± .280) PIN 1 IDENT. .484 ± .009 (12.294 ± .228) SQ. .020 ± .003 (.508 ± .076) .040 ± .003 (1.016 ± .076) 48-PIN CERAMIC LEADLESS CHIP CARRIER Package Type: 48S PIN 1 IDENT. .090 MAX. (2.286 MAX.) .040 ± .007 (1.016 ± .178) PIN 1 IDENT. .563 ± .009 (14.300 ± .228) SQ. .020 TYP. (.508 TYP.) HOLT INTEGRATED CIRCUITS 2 .040 TYP. (1.016 TYP.)