MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 D D D D D D D D D D Low Supply Voltage Range 2.5 V – 5.5 V Low Operation Current, 400 mA at 1 MHz, 3 V Ultra-Low Power Consumption Standby Mode: 2 µA RAM Retention Off Mode: 0.1 µA Five Power-Saving Modes Wake Up From Standby Mode in 6 µs 16-Bit RISC Architecture, 300 ns Instruction Cycle Time Single Common 32 kHz Crystal, Internal System Clock up to 3.8 MHz Integrated LCD Driver for up to 120 Segments Integrated Hardware Multiplier Performs Signed, Unsigned, and MAC Operations for Operands Up to 16 X 16 Bits Serial Communication Interface (USART), Select Asynchronous UART or Synchronous SPI by Software D D D D D D D Slope A/D Converter Using External Components 16-Bit Timer With Five Capture/Compare Registers Serial On-Board Programming Programmable Code Protection by Security Fuse Family Members Include: MSP430C336 – 24 KB ROM, 1 KB RAM MSP430C337 – 32 KB ROM, 1 KB RAM MSP430P337A – 32 KB OTP, 1 KB RAM EPROM Version Available for Prototyping: PMS430E337A Available in the following packages: 100 Pin Quad Flat-Pack (QFP), 100 Pin Ceramic Quad Flat-Pack (CFP) (EPROM Version) description The Texas Instruments MSP430 is an ultra-low power mixed signal microcontroller family consisting of several devices which features different sets of modules targeted to various applications. The controller is designed to be battery operated for an extended application lifetime. With the 16-bit RISC architecture, 16 integrated registers on the CPU, and a constant generator, the MSP430 achieves maximum code efficiency. The digital-controlled oscillator, together with the frequency lock loop (FLL), provides a wake up from a low-power mode to an active mode in less than 6 ms. The MSP430x33x series micro-controllers have built in hardware multiplication and communication capability using asynchronous (UART) and synchronous protocols. Typical applications of the MSP430 family include electronic gas, water, and electric meters and other sensor systems that capture analog signals, converts them to digital values, processes, displays, or transmits them to a host system. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 AVAILABLE OPTIONS PACKAGED DEVICES PLASTIC QFP (PJM) CERAMIC QFP (HFD) – 40°C to 85°C MSP430C336IPJM MSP430C337IPJM MSP430P337AIPJM — 25°C — PMS430E337AHFD TA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2/TACLK P3.3/TA0 P3.4/TA1 P3.5/TA2 P3.6/TA3 P3.7/TA4 P4.0 P4.1 P4.2/STE P4.3/SIMO P4.4/SOMI P4.5/UCLK P4.6/UTXD 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCC1 CIN TP0.0 TP0.1 TP0.2 TP0.3 TP0.4 TP0.5 P0.0 P0.1/RXD P0.2/TXD P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 VSS2 VCC2 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VSS1 Xin Xout/TCLK XBUF RST/NMI TCK TMS TDI/VPP TDO/TDI R33 R23 R13 R03 S29/O29/CMPI S28/O28 S27/O27 S26/O26 S25/O25 S24/O24 S23/O23 PJM or HFD PACKAGE (TOP VIEW) NC – No internal connection 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NC S22/O22 S21/O21 S20/O20 S19/O19 S18/O18 S17/O17 S16/O16 S15/O15 S14/O14 S13/O13 S12/O12 S11/O11 S10/O10 S9/O9 S8/O8 S7/07 S6/O6 S5/O5 S4/O4 S3/O3 S2/O2 S1 S0 COM0 COM1 COM2 COM3 VSS3 P4.7/URXD POST OFFICE BOX 655303 TCK TMS TDO/TDI TDI/VPP Test JTAG CPU Incl. 16 Reg. ACLK Oscillator FLL System Clock Multiplier MPY MPYS MAC 16x16 Bit 8x8 Bit MDB, 16 Bit MAB, 16 Bit MCLK XBUF Xout XIN VCC2 • DALLAS, TEXAS 75265 15/16 Bit Watchdog timer C: ROM P: OTP E: EPROM 24/32 kB ROM 32 kB OPT or EPROM VCC1 VSS3 TACLK TA0–4 16 Bit PWM TimerA UTXD URXD UCLK STE SIMO SOMI UART or SPI Function P4.7 TXD RXD 8 Bit Timer/Counter 1x8 Digital I/O’s I/O Port P4.0 USART USART MDB, 8 Bit MCB MAB, 4 Bit Reset SRAM Power-on- RST/NMI RAM Bus Conv VSS2 1024B VSS1 8 8 Timer/Port TP0.0–0.5 CIN 6 A/D Conv. Timer, O/P Applications TimerA 2 Int. Vectors 2x8 I/O’s All Interr. Cap. I/O Port P1.x P2.x CMPI f LCD Basic Timer1 1x8 Digital I/O’s RXD, TXD P3.7 I/O Port P3.0 P0.7 R03 R23 R13 R33 1, 2, 3, 4 MUX 120 Segments LCD 3 Int. Vectors 8 I/O’s, All With Interr. Cap. I/O Port P0.0 Com0–3 S0–28/O2–28 S29/O29/CMPI MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 functional block diagram 3 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 Terminal Functions TERMINAL NAME CIN COM0–3 NO. 2 I/O DESCRIPTION I Input port. CIN is used as an enable for counter TPCNT1 – (Timer/Port). 56–53 O Common outputs. COM0-3 are used for LCD backplanes – LCD P0.0 9 I/O General-purpose digital I/O P0.1/RXD 10 I/O General-purpose digital I/O, receive digital Input port – 8-bit Timer/Counter P0.2/TXD 11 I/O General-purpose digital I/O, transmit data output port – 8-bit Timer/Counter P0.3–P0.7 12–16 I/O Five general-purpose digital I/Os, bit 3-7 P1.0–P1.7 17–24 I/O Eight general-purpose digital I/Os, bit 0-7 P2.0–P2.7 25–27, 31–35 I/O Eight general-purpose digital I/Os, bit 0-7 P3.0, P3.1 36,37 I/O Two general-purpose digital I/Os, bit 0 and bit 1 P3.2/TACLK 38 I/O General-purpose digital I/O, clock input – Timer_A P3.3/TA0 39 I/O General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR0 P3.4/TA1 40 I/O General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR1 P3.5/TA2 41 I/O General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR2 P3.6/TA3 42 I/O General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR3 P3.7/TA4 43 I/O General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR4 P4.0 44 I/O General-purpose digital I/O, bit 0 P4.1 45 I/O General-purpose digital I/O, bit 1 P4.2/STE 46 I/O General-purpose digital I/O, slave transmit enable – USART/SPI mode P4.3/SIMO 47 I/O General-purpose digital I/O, slave in/master out – USART/SPI mode P4.4/SOMI 48 I/O General-purpose digital I/O, master in/slave out – USART/SPI mode P4.5/UCLK 49 I/O General-purpose digital I/O, external clock input – USART P4.6/UTXD 50 I/O General-purpose digital I/O, transmit data out – USART/UART mode P4.7/URXD 51 I/O General-purpose digital I/O, receive data in – USART/UART mode R03 88 I Input port of fourth positive (lowest) analog LCD level (V5) – LCD R13 89 I Input port of third most positive analog LCD level (V3 of V4) – LCD R23 90 I Input port of second most positive analog LCD level (V2) – LCD R33 91 O Output of most positive analog LCD level (V1) – LCD RST/NMI 96 I Reset input or non-maskable interrupt input port S0 57 O Segment line S0 – LCD S1 58 O Segment line S1 – LCD S2/O2–S5/O5 59–62 O Segment lines S2 to S5 or digital output ports, O2-O5, group 1 – LCD S6/O6–S9/O9 63–66 O Segment lines S6 to S9 or digital output ports O6-O9, group 2 – LCD S10/O10–S13/O13 67–70 O Segment lines S10 to S13 or digital output ports O10-O13, group 3 – LCD S14/O14–S17/O17 71–74 O Segment lines S14 to S17 or digital output ports O14-O17, group 4 – LCD S18/O18–S21/O21 75–78 O Segment lines S18 to S21 or digital output ports O18-O21, group 5 – LCD S22/O22–S25/O25 79, 81–83 O Segment line S22 to S25 or digital output ports O22-O25, group 6 – LCD 84–87 O Segment line S26 to S29 or digital output ports O26-O29, group 7 – LCD. Segment line S29 can be used as comparator input port CMPI – Timer/Port TCK 95 I Test clock. TCK is the clock input port for device programming and test TDI/VPP 93 I Test data input. TDI/VPP is used as a data input port or input for programming voltage S26/O26–S29/O29/CMPI 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION TMS 94 I Test mode select. TMS is used as an input port for device programming and test TDO/TDI 92 I/O Test data output port. TDO/TDI data output or programming data input terminal TP0.0 3 O General-purpose 3-state digital output port, bit 0 – Timer/Port TP0.1 4 O General-purpose 3-state digital output port, bit 1 – Timer/Port TP0.2 5 O General-purpose 3-state digital output port, bit 2 – Timer/Port TP0.3 6 O General-purpose 3-state digital output port, bit 3 – Timer/Port TP0.4 7 O General-purpose 3-state digital output port, bit 4 – Timer/Port TP0.5 8 I/O General-purpose 3-state digital input/output port, bit 5 – Timer/Port VCC1 1 Positive supply voltage VCC2 29 Positive supply voltage VSS1 100 Ground reference VSS2 28 Ground reference VSS3 52 Ground reference XBUF 97 O System clock (MCLK) or crystal clock (ACLK) output Xin 99 I Input port for crystal oscillator Xout/TCLK 98 I/O Output terminal of crystal oscillator or test clock input short-form description processing unit The processing unit is based on a consistent and orthogonal designed CPU and instruction set. This design structure results in a RISC-like architecture, highly transparent to the application development and is distinguished due to ease of programming. All operations, other than program-flow instructions consequently are performed as register operations in conjunction with seven addressing modes for source and four modes for destination operand. CPU registers Sixteen registers are located inside the CPU, providing reduced instruction execution time. This reduces a register-register operation execution time to one cycle of the processor frequency. PC/R0 Stack Pointer SP/R1 Status Register Four of the registers are reserved for special use as a program counter, a stack pointer, a status register and a constant generator. The remaining registers are available as general purpose registers. Constant Generator Peripherals are connected to the CPU using a data address and control bus and can be handled easily with all instructions for memory manipulation. POST OFFICE BOX 655303 Program Counter • DALLAS, TEXAS 75265 SR/CG1/R2 CG2/R3 General Purpose Register R4 General Purpose Register R5 General Purpose Register R14 General Purpose Register R15 5 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 instruction set The instruction set for this register-register architecture provides a powerful and easy-to-use assembly language. The instruction set consists of 51 instructions, with three formats and seven addressing modes. Table 1 provides a summation and example of the three types of instruction formats; the addressing modes are listed in Table 2. Table 1. Instruction Word Formats Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 → R5 Single operands, destination only e.g. CALL R8 PC → (TOS), R8→ PC Relative jump, un–/conditional e.g. JNE Jump-on equal bit = 0 Instructions that can operate on both word and byte data are differentiated by the suffix .B when a byte operation is required. Examples: Instructions for word operation: Instructions for byte operation: MOV EDE,TONI MOV.B EDE,TONI ADD #235h,&MEM ADD.B #35h,&MEM PUSH R5 PUSH.B R5 SWPB R5 ––– Table 2. Address Mode Descriptions S D Register ADDRESS MODE √ √ MOV Rs,Rd SYNTAX MOV R10,R11 EXAMPLE R10 → R11 OPERATION Indexed √ √ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6) Symbolic (PC relative) √ √ MOV EDE,TONI Absolute √ √ MOV &MEM,&TCDAT Indirect √ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6) Indirect autoincrement √ MOV @Rn+,Rm MOV @R10+,R11 M(R10) → R11 R10 + 2→ R10 Immediate √ MOV #X,TONI MOV #45,TONI #45 → M(TONI) M(EDE) → M(TONI) M(MEM) → M(TCDAT) NOTE 1: S = source, D = destination. Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other instructions. These addressing modes provide indirect addressing, ideally suited for computed branches and calls. The full use of this programming capability permits a program structure different from conventional 8- and 16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks instead of using flag type programs for flow control. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 operation modes and interrupts The MSP430 operating modes support various advanced requirements for ultra-low power and ultra-low energy consumption. This is achieved by the intelligent management of the operations during the different module operation modes and CPU states. The requirements are fully supported during interrupt event handling. An interrupt event awakens the system from each of the various operating modes and returns with the RETI instruction to the mode that was selected before the interrupt event. The clocks used are ACLK and MCLK. ACLK is the crystal frequency and MCLK is a multiple of ACLK and is used as the system clock. The following five operating modes are supported: D D D D D D Active mode (AM). The CPU is enabled with different combinations of active peripheral modules. Low power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals are active, and loop control for MCLK is active. Low power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals are active, and loop control for MCLK is inactive. Low power mode 2 (LMP2). The CPU is disabled, peripheral operation continues, ACLK signal is active, and MCLK and loop control for MCLK are inactive. Low power mode 3 (LMP3). The CPU is disabled, peripheral operation continues, ACLK signal is active, MCLK and loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator (DCO) ( MCLK generator) is switched off. ³ Low power mode 4 (LMP4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive (crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO is switched off. The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or enabled. However, some peripheral current-saving functions are accessed through the state of local register bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral, which is turned on or off using one register bit. The most general bits that influence current consumption and support fast turn-on from low power operating modes are located in the status register (SR). Four of these bits control the CPU and the system clock generator: SCG1, SCG0, OscOff, and CPUOff. 15 Reserved For Future Enhancements 9 8 V 7 SCG1 0 SCG0 OscOff CPUOff GIE N Z C rw-0 interrupts Software determines the activation of interrupts through the monitoring of hardware set interrupt flag status bits, the control of specific interrupt enable bits in SRs, the establishment of interrupt vectors, and the programming of interrupt handlers. The interrupt vectors and the power-up starting address are located in ROM address locations 0FFFFh through 0FFE0h. Each vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. Table 3 provides a summation of interrupt functions and addresses. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 Table 3. Interrupt Functions and Addresses INTERRUPT SOURCE INTERRUPT FLAG Power-up, external reset, Watchdog WDTIFG NMI, Oscillator fault NMIIFG (see Notes 2 and 4) OFIFG (see Notes 2 and 5) Dedicated I/O P0.0 Dedicated I/O P0.1 or 8-bit Timer/Counter SYSTEM INTERRUPT WORD ADDRESS PRIORITY Reset 0FFFEh 15, highest Non-maskable (Non)-maskable 0FFFCh 14 P0IFG.0 Mmaskable 0FFFAh 13 P0IFG.1 Maskable 0FFF8h 12 Maskable 0FFF6h 11 Watchdog Timer WDTIFG Maskable 0FFF4h 10 Timer_A CCIFG0 (see Note 3) Maskable 0FFF2h 9 Timer_A TAIFG (see Note 3) Maskable 0FFF0h 8 UART receive URXIFG Maskable 0FFEEh 7 UART transmit UTXIFG Maskable 0FFECh 6 0FFEAh 5 Timer/Port RC1FG,, RC2FG,, EN1FG (see Note 3) Maskable 0FFE8h 4 I/O port P2 P2IFG.07 (see Note 2) Maskable 0FFE6h 3 I/O port P1 P1IFG.07 (see Note 2) Maskable 0FFE4h 2 Basic Timer1 BTIFG Maskable 0FFE2h 1 I/O port P0.2 – P0.7 P0IFG.27 (see Note 2) Maskable 0FFE0h 0, lowest NOTES: 2. 3. 4. 5. Multiple source flags Interrupt flags are located in the individual module registers. Non-maskable : neither the individual or the general interrupt enable bit will disable an interrupt event. (Non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot. special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2 7 Address 6 5 4 0h 3 2 1 P0IE.1 P0IE.0 OFIE rw-0 WDTIE: OFIE: P0IE.0: P0IE.1: Watchdog Timer interrupt enable signal Oscillator fault interrupt enable signal Dedicated I/O P0.0 interrupt enable signal P0.1 or 8-bit Timer/Counter, RXD interrupt enable signal Address 7 01h 6 5 4 3 BTIE TPIE rw-0 URXIE: UTXIE: TPIE: BTIE: 8 rw-0 rw-0 USART receive interrupt enable signal USART transmit interrupt enable signal Timer/Port interrupt enable signal Basic Timer1 interrupt enable signal POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 rw-0 2 0 WDTIE rw-0 1 UTXIE rw-0 0 URXIE rw-0 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 interrupt flag registers 1 and 2 7 Address 6 5 02h 4 3 2 1 NMIIFG P0IFG.1 P0IFG.0 OFIFG rw-0 WDTIFG: rw-0 rw-0 rw-1 OFIFG: P0IFG.0: P0IFG.1: NMIIFG: Set on overflow or security key violation or Reset on VCC1 power-on or reset condition at RST/NMI-pin Flag set on oscillator fault Dedicated I/O P0.0 P0.1 or 8-bit Timer/Counter, RXD Signal at RST/NMI-pin Address 7 03h 6 5 4 3 2 BTIFG URXIFG: UTXIFG: BTIFG: WDTIFG rw-0 1 UTXIFG rw 0 rw-1 0 URXIFG rw-0 USART receive flag USART transmit flag Basic Timer1 flag module enable registers 1 and 2 Address 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 04h Address 05h UTXE rw-0 UTXE: URXE: Legend URXE rw-0 USART transmit enable USART receive enable rw: rw-0: Bit can be read and written Bit can be read and written. It is reset by PUC SFR bit not present in device POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 ROM memory organization MSP430C337 MSP430C336 FFFFh FFE0h FFDFh Int. Vector FFFFh FFE0h FFDFh 24 kB ROM Int. Vector MSP430P337A PMS430E337A FFFFh FFE0h FFDFh 32 kB ROM Int. Vector 32 kB OTP or EPROM A000h 8000h 05FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h 1024B RAM 16b Per. 8b Per. SFR 05FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h 8000h 1024B RAM 16b Per. 8b Per. SFR 05FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h 1024B RAM 16b Per. 8b Per. SFR peripherals Peripherals are connected to the CPU through a data, address, and controls bus and can be handled easily with instructions for memory manipulation. oscillator and system clock Two clocks are used in the system: the system (master) clock (MCLK) and the auxiliary clock (ACLK). The MCLK is a multiple of the ACLK. The ACLK runs with the crystal oscillator frequency. The special design of the oscillator supports the feature of low current consumption and the use of a 32 768 Hz crystal. The crystal is connected across two terminals without any other external components being required. The oscillator starts after applying VCC, due to a reset of the control bit (OscOff) in the status register (SR). It can be stopped by setting the OscOff bit to a 1. The enabled clock signals ACLK, ACLK/2, ACLK/4, or MCLK are accessible for use by external devices at output terminal XBUF . The controller system clocks have to deal with different requirements according to the application and system condition. Requirements include: D D D D 10 High frequency in order to react quickly to system hardware requests or events Low frequency in order to minimize current consumption, EMI, etc. Stable frequency for timer applications e.g. real time clock (RTC) Enable start-stop operation with minimum delay to operation function POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 oscillator and system clock (continued) These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. The compromise selected for the MSP430 uses a low-crystal frequency which is multiplied to achieve the desired nominal operating range: f (system) + (N ) 1) f (crystal) The crystal frequency multiplication is acheived with a frequency locked loop (FLL) technique. The factor N is set to 31 after a power-up clear condition. The FLL technique, in combination with a digital controlled oscillator (DCO), provides immediate start-up capability together with long term crystal stability. The frequency variation of the DCO with the FLL inactive is typically 330 ppm, which means that with a cycle time of 1 µs the maximum possible variation is 0.33 ns. For more precise timing, the FLL can be used, which forces longer cycle times if the previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to meet the chosen system frequency over a long period of time. The start-up operation of the system clock depends on the previous machine state. During a PUC, the DCO is reset to its lowest possible frequency. The control logic starts operation immediately after recognition of PUC. multiplication The multiplication operation is supported by a dedicated peripheral module. The module performs 16x16, 16x8, 8x16, and 8x8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required. digital I/O Five eight-bit I/O ports (P0 thru P4) are implemented. Port P0 has six control registers, P1 and P2 have seven control registers, and P3 and P4 modules have four control registers to give maximum flexibility of digital input/output to the application: D D D D Individual I/O bits are independently programable. Any combination of input, output, and interrupt conditions is possible. Interrupt processing of external events is fully implemented for all eight bits of the P0, P1, and P2 ports. Read/write access is available to all registers by all instructions. The seven registers are: D D D D D D D Input register contains information at the pins Output register contains output information Direction register controls direction Interrupt edge select contains input signal change necessary for interrupt Interrupt flags indicates if interrupt(s) are pending Interrupt enable contains interrupt enable pins Function select determines if pin(s) used by module or port These registers contain eight bits each with the exception of the interrupt flag register and the interrupt enable register which are 6 bits each. The two least significant bit (LSBs) of the interrupt flag and enable registers are located in the special function register (SFR). Five interrupt vectors are implemented, one for Port P0.0, one for Port P0.1, one commonly used for any interrupt event on Port P0.2 to Port P0.7, one commonly used for any interrupt event on Port P1.0 to Port P1.7, and one commonly used for any interrupt event on Port P2.0 to Port P2.7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 LCD drive Liquid crystal displays (LCDs) for static, 2-, 3-, and 4-MUX operation can be driven directly. The operation of the controller LCD logic is defined by software through memory-bit manipulation. LCD memory is part of the LCD module, not part of data memory. Eight mode and control bits define the operation and current consumption of the LCD drive. The information for the individual digits can be easily obtained using table programming techniques combined with the proper addressing mode. The segment information is stored into LCD memory using instructions for memory manipulation. The drive capability is defined by the external resistor divider that supports analog levels for 2-, 3-, and 4-MUX operation. Groups of the LCD segment lines can be selected for digital output signals. The MSP430x33x configuration has four common lines, 30 segment lines, and four terminals for adjusting the analog levels. Basic Timer1 The Basic Timer1 (BT1) divides the frequency of MCLK or ACLK, as selected with the SSEL bit, to provide low frequency control signals. This is done within the system by one central divider, the Basic Timer1, to support low current applications. The BTCTL control register contains the flags which control or select the different operational functions. When the supply voltage is applied or when a reset of the device (RST/NMI pin), a watchdog overflow, or a watchdog security key violation occurs, all bits in the register hold undefined or unchanged status. The user software usually configures the operational conditions on the BT during initialization. The Basic Timer1 has two eight bit timers which can be cascaded to a sixteen bit timer. Both timers can be read and written by software. Two bits in the SFR address range handle the system control interaction according to the function implemented in the Basic Timer1. These two bits are the Basic Timer1 interrupt flag (BTIFG) and the Basic Timer1 interrupt enable (BTIE) bit. Watchdog Timer The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a software upset has occurred. If the selected time interval expires, a system reset is generated. If this watchdog function is not needed in an application, the module can work as an interval timer, which generates an interrupt after the selected time interval. The Watchdog Timer counter (WDTCNT) is a 15/16-bit upcounter which is not directly accessible by software. The WDTCNT is controlled using the Watchdog Timer control register (WDTCTL), which is an 8-bit read/write register. Writing to WDTCTL, in both operating modes (watchdog or timer) is only possible by using the correct password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte password is 05Ah. If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated. When the password is read its value is 069h. This minimizes accidental write operations to the WDTCTL register. In addition to the Watchdog Timer control bits, there are two bits included in the WDTCTL that configure the NMI pin. USART The universal synchronous/asynchronous interface is a dedicated peripheral module which provides serial communications. The USART supports synchronous SPI (3 or 4 pin), and asynchronous UART communications protocols, using double buffered transmit and receive channels. Data streams of 7 or 8 bits in length can be transferred at a rate determined by the program, or by a rate defined by an external clock. Low power applications are optimized by UART mode options which allow for the receipt of only the first byte of a complete frame. The applications software then decides if the succeeding data is to be processed. This option reduces power consumption. Two dedicated interrupt vectors are assigned to the USART module, one for the receive and one for the transmit channel. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 Timer/Port The Timer/Port module has two 8-bit counters, an input that triggers one counter and six digital outputs with 3-state capability. Both counters have an independent clock selector for selecting an external signal or one of the internal clocks (ACLK or MCLK). One of the counters has an extended control capability to halt, count continuously, or gate the counter by selecting one of two external signals. This gate signal sets the interrupt flag if an external signal is selected and the gate stops the counter. Both timers can be read to and written from by software. The two 8-bit counters can be cascaded to form a 16-bit counter. A common interrupt vector is implemented. The interrupt flag can be set by three events in the 8-bit counter mode (gate signal or overflow from the counters) or by two events in the 16-bit counter mode (gate signal or overflow from the MSB of the cascaded counter). slope A/D conversion Slope A/D conversion is accomplished with the Timer/Port module using external resistor(s) for reference (Rref), external resistor(s) to the measured (Rmeas), and an external capacitor. The external components are driven by software in such a way that the internal counter measures the time that is needed to charge or discharge the capacitor.The reference resistor’s (Rref) charge or discharge time is represented by Nref counts. The unknown resistors (Rmeas) charge or discharge time is represented by Nmeas counts. The unknown resistor’s value Rmeas is the value of Rref multiplied by the relative number of counts (Nmeas/Nref). This value determines resistive sensor values that correspond to the physical data, for example temperature, when an NTC or PTC resistor is used. Timer_A The Timer_A module offers one sixteen bit counter and five capture/compare registers. The timer clock source can be selected to come from an external source TACLK (SSEL=0), the ACLK (SSEL=1), or MCLK (SSEL=2 or SSEL=3). The clock source can be divided by one, two, four or eight. The timer can be fully controlled (in word mode) since it can be halted, read, and written. It can be stopped, run continuously, count up, or count up/down using one compare block to determine the period. The five capture/compare blocks are configured by the application software to run in either capture or compare mode. The capture mode is primarily used to measure external or internal events with any combination of positive, negative, or both edges of the clock. The clock can also be stopped in capture mode by software. One external event (CCISx=0) per capture block can be selected. If CCISx=1, the ACLK is the capture signal; and if CCISx=2 or CCISx=3, software capture is chosen. The compare mode is primarily used to generate timing for the software or application hardware or to generate pulse-width modulated output signals for various purposes like D/A conversion functions or motor control. An individual output module, which can run independently of the compare function or is triggered in several ways, is assigned to each of the five capture/compare registers. Two interrupt vectors are used by the Timer_A module. One individual vector is assigned to capture/compare block CCR0 and one common interrupt vector is assigned to the timer and the other four capture/compare blocks. The five interrupt events using the common vector are identified by an individual interrupt vector word. The interrupt vector word is used to add an offset to the program counter to continue the interrupt handler software at the correct location. This simplifies the interrupt handler and gives each interrupt event the same interrupt handler overhead of 5 cycles. 8-bit Timer/Counter The 8-bit interval timer supports three major functions for applications: D D D Serial communication or data exchange Plus counting or plus accumulation Timer POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 8-bit Timer/Counter (continued) The 8-bit Timer/Counter peripheral includes the following major blocks: an 8-bit up-counter with preload register, an 8-bit control register, an input clock selector, an edge detection (e.g. start bit detection for asynchronous protocols), and an input and output data latch, triggered by the carry-out-signal from the 8-bit counter. The 8-bit counter counts up with an input clock, which is selected by two control bits from the control register. The four possible clock sources are MCLK, ACLK, the external signal from terminal P0.1, and the signal from the logical AND of MCLK and terminal P0.1. Two counter inputs (load, enable) control the counter operation. The load input controls load operations. A write-access to the counter results in loading the content of the preload register into the counter. The software writes or reads the preload register with all instructions. The preload register acts as a buffer and can be written immediately after the load of the counter is completed. The enable input enables the count operation. When the enable signal is set to high, the counter will count-up each time a positive clock edge is applied to the clock input of the counter. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 peripheral file map PERIPHERALS WITH BYTE ACCESS UART Transmit buffer, UTXBUF 077h Port P3 selection, P3SEL 01Bh Receive buffer, URXBUF 076h Port P3 direction, P3DIR 01Ah Baud rate, UBR1 075h Port P3 output, P3OUT 019h Baud rate, UBR0 074h Modulation control, UMCTL 073h Port P3 Port P0 Port P3 input, P3IN 018h Port P0 interrupt enable, P0IE 015h Receive control, URCTL 072h Port P0 interrupt edge select, P0IES 014h Transmit control, UTCTL 071h Port P0 interrupt flag, P0IFG 013h 012h UART control, UCTL 070h Port P0 direction, P0DIR EPROM EPROM control, EPCTL 054h Port P0 output, P0OUT 011h Crystal Buffer Crystal buffer control, CBCTL 053h Port P0 input, P0IN 010h System Clock SCG frequency control, SCFQCTL 052h Special SFR interrupt flag2, IFG2 003h SCG frequency integrator, SCFI1 051h Function SFR interrupt flag1, IFG1 002h SCG frequency integrator, SCFI0 050h SFR interrupt enable2, IE2 001h Timer/Port enable, TPE 04Fh SFR interrupt enable1, IE1 000h Timer/Port data, TPD 04Eh PERIPHERALS WITH WORD ACCESS Timer/Port counter2, TPCNT2 04Dh Multiply Timer/Port Basic Timer1 8-bit T/C LCD Port P1 Port P4 013Eh 013Ch Timer/Port counter1, TPCNT1 04Ch Result high word, ResHi Timer/Port control, TPCTL 04Bh Result low word, ResLo 013Ah Basic timer counter2, BTCNT2 047h Second operand, OP2 0138h Basic timer counter1, BTCNT1 046h Reserved 0136h Basic timer control, BTCTL 040h Multiply+accumulate/operand1, MAC 0134h 8-bit Timer/Counter data, TCDAT 044h Multiply signed/operand1, MPYS 0132h 8-bit Timer/Counter preload, TCPLD 043h Multiply unsigned/operand1, MPY 0130h 8-bit Timer/Counter control, TCCTL 042h Watchdog Watchdog Timer control, WDTCTL 0120h LCD memory 15, LCDM15 03Fh Timer_A Timer_A interrupt vector, TAIV 012Eh Timer_A control, TACTL 0160h : Port P2 Sum extend, SumExt LCD memory 1, LCDM1 031h Cap/Com control, CCTL0 0162h LCD control & mode, LCDCTL 030h Cap/Com control, CCTL1 0164h Port P2 selection, P2SEL 02Eh Cap/Com control, CCTL2 0166h Port P2 interrupt enable, P2IE 02Dh Cap/Com control, CCTL3 0168h Port P2 interrupt edge Select, P2IES 02Ch Cap/Com control, CCTL4 016Ah Port P2 interrupt flag, P2IFG 02Bh Reserved 016Ch Port P2 direction, P2DIR 02Ah Reserved 016Eh Port P2 output, P2OUT 029h Timer_A register, TAR 0170h Port P2 input, P2IN 028h Cap/Com register, CCR0 0172h Port P1 selection, P1SEL 026h Cap/Com register, CCR1 0174h Port P1 interrupt enable, P1IE 025h Cap/Com register, CCR2 0176h Port P1 interrupt edge Select, P1IES 024h Cap/Com register, CCR3 0178h Port P1 interrupt flag, P1IFG 023h Cap/Com register, CCR4 017Ah Port P1 direction, P1DIR 022h Reserved 017Ch Port P1 output, P1OUT 021h Reserved 017Eh Port P1 input, P1IN 020h Port P4 selection, P4SEL 01Fh Port P4 direction, P4DIR 01Eh Port P4 output, P4OUT 01D Port P4 input, P4IN 01Ch POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 absolute maximum ratings† Supply voltage range, between VCC terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 0.3 V Supply voltage range, between VSS terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 0.3 V Input voltage range, VCC1 to any VSS terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 6 V Input voltage range, VCC2 to any VSS terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 6 V Input voltage range to any terminal (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA Storage temperature range, Tstg, (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C Storage temperature range, Tstg, (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. VCC1 VSS1 Common Lines COM0 to COM3, Segment Lines S0 to S29 Output Drivers O2 to O29 VCC1 VSS1 Core Logic With Core CPU, System, JTAG/Test, All Peripheral Modules J/X T/B A/U G/F VCC1 VSS1 Terminal of Timer/Port VSS3 VSS2 VSS1 Input Buffers and Output Drivers of Port P0–P4 Substrate and Ground Potential For Input Inverters/Buffers (see Note A) (see Note B) NOTES: A. Ground potential for all port output drivers and input terminals, excluding first inverter/buffer B. Ground potential for entire device core logic and peripheral modules Figure 1. Supply Voltage Interconnection 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC2 VSS2 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 recommended operating conditions PARAMETER MIN Supply voltage, VCC, (MSP430C33x) 2.5 Supply voltage, VCC, (MSP430E/P33xA) 2.5 Supply voltage, VSS NOM MAX V 5.5 V 0 MSP430C33x, MSP430P33xA Operating free-air free air temperature range TA –40 PMS430E33xA 85 32 768 VCC = 3 V VCC = 5 V Processor frequency (signal MCLK), MCLK) fsystem t Low-level input voltage, VIL† (excluding Xin, Xout) High-level input voltage, VIH† (excluding Xin, Xout) High-level input voltage, VIH(Xin, Xout) † A serial resistor of 1 kΩ to the RST/NMI pin is recommended to enhance latch–up immunity. °C HZ DC 1.65 MHz DC 3.8 MHz VSS 0.7×VCC VSS VSS+0.8 VCC 0.2×VCC1 0.8×VCC1 VCC1 VCC = 3 V/5 V Low-level input voltage, VIL(Xin, Xout) – Maximum Processor Frequency – MHz f (system) V 25 XTAL frequency f(XTAL) (signal ACLK) UNIT 5.5 V V 5 4 3 2 1.1 MHz at 2.5 V 1 0 0 1 2 3 4 5 VCC – Supply Voltage – V 6 7 Figure 2. Processor Frequency vs Supply Voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) supply current (into VCC) excluding external current (f(system) = 1 MHz) (see Note 6) PARAMETER I(AM) NOM MAX C336/7 TA= –40°C +85°C, TA= –40°C +85°C, TEST CONDITIONS VCC = 3 V VCC = 5 V 400 500 800 900 P337A TA= –40°C +85°C, TA= –40°C +85°C, VCC = 3 V VCC = 5 V 570 700 1170 1250 C336/7 TA= –40°C +85°C, TA= –40°C +85°C, VCC = 3 V VCC = 5 V 50 70 100 130 P337A TA= –40°C +85°C, TA= –40°C +85°C, VCC = 3 V VCC = 5 V 50 70 100 130 TA= –40°C +85°C, TA= –40°C +85°C, VCC = 3 V VCC = 5 V 7 12 18 25 TA= –40°C TA= 25°C 2.0 3.5 VCC = 3 V 2.0 3.5 1.6 3.5 5.2 10 4.2 10 Active mode I(CPUOff) I(LPM2) I(LPM3) Low power mode mode, (LPM0,1) (LPM0 1) mode (LPM2) Low power mode, TA= 85°C TA= –40°C Low power mode, mode (LPM3) TA= 25°C TA= 85°C I((LPM4)) TA= –40°C TA= 25°C Low power mode, (LPM4) VCC = 5 V VCC = 3 V/5 V MIN 4.0 10 0.1 0.8 0.1 0.8 UNIT µA µA µA µA µA TA= 85°C 0.4 1.5 NOTE 6: All inputs are tied to 0 V or VCC2. Outputs do not source or sink any current. The current consumption in LPM2 and LPM3 are measured with active Basic Timer1 Module (ACLK selected), LCD Module (fLCD=1024Hz, 4MUX) and USART module (UART, ACLK, 2400 Baud selected) Current Consumption of active mode versus system frequency, IAM = IAM[1MHz] × fsystem[MHz] Current Consumption of active mode versus supply voltage, IAM = IAM[3V] + 200µA/V × (VCC–3) 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) schmitt-trigger inputs Port 0 to P4: P0.x to P4.x, Timer/Port: CIN, TP0.5 PARAMETER VIT+ VIT– Vhys y TEST CONDITIONS Positive-going input threshold voltage Negative-going input threshold voltage Input hysteresis (VIT+–VIT–) MIN NOM MAX VCC = 3 V VCC = 5 V 1.2 2.1 2.3 3.4 VCC = 3 V VCC = 5 V 0.7 1.5 1.4 2.3 VCC = 3 V VCC = 5 V 0.3 1.0 0.6 1.4 UNIT V outputs Port 0 to P4: P0.x to P4.x, Timer/Port: TP0.0 to TP0.5, LCD: S2/O2 to S29/O29, XBUF: XBUF, JTAG:TDO PARAMETER VOH VOL High level output voltage High-level Low level output voltage Low-level TEST CONDITIONS MIN NOM MAX IOH = – 1.2 mA, See Note 7 IOH = – 3.5 mA, See Note 8 VCC = 3 V VCC–0.4 VCC–1.0 VCC VCC IOH = – 1.5 mA, See Note 7 IOH = – 4.5 mA, See Note 8 VCC = 5 V VCC–0.4 VCC–1.0 VCC VCC IOL = + 1.2 mA, See Note 7 IOL = + 3.5 mA, See Note 8 VCC = 3 V VSS VSS VSS+0.4 VSS+1.0 VCC = 5 V VSS VSS VSS+0.4 VSS+1.0 IOL = + 1.5 mA, See Note 7 IOL = + 4.5 mA, See Note 8 UNIT V V NOTES: 7. The maximum total current for all outputs combined should not exceed ±9.6 mA to hold the maximum voltage drop specified. 8. The maximum total current for all outputs combined should not exceed ±28 mA to hold the maximum voltage drop specified. leakage current (see Note 9) PARAMETER TEST CONDITIONS Ilkg(TP) High-impendance leakage current, Timer/Port Timer/Port:VTP0.x, VCC = 3 V/5 V, CIN = VSS, VCC, (see Note 10) Ilkg(S27) High-impendance leakage current, S27 Ilkg(P0x) Leakage current, port 0 VS27 = VSS to VCC, Port P0: P0.x, 0 ≤ × ≤ 7, (see Note 11) VCC = 3 V/5 V VCC = 3 V/5 V, MIN NOM MAX UNIT ± 50 nA ± 50 nA ± 50 nA NOTES: 9. The leakage current is measured with VSS or VCC applied to the corresponding pins(s) – unless otherwise noted. 10. All Timer/Port pins (TP0.0 to TP0.5) are Hi-Z. Pins CIN and TP0.0 to TP0.5 are connected together during leakage current measurement. In the leakage measurement mode, the input CIN is included. The input voltage is VSS or VCC. 11. The leakages of the digital port terminals are measured individually. The port terminal must be selected for input and there must be no optional pullup or pulldown resistor. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) optional resistors (see Note 12) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT R(opt1) VCC = 3 V/5 V 1.4 4.1 6.8 kΩ R(opt2) VCC = 3 V/5 V 2.1 6.2 11 kΩ R(opt3) VCC = 3 V/5 V VCC = 3 V/5 V 4.2 12 20 kΩ 6.6 19 32 kΩ VCC = 3 V/5 V VCC = 3 V/5 V 12 37 62 kΩ 26 75 124 kΩ VCC = 3 V/5 V VCC = 3 V/5 V 39 112 185 kΩ 65 187 309 kΩ VCC = 3 V/5 V VCC = 3 V/5 V 91 261 431 kΩ 117 337 557 kΩ MAX UNIT R(opt4) R(opt5) R(opt6) Resistors, individually programmable with ROM code, all port pins, values applicable for pull-down and pull-up R(opt7) R(opt8) R(opt9) R(opt10) NOTE 12: Optional resistors R(optx) for pulldown or pullup are not programmed in standard OTP/EPROM devices P/E 337. inputs and outputs PARAMETER CONDITIONS t(int) External Interrupt timing Port P0, P1 to P2: External trigger signal for the interrupt flag (see Notes 13 and 14) t(cap) Timer_A, Capture timing TA0-TA4 External capture signal (see Note 15) f(IN) t(H) or t(L) Input frequency P0.1, P0 1 CIN, CIN TP 0.5, 0 5 UCLK, UCLK SIMO, SIMO SOMI, SOMI TACLK, TACLK TA0-TA4 t(H) or t(L) f(XBUF) f(TAx) f(UCLK) Output frequency t(Xdc) ∆t(TA) Duty cycle of output t(τ) USART: Deglitch time MIN NOM 3 V/5 V 1.5 cycle 3 V/5 V 250 ns 3 V/5 V DC 3V 300 f(system) f(system) 5V 300 f(system) f(system) XBUF, CL = 20 pF 3 V/5 V TA0-4, CL = 20 pF 3 V/5 V DC UCLK, CL = 20 pF XBUF, CL = 20 pF f(MCLK)= 1.1 MHz f(XBUF) = f(ACLK) f(XBUF) = f(ACLK/n) TA0..4, CL = 20 pF t(TAH)= t(TAL) 3 V/5 V DC f(system)/2 f(system) 3 V/5 V 3 V/5 V 3 V/5 V 40% 35% 60% 65% UCLK, C(L) = 15pF t(UCH)= t(UCL) ∆t(UC) VCC ns MHz 50 3 V/5 V 0 ±100 ns 3 V/5 V 0 ±100 ns 2.6 1.4 µs µs 3V 5V See Note16 MHz 0.6 0.3 NOTES: 13. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int). The conditions to set the flag must be met independently from this timing constraint. T(int) is defined in MCLK cycles. 14. The external interrupt signal cannot exceed the maximum input frequency (f(in)) 15. The external capture signal triggers the capture event every time t(cap) is met. It may be triggered even with capture signals shorter than t(cap). The conditions to set the flag must be met independently from this timing constraint. 16. The signal applied to the USART receive signal/terminal (URXD) should meet the timing requirements of t(τ) to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum timing condition of t(τ). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD line. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) LCD PARAMETER V(33) V(23) TEST CONDITIONS MIN Voltage at R33 Analog voltage V(13) V(03) Output 1 Output 0 I(R03) Input leakage R13 = VCC/3 R23 = 2 × VCC/3 I(R23) V(Sxx0) V(Sxx1) V(Sxx2) Segment line g voltage I(Sxx) µA, (S )= – 3 µA VCC+0.2 V V(33) – 2.5 I(HLCD)<= 10 nA I(LLCD) <= 10 nA UNIT (V33–V03) × 2/3 + V03 (V(33)–V(03)) × 1/3 + V(03) VCC = 3 V/5 V Voltage at R13 R03 = VSS I(R13) MAX 2.5 Voltage at R23 Voltage at R03 VO(HLCD) VO(LLCD) NOM VCC+0.2 V(R33) – 0.125 VSS VCC = 3 V/5 V VCC VSS + 0.125 V ±20 No load at all segmentt and d common lines, VCC = 3 V/5 V ±20 nA ±20 VCC = 3 V/5 V V(Sxx3) V(03) V(13) V(03) – 0.1 V(13) – 0.1 V(23) V(33) V(23) – 0.1 V(33) + 0.1 V PUC/POR PARAMETER TEST CONDITIONS MIN NOM MAX UNIT 150 250 µs 1.5 2.4 V 1.2 2.1 V 0.9 1.8 V 0 0.4 t(POR) delay TA = –40°C TA = 25°C POR V(POR) ( ) VCC = 3 V/5 V TA = 85°C V(min) t(reset) PUC/POR Reset is accepted internally V µs 2 V VCC V (POR) V (min) POR No POR POR t Figure 3. Power-On Reset (POR) vs Supply Voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 3 2.4 2.5 2.1 V POR [V] max 1.8 2 1.5 1.5 min 1 1.2 0.9 0.5 25°C 0 –40 –20 0 20 40 60 80 Temperature [°C] Figure 4. V(POR) vs Temperature electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) crystal oscillator: Xin, Xout PARAMETER C(Xin) Integrated capacitance at input C(Xout) Integrated capacitance at output TEST CONDITIONS MIN NOM VCC = 3V/5V MAX UNIT 12 pF 12 pF DCO PARAMETER TEST CONDITIONS MIN NOM MAX DCO N(DCO) = 1 A0h FN_4=FN_3=FN_2 = 0 VCC = 3 V/5 V f(DCO3) N(DCO) = 00 0110 0000 FN_4=FN_3=FN_2 = 0 VCC = 3 V VCC = 5 V 0.15 0.6 0.18 0.62 f(DCO26) N(DCO) = 11 0100 0000 FN_4=FN_3=FN_2 = 0 VCC = 3 V VCC = 5 V 1.25 4.7 1.45 5.5 f(DCO3) N(DCO) = 00 0110 0000 FN_4=FN_3=0, FN_2 = 1 VCC = 3 V VCC = 5 V 0.36 1.05 0.39 1.2 f(DCO26) N(DCO) = 11 0100 0000 FN_4=FN_3=0, FN_2 = 1 VCC = 3 V VCC = 5 V 2.5 8.1 3 9.9 f(DCO3) N(DCO) = 00 0110 0000 FN_4=0, FN_3=1, FN_2=X VCC = 3 V VCC = 5 V 0.5 1.5 0.6 1.8 f(DCO26) N(DCO) = 11 0100 0000 FN_4=0,FN_3 =1, FN_2=X VCC = 3 V VCC = 5 V 3.7 11 4.5 13.8 f(DCO3) N(DCO) = 00 0110 0000 FN_4=1, FN_3 = FN_2=X VCC = 3 V VCC = 5 V 0.7 1.85 0.8 2.4 f(DCO26) N(DCO) = 11 0100 0000 FN_4=1, FN_3 = FN_2=X VCC = 3 V VCC = 5 V 4.8 13.3 6 17.7 N(DCO) f(MCLK) = f(NOM) FN_4=FN_3=FN_2 = 0 VCC = 3 V/5 V A0h S f(NDCO)+1 = S x f(NDCO) VCC = 3 V/5 V 1.07 f(NOM) f(NOM) 2xf(NOM) 3xf(NOM) 4xf(NOM) 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 1A0h UNIT MHz 340h 1.13 MHz MHz MHz MHz MHz MHz MHz MHz MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 electrical characteristics over recommended and operating free-air temperature range (unless otherwise noted) (continued) f(DCO26) 4xfNOM f(DCO26) f(DCO3) 3xfNOM f(DCO26) f(DCO3) 2xfNOM Legend Tolerance at Tap 26 f(DCO26) DCO Frequency Adjusted by Bits 2∧9–2∧5 in SCFI1 f(DCO3) fNOM Tolerance at Tap 3 f(DCO3) FN_2 = 0 FN_3 = 0 FN_4 = 0 FN_2 = 1 FN_3 = 0 FN_4 = 0 FN_2 = X FN_3 = 1 FN_4 = 0 FN_2 = X FN_3 = X FN_4 = 1 RAM PARAMETER TEST CONDITIONS MIN NOM MAX UNIT V(RAMh) CPU halted (see Note 17) 1.8 V NOTE 17: This parameter defines the minimum supply voltage when the data in the program memory RAM remains unchanged. No program execution should happen during this supply voltage condition. Timer/Port comparator PARAMETER TEST CONDITIONS I(com) ( ) Comparator (Timer/Port) Vref(COM) Internal reference voltage at (–) terminal Vh (COM) hys(COM) Input hysteresis (comparator) CPON = 1 VCC = 3 V VCC = 5 V CPON = 1 VCC = 3 V/5 V VCC = 3 V CPON = 1 VCC = 5 V POST OFFICE BOX 655303 MIN NOM MAX 175 350 600 0.230 × VCC1 • DALLAS, TEXAS 75265 0.260 × VCC1 UNIT µA V 5 37 mV 10 42 mV 23 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) JTAG, program memory PARAMETER f(TCK) JTAG/Test R(test) V(FB) I(FB) t(FB) JTAG/Fuse (see Note 19) NOM Pullup resistors on TMS, TCK, TDI (see Note 18) VCC = 3 V/5 V 25 VCC = 3 V/5 V VCC = 3 V/5 V 5.5 6.0 11.0 12.0 Fuse blow voltage, E/P versions (see Note 20) DC 5 DC 10 60 Supply current on TDI/VPP to blow fuse Programming voltage, applied to TDI/VPP VCC = 5 V VCC = 5 V 12.0 VCC = 5 V VCC = 5 V 5 Programming time, fast algorithm Number of pulses for successful programming VCC = 5 V 4 Current from programming voltage source EPROM(E) ( ) and OTP(P) versions only ( ) version onlyy EPROM(E) MAX VCC = 3 V VCC = 5 V Time to blow the fuse Pn t(erase) MIN TCK frequency Fuse blow voltage, C versions (see Note 20) V(PP) I(PP) t(pps) t(ppf) TEST CONDITIONS Programming time, single pulse 12.5 90 UNIT MHz kΩ 100 mA 1 ms 13.0 70 V mA ms µs 100 100 Data retention TJ <55°C 10 Year Erase time wave length 2537 Å at 15 Ws/cm2 (UV lamp of 12 mW/ cm2) 30 min Write/erase cycles 1000 NOTES: 18. The TMS and TCK pullup resistors are implemented in all ROM(C), OTP(P) and EPROM(E) versions. The pullup resistor on TDI is implemented in C versions only. 19. Once the fuse is blown no further access to the MSP430 JTAG/test feature is possible. 20. The voltage supply to blow the fuse is applied to TDI/VPP pin during the fuse blowing procedure. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 typical input/output schematics VCC VCC (see Note A) (see Note A) (see Note B) (see Note B) (see Note B) (see Note B) (see Note A) (see Note A) GND GND CMOS INPUT CMOS SCHMITT-TRIGGER INPUT VCC (see Note A) (see Note B) (see Note A) (see Note B) GND I/O WITH SCHMITT-TRIGGER INPUT CMOS 3-STATE OUTPUT TDO_Internal VCC 60 k TYP TDO_Control TDI_Control TDI_Internal MSP430C336/337: TMS, TCK, TDI MSP430P/E337A: TMS, TCK MSP430C33x: TDO/TDI MSP430P/E337A: TDO/TDI NOTES: A. Optional selection of pullup or pulldown resistors available on ROM (masked) versions. B. Fuses for the optional pullup and pulldown resistors can only be programmed at the factory. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 typical input/output schematics VC COM 0–3 VD Control COM0–3 VA S0, S1 VB Segment contol VA S2/O2–Sn/On VB Non-Inverting Segment control LCDCTL (LCDM5,6,7) Data (LCD RAM bits 0–3 or bits 4–7) LCD OUTPUT (COM0–4, Sn, Sn/On) NOTE A: The signals VA, VB, VC, and VD come from the LCD module analog voltage generator. VPP_ Internal TDI_ Internal TDI/VPP JTAG Fuse TDO/TDI_Control TDO/TDI TMS TDO_ Internal JTAG Fuse Blow Control From/To JTAG_CBT_SIG_REG NOTES: A. During programming activity and when blowing the JTAG enable fuse, the TDI/VPP terminal is used to apply the correct voltage source. The TDO/TDI terminal is used to apply the test input data for JTAG circuitry. B. The TDI/VPP terminal of the ’P337A and ’E337A does not have an internal pullup resistor. An external pulldown resistor is recommended to avoid a floating node, which could increase the current consumption of the device. Remove the external pulldown resistors when switching from P/E337A to C337 devices. Otherwise system power consumption will increase. C. The TDO/TDI terminal is in a high-impedance state after POR. The ’P337A and ’E337A need a pullup or a pulldown resistor to avoid floating a node, which could increase the current consumption of the device. Figure 5. MSP430P/E337A: TDI/VPP, TDO/TDI 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 JTAG fuse check mode MSP430 devices that have the fuse on the TDI/VPP terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/VPP pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. Fuse check current may or may not flow continuously while the fuse check mode is active, depending on which type of device is in use and the state of the TMS pin. For the mask ROM or C versions, the fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see Figure 6). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). Time TMS Goes Low After POR TMS ITDI ITF Figure 6. Fuse Check Mode Current, MSP430C33xA For the OTP or P versions, the fuse check current will flow continuously when fuse check mode is active, regardless of the state of the TMS pin, until the fuse check mode is deactivated with the second positive edge at the TMS pin (see Figure 7). Time TMS Goes Low After POR TMS ITDI ITF Figure 7. Fuse Check Mode Current, MSP430P337A Care must be taken to avoid accidentally activating the fuse check mode, including guarding against EMI/ESD spikes that could cause signal edges on the TMS pin. Configuration of TMS, TCK, TDI/VPP and TDO/TDI pins in applications. C3xx P/E3xx TDI Open 68k, pull down TDO Open 68k, pull down TMS Open Open TCK Open Open POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 MECHANICAL DATA PJM (R-PQFP-G100) PLASTIC QUAD FLATPACK 0,38 0,22 0,65 80 0,13 M 51 50 81 12,35 TYP 100 14,20 13,80 17,45 16,95 31 1 30 0,16 NOM 18,85 TYP 20,20 19,80 23,45 22,95 2,90 2,50 Gage Plane 0,25 0,25 MIN 0°– 7° 1,03 0,73 Seating Plane 0,10 3,40 MAX 4040022 / B 03/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-022 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227 – OCTOBER 1999 MECHANICAL DATA HFD (S-GQFP-G100) CERAMIC QUAD FLATPACK 0,65 0,30 TYP 80 51 81 50 12,35 TYP 100 14,20 13,80 17,45 16,95 31 1 30 0,15 TYP 18,85 TYP 20,20 19,20 3,70 TYP 23,45 22,95 0,10 MIN 0°– 8° 1,00 0,60 Seating Plane 0,10 4,25 MAX 4081530/A 09/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated