PI6C2504 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Phase-Locked Loop Clock Driver with 4 Clock Outputs Product Features Product Description • High-Performance Phase-Locked-Loop Clock Distribution for Networking The PI6C2504 features a low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. • Registered DIMM Synchronous DRAM modules for server/workstation/PC applications • Allows Clock Input to have Spread Spectrum modulation for EMI reduction • Zero Input-to-Output delay • Low jitter: Cycle-to-Cycle jitter ±100ps max. • On-chip series damping resistor at clock output drivers for low noise and EMI reduction • Operates at 3.3V VCC • Wide range of Clock Frequencies up to 80 MHz • Package: Plastic 16-pin QSOP Package (Q) Logic Block Diagram Product Pin Configuration G 4 CLK_IN Y[0:3] PLL FB_IN FB_OUT AVCC Functional Table Inputs Outputs G Y[0:3] FB_O UT L L CLK _IN H CLK _IN CLK _IN 1 AGND 1 16 CLK_IN VCC 2 15 AVCC Y0 3 14 GND 13 GND 16-Pin Q Y1 4 GND 5 12 Y3 VCC 6 11 Y2 G 7 10 VCC FB_OUT 8 9 FB_IN PS8380A 07/17/00 PI6C2504 Phase-Locked Loop Clock Driver with 4 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Functions Pin Name Pin No. Type D e s cription CLK _IN 16 I Reference Clock input. CLK _IN allows spread spectrum clock input. FB_IN 9 I Feedback input. FB_IN provides the feedback signal to the internal PLL. G 7 I O utput bank enable. When G is LO W, outputs Y[0:3] are disabled to a logic low state. FB_O UT 8 O Feedback output. FB_O UT is dedicated for external feedback. FB_O UT has an embedded series- damping resistor of the same value as the clock outputs Yx. Y[0:3] 3,4,11,12 O C lock outputs. These outputs provide low- skew copies of CLK _IN Each output has an embedded series- damping resistor. AVC C 15 Power Analog power supply. For test purposes, AVC C can be also used to bypass the PLL. When AVC C is strapped to ground, PLL is bypassed and CLK _IN is buffered directly to the device outputs. AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VC C 2, 6, 10 Power Power supply. GND 5, 13, 14 Ground Ground DC Specifications (Absolute maximum ratings over operating free-air temperature range) Symbol Parame te r VI Input voltage range VO Output voltage range IO_DC M in. M ax. Units 0.5 VCC +0.5 V 100 mA 1.0 W 150 oC DC output current o Power Maximum power dissipation at TA = 55 C in still air TSTG Storage temperature 65 Note: Stress beyond those listed under absolute maximum ratings may cause permanent damage to the device. Parame te r Te s t Conditions ICC VI = VCC or GND; IO = 0(1) CI VI = VCC or GND CO VO =VCC or GND VCC M in. Typ. 3.6V M ax. Units 10 µA 4 3.3V pF 6 Note: 1. Continuous Output Current Recommended Operating Conditions Symbol Parame te r M in. M ax. 3.6 VC C S upply voltage 3.0 VI H High level input voltage 2.0 VI L Low level input voltage VI Input voltage 0 VC C TA O perating free- air temperature 0 70 0.8 2 Units V ºC PS8380A 07/17/00 PI6C2504 Phase-Locked Loop Clock Driver with 4 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Electrical Characteristics (Over recommended operating free-air temperature range Pull Up/Down Currents, VCC = 3.0V) Symbol IO H IO L Parame te r Pull- up c urre nt Pull- d o wn c urre nt Condition M in. M ax. VO U T = 2 . 4 V − 18 VO U T = 2 . 0 V − 30 VO U T = 0 . 8 V 25 VO U T = 0 . 5 5 V 17 Units mA AC Specifications Timing requirements over recommended ranges of supply voltage and operating free-air temperature Symbol Parame te r M in. M ax. Units FC L K Clock frequency 25 80 MHz DCYI Input clock duty cycle 40 60 % 1 ms Stabilization Time after power up Switching Characteristics (Over recommended ranges of supply voltage and operating free-air temperature, CL=30pF) VCC = 3.3V ±0.3V, 0-70 °C Parame te r From (Input) To (Output) tphase error without jitter CLK_IN ↑ at 100MHz and 66MHz FB_IN↑ 150 +150 Jitter, cycle- to- cycle At 100 MHz and 66 MHz Any Y or FB_OUT 100 +100 Skew, at 100 MHz and 66 MHz Any Y or FB_OUT M in. Typ. M ax. Units ps 200 Duty cycle 45 55 tr, rise- time, 0.4V to 2.0V 1.0 tf, fall- time, 2.0V to 0.4V 1.1 % ns Note: These switching parameters are guaranteed by design. 3 PS8380A 07/17/00 PI6C2504 Phase-Locked Loop Clock Driver with 4 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Package Mechanical Information: 16-pin QSOP Package (Q). ° Ordering Information Orde ring Code Package Name Package Type Ope rating Range PI6C2504Q Q 16 16- pin Q SO P Commercial Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 4 PS8380A 07/17/00