TI SN74BCT646DWR

 SCBS037D − AUGUST 1989 − REVISED MAY 2004
D State-of-the-Art BiCMOS Design
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54BCT646 . . . JT OR W PACKAGE
SN74BCT646 . . . DW OR NT PACKAGE
(TOP VIEW)
24
2
23
3
22
4
21
5
20
6
19
7
8
18
17
9
16
10
15
11
14
12
13
DIR
SAB
CLKAB
NC
VCC
CLKBA
SBA
1
VCC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
A3
NC
A4
A5
A6
5
1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
4 3 2
19
11
12 13 14 15 16 17 18
A7
A8
GND
NC
B8
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
SN54BCT646 . . . FK PACKAGE
(TOP VIEW)
OE
B1
B2
NC
B3
B4
B5
B7
B6
D
D
D Multiplexed Real-Time and Stored Data
D ESD Protection Exceeds JESD 22
Significantly Reduces ICCZ
Bus Transceivers/ Registers
Independent Registers and Enables for
A and B Buses
NC − No internal connection
description/ordering information
These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked
into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1
illustrates the four fundamental bus-management functions that can be performed with the ’BCT646 devices.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port can be stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high),
A data can be stored in one register and/or B data can be stored in the other register.
ORDERING INFORMATION
PDIP − NT
0°C
0
C to 70
70°C
C
−55°C
125°C
−55
C to 125
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
Tube
SN74BCT646NT
Tube
SN74BCT646DW
Tape and reel
SN74BCT646DWR
CDIP − JT
Tube
SNJ54BCT646JT
SNJ54BCT646JT
CFP − W
Tube
SNJ54BCT646W
SNJ54BCT646W
LCCC − FK
Tube
SNJ54BCT646FK
SOIC − DW
SN74BCT646NT
BCT646
SNJ54BCT646FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
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'$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+
POST OFFICE BOX 655303
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1
SCBS037D − AUGUST 1989 − REVISED MAY 2004
description/ordering information(continued)
When an output function is disabled, the input function still is enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
2
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21
OE
L
3
DIR
L
23
1
CLKAB CLKBA
X
X
22
SBA
L
2
SAB
X
BUS B
BUS A
BUS A
BUS B
SCBS037D − AUGUST 1989 − REVISED MAY 2004
21
OE
L
1
23
CLKAB CLKBA
X
↑
X
↑
↑
↑
2
SAB
L
2
SAB
X
X
X
22
SBA
X
BUS B
BUS A
BUS B
BUS A
3
DIR
X
X
X
23
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
21
OE
X
X
H
1
CLKAB
X
3
DIR
H
22
SBA
X
X
X
STORAGE FROM
A, B, OR A AND B
21
OE
L
L
3
DIR
L
H
1
CLKAB
X
H or L
23
CLKBA
H or L
X
2
SAB
X
H
22
SBA
H
X
TRANSFER STORED DATA
TO A AND/OR B
Pin numbers shown are for the DW, JT, NT, and W packages.
Figure 1. Bus-Management Functions
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3
SCBS037D − AUGUST 1989 − REVISED MAY 2004
FUNCTION TABLE
INPUTS
DATA I/O
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1 THRU A8
X
X
↑
X
X
X
Input
B1 THRU B8
Unspecified†
OPERATION OR FUNCTION
X
X
X
↑
X
X
Unspecified†
Input
Store A, B unspecified†
Store B, A unspecified†
H
X
↑
↑
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
H or L
X
H
X
Input
Output
Stored A data to B bus
† The data output functions can be enabled or disabled by various signals at the OE and DIR inputs. Data input functions always are enabled, i.e.,
data at the bus pins is stored on every low-to-high transition of the clock inputs.
logic diagram (positive logic)
OE
DIR
CLKBA
SBA
CLKAB
SAB
21
3
23
22
1
2
One of Eight
Channels
1D
C1
A1
4
20
1D
C1
To Seven Other Channels
Pin numbers shown are for the DW, JT, NT, and W packages.
4
POST OFFICE BOX 655303
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B1
SCBS037D − AUGUST 1989 − REVISED MAY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range: Control inputs (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC
Current into any output in the low state: SN54BCT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74BCT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
(see Note 3): NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-3.
recommended operating conditions (see Note 4)
SN54BCT646
SN74BCT646
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IIK
Low-level input voltage
0.8
0.8
V
Input clamp current
−18
−18
mA
IOH
IOL
High-level output current
−12
−15
mA
Low-level output current
48
64
mA
High-level input voltage
2
2
V
V
TA
Operating free-air temperature
−55
125
0
70
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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5
SCBS037D − AUGUST 1989 − REVISED MAY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
VCC = 4.5 V,
VOH
II = −18 mA
IOH = − 3 mA
IOH = −12 mA
IOH = −15 mA
VCC = 4.5 V
VCC = 4.5 V
IOL = 48 mA
IOL = 64 mA
VCC = 5.5 V,
VI = 5.5 V
VCC = 5.5 V,
VI = 2.7 V
Control inputs
VCC = 5.5 V,
VI = 0.5 V
A or B port
VCC = 5.5 V,
VCC = 5.5 V,
VO = 0
VI = GND
VCC = 5.5 V,
VCC = 5.5 V,
VI = 4.5 V
VI = GND
VOL
SN54BCT646
TYP†
MAX
MIN
−1.2
2.4
3.3
2
3.2
0.38
IIH‡
IIL‡
IOS§
ICCL
ICCH
ICCZ
Control inputs
A or B port
Control inputs
A or B port
A or B port
A or B port
−1.2
2.4
3.3
2
3.1
−100
V
0.55
0.55
1
1
1
1
70
70
20
20
−0.7
−0.7
−0.7
−0.7
−225
42
UNIT
V
0.42
A or B port
II
SN74BCT646
TYP†
MAX
MIN
−100
µA
A
mA
mA
67
mA
5.6
9
mA
10
16
mA
42
5.6
9
10
16
Control inputs VCC = 5 V,
VI = 2.5 V or 0.5 V
6
Cio
A or B port
VCC = 5 V,
VO = 2.5 V or 0.5 V
12
† All typical values are at VCC = 5 V, TA = 25°C.
‡ For I/O ports, the parameters IIH and IIL include the off-state output current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
mA
−225
67
Ci
V
6
pF
14
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
MIN
MAX
SN54BCT646
MIN
MIN
Clock frequency
Pulse duration, CLK high or low
6
6
6
ns
tsu
th
Setup time, A or B before CLKAB↑ or CLKBA↑
6
7
6
ns
0.5
0.5
0.5
ns
Hold time, A or B after CLKAB↑ or CLKBA↑
POST OFFICE BOX 655303
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83
UNIT
MAX
fclock
tw
6
83
MAX
SN7BCT646
83
MHz
SCBS037D − AUGUST 1989 − REVISED MAY 2004
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
TYP
SN54BCT646
MAX
83
CLKBA or CLKAB
A or B
A or B
B or A
SAB or SBA†
(with A or B high)
A or B
SAB or SBA†
(with A or B low)
A or B
OE
A or B
OE
A or B
DIR
A or B
MIN
MAX
83
MIN
MHz
3.6
7
9.4
3.6
12.4
3.6
11.2
3.9
7
9.2
3.9
11.5
3.9
10.6
3.1
6
8.1
3.1
11.1
3.1
9.5
3.7
6.8
8.9
3.7
12.1
3.7
10.5
4.5
8.8
11.2
4.5
15.2
4.5
13.8
3.3
6
8.1
3.3
9.8
3.3
9.1
3.9
7.7
10.2
3.9
13.3
3.9
12
4.7
8.3
10.8
4.7
13.7
4.7
12.9
4
7.9
10.7
4
14
4
13.2
4.6
8.8
11.8
4.6
15.4
4.6
14.4
4
7.2
9.4
4
12
4
10.9
3.4
7
9.3
3.4
11.6
3.4
10.5
2.8
7.8
10.7
2.8
14
2.8
13.1
3.8
8.9
11.9
3.8
15.6
3.8
14.6
3.8
12.6
3.2
11.8
• DALLAS, TEXAS 75265
UNIT
MAX
83
3.8
8.4
10.7
3.8
13.2
DIR
A or B
tPLZ
3.2
7.3
9.9
3.2
12.6
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
POST OFFICE BOX 655303
SN74BCT646
ns
ns
ns
ns
ns
ns
ns
ns
7
SCBS037D − AUGUST 1989 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
7 V (tPZL, tPLZ, O.C.)
S1
Open
(all others)
From Output
Under Test
Test
Point
CL
(see Note A)
R1
From Output
Under Test
R1
Test
Point
CL
(see Note A)
R2
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
RL = R1 = R2
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
High-Level
Pulse
(see Note B)
3V
Timing Input
(see Note B)
3V
1.5 V
1.5 V
0V
1.5 V
tw
0V
Data Input
(see Note B)
3V
th
tsu
Low-Level
Pulse
3V
1.5 V
1.5 V
0V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Output
Control
(low-level enable)
3V
Input
(see Note B)
1.5 V
1.5 V
0V
tPLH
In-Phase
Output
(see Note D)
1.5 V
VOL
VOH
1.5 V
1.5 V
0V
tPLZ
1.5 V
Waveform 1
(see Notes C and D)
3.5 V
VOL
tPHZ
tPLH
tPHL
Out-of-Phase
Output
(see Note D)
1.5 V
1.5 V
tPZL
tPHL
VOH
1.5 V
0.3 V
tPZH
Waveform 2
(see Notes C and D)
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
VOH
1.5 V
0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. The outputs are measured one at a time, with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
F. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
5962-9155501M3A
ACTIVE
LCCC
FK
28
1
TBD
Call TI
Level-NC-NC-NC
5962-9155501MKA
ACTIVE
CFP
W
24
1
TBD
Call TI
Level-NC-NC-NC
5962-9155501MLA
ACTIVE
CDIP
JT
24
1
TBD
Call TI
Level-NC-NC-NC
SN74BCT646DW
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74BCT646DWE4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74BCT646DWR
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74BCT646DWRE4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74BCT646NT
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74BCT646NTE4
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SNJ54BCT646FK
ACTIVE
LCCC
FK
28
1
TBD
Call TI
Level-NC-NC-NC
SNJ54BCT646JT
ACTIVE
CDIP
JT
24
1
TBD
Call TI
Level-NC-NC-NC
SNJ54BCT646W
ACTIVE
CFP
W
24
1
TBD
Call TI
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
13
24
B
1
24
28
A MAX
1.280
(32,51)
1.460
(37,08)
A MIN
1.240
(31,50)
1.440
(36,58)
B MAX
0.300
(7,62)
0.291
(7,39)
B MIN
0.245
(6,22)
0.285
(7,24)
DIM
12
0.070 (1,78)
0.030 (0,76)
0.100 (2,54) MAX
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
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MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.090 (2,29)
0.045 (1,14)
0.045 (1,14)
0.026 (0,66)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
1
0.360 (9,14)
0.240 (6,10)
24
0.019 (0,48)
0.015 (0,38)
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5 / B 03/95
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI004 – OCTOBER 1994
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
PINS **
A
24
28
A MAX
1.260
(32,04)
1.425
(36,20)
A MIN
1.230
(31,24)
1.385
(35,18)
B MAX
0.310
(7,87)
0.315
(8,00)
B MIN
0.290
(7,37)
0.295
(7,49)
DIM
24
13
0.280 (7,11)
0.250 (6,35)
1
12
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0°– 15°
0.010 (0,25) M
0.010 (0,25) NOM
4040050 / B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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