TI CD54ACT191F3A

CD54AC191,
CD54ACT191
Data sheet acquired from Harris Semiconductor
SCHS243A
Presettable Synchronous 4-Bit Binary
Up/Down Counter
October 1998 - Revised May 2000
Features
Description
• Buffered Inputs
The CD54AC191 and CD54ACT191 are asynchronously
presettable binary up/down synchronous counters that utilize
Advanced CMOS Logic technology. Presetting the counter to
the number on preset data inputs (P0-P3) is accomplished
by setting LOW the asynchronous parallel load input (PL).
Counting occurs when PL is HIGH, Count Enable (CE) is
LOW, and the Up/Down (U/D) input is either LOW for upcounting or HIGH for down-counting. The counter is incremented or decremented synchronously with the LOW-toHIGH transition of the clock.
• Typical Propagation Delay
- 12.8ns at VCC = 5V, TA = 25oC, CL = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
When an overflow or underflow of the counter occurs, the
Terminal Count (TC) output, which is LOW during counting,
goes HIGH and remains HIGH for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 12). The TC output also initiates the Ripple
Clock (RC) output which, normally HIGH, goes LOW and
remains LOW for the low-level cascaded using the Ripple
Count output.
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
Ordering Information
PART
NUMBER
TEMP.
RANGE (oC)
Pinout
CD54AC191, CD54ACT191
(CERDIP)
TOP VIEW
PACKAGE
CD54AC191F3A
-55 to 125
16 Ld CERDIP
CD54ACT191F3A
-55 to 125
16 Ld CERDIP
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information.
P1 1
16 VCC
Q1 2
15 P0
Q0 3
14 CP
CE 4
13 RC
U/D 5
12 TC
Q2 6
11 PL
Q3 7
10 P2
GND 8
9 P3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © 2000, Texas Instruments Incorporated
1
CD54AC191, CD54ACT191
Functional Diagram
BINARY
PRESET
P0
15
P1
1
P2
10
P3
9
ASYN. PARALLEL 11
LOAD ENABLE
3
2
CLOCK
Q1
14
6
7
UP/DOWN
Q0
5
Q2
BINARY
OUTPUTS
Q3
12 TERMINAL
COUNT
COUNT
ENABLE
13
4
RIPPLE CLOCK
TRUTH TABLE
INPUTS
PL
CE
U/D
CP
FUNCTION
H
L
L
↑
Count Up
H
L
H
↑
Count Down
L
X
X
X
Asynchronous Preset
H
H
X
X
No Change
U/D or CE should be changed only when clock is high.
X = Don’t Care
↑ = Low-to-High clock transition.
2
CD54AC191, CD54ACT191
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA
Thermal Resistance (Typical, Note 5)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VIH
-
-
1.5
1.2
-
1.2
-
1.2
-
V
AC TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
VIL
VOH
-
VIH or VIL
3
2.1
-
2.1
-
2.1
-
V
5.5
3.85
-
3.85
-
3.85
-
V
1.5
-
0.3
-
0.3
-
0.3
V
3
-
0.9
-
0.9
-
0.9
V
5.5
-
1.65
-
1.65
-
1.65
V
-0.05
1.5
1.4
-
1.4
-
1.4
-
V
-0.05
3
2.9
-
2.9
-
2.9
-
V
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-4
3
2.58
-
2.48
-
2.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
-
3
CD54AC191, CD54ACT191
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Low Level Output Voltage
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VOL
VIH or VIL
0.05
1.5
-
0.1
-
0.1
-
0.1
V
0.05
3
-
0.1
-
0.1
-
0.1
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
12
3
-
0.36
-
0.44
-
0.5
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
High Level Input Voltage
VIH
-
-
4.5 to
5.5
2
-
2
-
2
-
V
Low Level Input Voltage
VIL
-
-
4.5 to
5.5
-
0.8
-
0.8
-
0.8
V
High Level Output Voltage
VOH
VIH or VIL
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
Input Leakage Current
Quiescent Supply Current
MSI
ACT TYPES
Low Level Output Voltage
Input Leakage Current
Quiescent Supply Current
MSI
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
VOL
VIH or VIL
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
2.4
-
2.8
-
3
mA
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.
ACT Input Load Table
INPUT
UNIT LOAD
P0-P3, PL
0.75
CL, U/D, CE
0.85
NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.
4
CD54AC191, CD54ACT191
Prerequisite For Switching Function
PARAMETER
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
MAX
MIN
MAX
UNITS
fMAX
(Note 10)
1.5
5.5
-
4.8
-
MHz
3.3
(Note 8)
49
-
43
-
MHz
5
(Note 9)
68
-
60
-
MHz
1.5
91
-
104
-
ns
3.3
10.5
-
11.6
-
ns
5
7.3
-
8.3
-
ns
1.5
66
-
75
-
ns
3.3
7.4
-
8.4
-
ns
5
5.3
-
6
-
ns
1.5
71
-
81
-
ns
3.3
8
-
9.1
-
ns
5
5.7
-
6.5
-
ns
1.5
44
-
50
-
ns
3.3
4.9
-
5.6
-
ns
5
3.5
-
4
-
ns
1.5
115
-
131
-
ns
3.3
12.9
-
14.7
-
ns
5
9.2
-
10.5
-
ns
1.5
132
-
150
-
ns
3.3
14.7
-
16.8
-
ns
5
10.5
-
12
-
ns
1.5
22
-
25
-
ns
3.3
2.5
-
2.8
-
ns
5
2
-
2
-
ns
1.5
0
-
0
-
ns
3.3
0
-
0
-
ns
5
0
-
0
-
ns
1.5
0
-
0
-
ns
3.3
0
-
0
-
ns
5
0
-
0
-
ns
AC TYPES
Max. Frequency
CP Pulse Width
PL Pulse Width
Recovery Time
Set-Up Time, Pn to PL
Set-Up Time, CE to CP
Set-Up Time, U/D to CP
Hold Time, Pn to PL
Hold Time, CE to CP
Hold Time, U/D to CP
tW
tW
tREC
tSU
tSU
tSU
tH
tH
tH
ACT TYPES
Max. Frequency
fMAX
(Note 10)
5
(Note 9)
68
-
60
-
MHz
CP Pulse Width
tW
5
7.3
-
8.3
-
ns
PL Pulse Width
tW
5
5.3
-
6
-
ns
Recovery Time
tREC
5
5.7
-
6.5
-
ns
tSU
5
3.5
-
4
-
ns
Set-Up Time, Pn to PL
5
CD54AC191, CD54ACT191
Prerequisite For Switching Function
(Continued)
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
MAX
MIN
MAX
UNITS
Set-Up Time, CE to CP
tSU
5
9.2
-
10.5
-
ns
Set-Up Time, U/D to CP
tSU
5
10.5
-
12
-
ns
Hold Time, Pn to PL
tH
5
2
-
2
-
ns
Hold Time, CE to CP
tH
5
0
-
0
-
ns
Hold Time, U/D to CP
tH
5
0
-
0
-
ns
PARAMETER
NOTES:
8. 3.3V Min is at 3V.
9. 5V Min is at 4.5V.
10. Applies to non-cascaded operation only. With cascaded counters clock-to-terminal count propagation delays, count enable (CE)-to-clock
set-up times, and count enable (CE)-to-clock hold times determine max clock frequency. For example, with these AC devices at 85oC
and VCC = 5V:.
1
1
f MAX ( CP ) = -------------------------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ ≈ 36MHz
CP-to-TC prop. delay + CE-to-CP setup + CE-to-CP Hold 18.2 + 9.2 + 0
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
-40oC TO 85oC
PARAMETER
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tPLH, tPHL
1.5
-
-
171
-
-
188
ns
3.3
(Note 12)
5.4
-
19.1
5.3
-
21
ns
5
(Note 13)
3.9
-
13.6
3.8
-
15
ns
1.5
-
-
173
-
-
190
ns
3.3
5.4
-
19.4
5.3
-
21.3
ns
5
3.9
-
13.8
3.8
-
15.2
ns
1.5
-
-
182
-
-
200
ns
3.3
5.8
-
20.4
5.6
-
22.4
ns
5
4.1
-
14.5
4
-
16
ns
1.5
-
-
136
-
-
150
ns
3.3
4.3
-
15.3
4.2
-
16.8
ns
5
3.1
-
11
3
-
12
ns
1.5
-
-
227
-
-
250
ns
3.3
7.2
-
25.5
7
-
28
ns
5
5.2
-
18.2
5
-
20
ns
1.5
-
-
246
-
-
271
ns
3.3
7.8
-
27.6
7.6
-
30.4
ns
5
5.6
-
19.7
5.4
-
21.7
ns
1.5
-
-
160
-
-
176
ns
3.3
5.1
-
17.9
4.9
-
19.7
ns
5
3.6
-
12.8
3.5
-
14.1
ns
AC TYPES
Propagation Delay
PL to Qn
Propagation Delay
Pn to Qn
Propagation Delay
CP to Qn
Propagation Delay
CP to RC
Propagation Delay
CP to TC
Propagation Delay
U/D to RC
Propagation Delay
U/D to TC
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
6
CD54AC191, CD54ACT191
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
(Continued)
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tPLH, tPHL
1.5
-
-
137
-
-
151
ns
3.3
4.4
-
15.4
4.2
-
16.9
ns
5
3.1
-
11
3
-
12.1
ns
CI
-
-
-
10
-
-
10
pF
CPD
(Note 14)
-
-
96
-
-
96
-
pF
Propagation Delay
PL to Qn
tPLH, tPHL
5
(Note 13)
4.2
-
14.8
4.1
-
16.3
ns
Propagation Delay
Pn to Qn
tPLH, tPHL
5
3.9
-
13.8
3.8
-
15.2
ns
Propagation Delay
CP to Qn
tPLH, tPHL
5
4.1
-
14.5
4
-
16
ns
Propagation Delay
CP to RC
tPLH, tPHL
5
3.1
-
10.9
3
-
12
ns
Propagation Delay
CP to TC
tPLH, tPHL
5
5.2
-
18.2
5
-
20
ns
Propagation Delay
U/D to RC
tPLH, tPHL
5
5.6
-
19.7
5.4
-
21.7
ns
Propagation Delay
U/D to TC
tPLH, tPHL
5
3.8
-
13.5
3.7
-
14.9
ns
Propagation Delay
CE to RC
tPLH, tPHL
5
3.3
-
11.5
3.2
-
12.7
ns
Input Capacitance
CI
-
-
-
10
-
-
10
pF
CPD
(Note 14)
-
-
96
-
-
96
-
pF
PARAMETER
Propagation Delay
CE to RC
Input Capacitance
Power Dissipation Capacitance
ACT TYPES
Power Dissipation Capacitance
NOTES:
11. Limits tested 100%.
12. 3.3V Min is at 3.6V, Max is at 3V.
13. 5V Min is at 5.5V, Max is at 4.5V
14. CPD is used to determine the dynamic power consumption per package.
PD = CPDVCC2 fi + (CL + VCC2 fo) where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
1/fMAX
CP
CP OR CE
VS
tPHL
Qn OR TC
INPUT LEVEL
tW
VS
tPLH
VS
RC
VS
FIGURE 1.
INPUT LEVEL
VS
tPHL
tPLH
VS
VS
FIGURE 2.
7
VS
CD54AC191, CD54ACT191
INPUT LEVEL
Pn
Pn
INPUT LEVEL
VS
tPHL
tPLH
VS
VS
Qn
tW
VS
INPUT LEVEL
VS
VS
PL
tPLH
tPHL
VS
VS
Qn
FIGURE 3.
FIGURE 4.
INPUT LEVEL
Pn
VS
tW
tH(H)
tSU(H)
INPUT LEVEL
PL
VS
VS
VS
PL
tH(L)
tSU(L)
INPUT LEVEL
VS
INPUT LEVEL
tREC
CP
Qn
Qn
The shaded areas indicate when the input is permitted to change for
predictable output performance.
FIGURE 6.
FIGURE 5.
INPUT LEVEL
U/D
VS
VS
tPLH
VS
VS
tPHL
CE
tPLH
VS
RC
FIGURE 7.
RL (NOTE)
500Ω
DUT
CL
50pF
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
AC
ACT
VCC
3V
Input Switching Voltage, VS
0.5 VCC
1.5V
Output Switching Voltage, VS
0.5 VCC
0.5 VCC
Input Level
CE MAY
CHANGE
CE MAY
CHANGE
FIGURE 8.
OUTPUT
OUTPUT
LOAD
tH(L)
(H-L)
ONLY
VS
FIGURE 9. PROPAGATION DELAY TIMES
8
VS INPUT
LEVEL
VS
tSU(L)
tPHL
VS
TC
CP
tSU(H)
VS
INPUT
LEVEL
CD54AC191, CD54ACT191
LOAD
P0
PRESET
INPUTS
P1
H
L
P2
H
P3
H
CLOCK
DOWN/UP
L
ENABLE
L
Q0
H
H
L
Q1
H
L
Q2
Q3
TERMINAL COUNT
H
L
RIPPLE CLOCK
13 14 15
LOAD
0
12
2
COUNT UP
2
INHIBIT
1
0
15 14 13
COUNT DOWN
Sequence:
1. Load (preset) to binary thirteen.
2. Count up to fourteen, fifteen, zero, one, and two.
3. Inhibit.
4. Count down to one, zero, fifteen, fourteen, and thirteen.
FIGURE 10. CD54AC191 DECODE COUNTERS TYPICAL LOAD, COUNT, AND INHIBIT SEQUENCES
DIRECTION
CONTROL
ENABLE
U/D
U/D
U/D
CE
CE
CE
CP
CP
TC
CP
TC
CLOCK
FIGURE 11. SYNCHRONOUS N-STAGE COUNTER WITH PARALLEL GATED TC/RC
DIRECTION
CONTROL
U/D
ENABLE
U/D
RC
RC
U/D
CE
CE
CE
CP
CP
CP
RC
CLOCK
FIGURE 12. SYNCHRONOUS N-STAGE COUNTER USING RIPPLE TC/RC
9
TC
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
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