CD74AC138, CD74ACT138, CD74AC238, CD74ACT238 Data sheet acquired from Harris Semiconductor SCHS234 3-to-8-Line Decoders/Demultiplexers September 1998 Features Description • CD74AC138, CD74ACT138 . . . . . . . . . . . . . . . Inverting The CD74AC138, CD74ACT138, CD74AC238, and CD74ACT238 are 3-to-8-line decoders/demultiplexers that utilize the Harris Advanced CMOS Logic technology. Both circuits have three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs determine which one of the eight normally HIGH outputs of the AC/ACT138 will go LOW or which on of the normally LOW outputs of the AC/ACT238 will go HIGH. Two active LOW and one active HIGH enables (E1, E2 and E3) are provided to simplify the cascading of these devices. • CD74AC238, CD74ACT238 . . . . . . . . . . . Non-Inverting • Buffered Inputs • Typical Propagation Delay - 5ns at VCC = 5V, TA = 25oC, CL = 50pF [ /Title (CD74 AC138 , CD74 ACT13 8, CD74 AC238 , CD74 ACT23 8) /Subject (3to-8Line Decoders/De multiplexers) /Autho r () /Keywords (Harris Semiconductor, Advan ced • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 • SCR-Latchup-Resistant CMOS Process and Circuit Design Ordering Information • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. • Balanced Propagation Delays CD74AC138E 0 to 70oC, -40 to 85, 16 Ld PDIP -55 to 125 E16.3 • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply CD74ACT138E 0 to 70oC, -40 to 85, 16 Ld PDIP -55 to 125 E16.3 CD74AC238E 0 to 70oC, -40 to 85, 16 Ld PDIP -55 to 125 E16.3 CD74ACT238E 0 to 70oC, -40 to 85, 16 Ld PDIP -55 to 125 E16.3 CD74AC138M 0 to 70oC, -40 to 85, 16 Ld SOIC -55 to 125 M16.15 CD74ACT138M 0 to 70oC, -40 to 85, 16 Ld SOIC -55 to 125 M16.15 CD74AC238M 0 to 70oC, -40 to 85, 16 Ld SOIC -55 to 125 M16.15 CD74ACT238M 0 to 70oC, -40 to 85, 16 Ld SOIC -55 to 125 M16.15 • ±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50Ω Transmission Lines Pinout CD74AC138, CD74ACT138, CD74AC238, CD74ACT238 (PDIP, SOIC) TOP VIEW A0 1 A1 2 A2 3 E1 4 E2 5 E3 6 AC/ACT138 Y7 7 AC/ACT238 Y7 GND 8 16 VCC Y0 AC/ACT138 15 Y0 AC/ACT238 14 Y1 AC/ACT138 Y1 AC/ACT238 13 Y2 AC/ACT138 Y2 AC/ACT238 12 Y3 AC/ACT138 Y3 AC/ACT238 11 Y4 AC/ACT138 Y4 AC/ACT238 10 Y5 AC/ACT138 Y5 AC/ACT238 9 Y6 AC/ACT138 Y6 AC/ACT238 NOTES: 17. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 18. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a Trademark of Fairchild Semiconductor. Copyright © Harris Corporation 1998 1 File Number 1909.1 CD74AC138, CD74ACT138, CD74AC238, CD74ACT238 Functional Diagram AC/ACT AC/ACT 238 138 A0 1 15 2 14 3 13 A1 A2 Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 12 4 11 5 10 6 9 E1 E2 E3 7 CD74AC/ACT138 TRUTH TABLE INPUTS ENABLE ADDRESS OUTPUTS E3 (NOTE 4) E0 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X H X X X H H H H H H H H L X X X X H H H H H H H H H L L L L L H H H H H H H H L L L H H L H H H H H H H L L H L H H L H H H H H H L L H H H H H L H H H H H L H L L H H H H L H H H H L H L L H H H H H L H H H L H H L H H H H H H L H H L H H H H H H H H H H L CD74AC/ACT238 TRUTH TABLE INPUTS ENABLE ADDRESS OUTPUTS E3 (NOTE 4) E0 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X H X X X L L L L L L L L L X X X X L L L L L L L L H L L L L H L L L L L L L H L L L H L H L L L L L L H L L H L L L H L L L L L H L L H H L L L H L L L L H L H L L L L L L H L L L H L H L H L L L L L H L L H L H H L L L L L L L H L H L H H H L L L L L L L H NOTES: 19. H = High Level, L = Low Level, X = Don’t Care 20. E0 = E1 + E2 2 CD74AC138, CD74ACT138, CD74AC238, CD74ACT238 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or Ground Current, ICC or IGND (Note 5) . . . . . . . . .±100mA Thermal Resistance (Typical, Note 7) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 6) AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 21. For up to 4 outputs per device, add ±25mA for each additional output. 22. Unless otherwise specified, all voltages are referenced to ground. 23. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VIH - - 1.5 1.2 - 1.2 - 1.2 - V AC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL VOH - VIH or VIL 3 2.1 - 2.1 - 2.1 - V 5.5 3.85 - 3.85 - 3.85 - V 1.5 - 0.3 - 0.3 - 0.3 V 3 - 0.9 - 0.9 - 0.9 V 5.5 - 1.65 - 1.65 - 1.65 V -0.05 1.5 1.4 - 1.4 - 1.4 - V -0.05 3 2.9 - 2.9 - 2.9 - V -0.05 4.5 4.4 - 4.4 - 4.4 - V -4 3 2.58 - 2.48 - 2.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 (Note 8, 9) 5.5 - - 3.85 - - - V -50 (Note 8, 9) 5.5 - - - - 3.85 - V - 3 CD74AC138, CD74ACT138, CD74AC238, CD74ACT238 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V 0.05 3 - 0.1 - 0.1 - 0.1 V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 12 3 - 0.36 - 0.44 - 0.5 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 8, 9) 5.5 - - - 1.65 - - V 50 (Note 8, 9) 5.5 - - - - - 1.65 V II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - 0.8 - 0.8 - 0.8 V High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - 4.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 (Note 8, 9) 5.5 - - 3.85 - - - V -50 (Note 8, 9) 5.5 - - - - 3.85 - V Input Leakage Current Quiescent Supply Current MSI ACT TYPES Low Level Output Voltage Input Leakage Current Quiescent Supply Current MSI Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load VOL VIH or VIL 0.05 4.5 - 0.1 - 0.1 - 0.1 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 8, 9) 5.5 - - - 1.65 - - V 50 (Note 8, 9) 5.5 - - - - - 1.65 V II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 8 - 80 - 160 µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 2.4 - 2.8 - 3 mA NOTES: 24. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 25. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC. ACT Input Load Table INPUT UNIT LOAD A0-A2 0.83 E1, E2 1 E3 0.42 NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. 4 CD74AC138, CD74ACT138, CD74AC238, CD74ACT238 Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS tPLH, tPHL 1.5 - - 125 - - 138 ns 3.3 (Note 11) 4 - 14 3.9 - 15.4 ns 5 (Note 12) 2.8 - 10 2.8 - 11 ns 1.5 - - 114 - - 125 ns 3.3 3.6 - 12.7 3.5 - 14 ns 5 2.6 - 9.1 2.5 - 10 ns 1.5 - - 125 - - 138 ns 3.3 4 - 14 3.9 - 15.4 ns 5 2.8 - 10 2.8 - 11 ns 1.5 - - 170 - - 187 ns 3.3 5.4 - 19.1 5.3 - 21 ns 5 3.9 - 13.6 3.8 - 15 ns 1.5 - - 135 - - 149 ns 3.3 4.3 - 15.2 4.2 - 16.7 ns 5 3.1 - 10.7 3 - 11.9 ns 1.5 - - 189 - - 208 ns 3.3 6 - 21.1 5.8 - 23.2 ns 5 4.3 - 15.1 4.2 - 16.6 ns CI - - - 10 - - 10 pF CPD (Note 13) - - 110 - - 110 - pF Propagation Delay, An to Output (CD74AC/ACT138) tPLH, tPHL 5 (Note 12) 3.1 - 10.9 3 - 12 ns Propagation Delay, E1, E2 to Output (CD74AC/ACT138) tPLH, tPHL 5 2.7 - 9.5 2.6 - 10.5 ns Propagation Delay, E3 to Output (CD74AC/ACT138) tPLH, tPHL 5 2.8 - 10 2.8 - 11 ns Propagation Delay, An to Output (CD74AC/ACT238) tPLH, tPHL 5 4 - 14.2 3.9 - 15.6 ns Propagation Delay, E1, E2 to Output (CD74AC/ACT238) tPLH, tPHL 5 3.7 - 12.9 3.6 - 14.2 ns PARAMETER AC TYPES Propagation Delay, An to Output (CD74AC/ACT138) Propagation Delay, E1, E2 to Output (CD74AC/ACT138) Propagation Delay, E3 to Output (CD74AC/ACT138) Propagation Delay, An to Output (CD74AC/ACT238) Propagation Delay, E1, E2 to Output (CD74AC/ACT238) Propagation Delay, E3 to Output (CD74AC/ACT238) Input Capacitance Power Dissipation Capacitance tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL ACT TYPES 5 CD74AC138, CD74ACT138, CD74AC238, CD74ACT238 Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) (Continued) -40oC TO 85oC PARAMETER -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS Propagation Delay, E3 to Output (CD74AC/ACT238) tPLH, tPHL 5 3.5 - 12.4 3.4 - 13.6 ns Input Capacitance CI - - - 10 - - 10 pF CPD (Note 13) - - 110 - - 110 - pF Power Dissipation Capacitance NOTES: 26. Limits tested at 100%. 27. 3.3V Min at 3.6V, Max at 3V. 28. 5V Min at 5.5V, Max at 4.5V. 29. CPD is used to determine the dynamic power consumption per package. AC: PD = VCC2 fi (CPD + CL) ACT: PD = VCC2 fi (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage. tf = 3ns tr = 3ns tr = 3ns 90% VS INPUT 10% tf = 3ns E1, E2 90% VS GND INPUT GND E3 138 OUTPUT 138 OUTPUT VS VS tPHL tPLH tPHL tPLH VS VS 238 OUTPUT tPLH 238 OUTPUT tPLH tPHL tPHL FIGURE 8. PROPAGATION DELAY TIMES FIGURE 9. PROPAGATION DELAY TIMES OUTPUT RL (NOTE) 500Ω DUT OUTPUT LOAD CL 50pF NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ. CD74AC CD74ACT VCC 3V Input Switching Voltage, VS 0.5 VCC 1.5V Output Switching Voltage, VS 0.5 VCC 0.5 VCC Input Level FIGURE 10. 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