PRELIMINARY 1.28 Gbit SDRAM ELECTRONICS 3DSD1280-323H 1.28 GBit Synchronous DRAM - Hermetic package Features General Description Organized as 40M x 32-bit. Single +3.3V ±0.3V power supply Two stacks of ten 64 MBit SDRAM mounted on ceramic hermetic package Fully synchronous; all signals registered on positive edge of system clock. Internal pipelined operation; column address can be changed every clock cycle. Programmable burst lengths: 1, 2, 4, 8 or full page. Auto Precharge, includes Concurrent Auto Precharge, and Auto Refresh Modes. Self Refresh Mode LVTTL - compatible inputs and outputs Vcc and Vss are decoupled with four 10nF and four 100nF capacitors inside the module MIL-STD-883D Class S screening temperature range : -15°C to +80° The 3DSD1280-323H is a highly integrated Synchronous Dynamic Random Access Memory ceramic module, containing 1,342,177,280 bits. It is organized with ten banks of 128 Mbit. Each Bank has a 32-bit interface, and is selected with specific CS#. All other signals are common to the twenty 64 MBit SDRAM memories. It is particularly well suited for use in high performance and high density aerospace applications, such as solid state recorder for airbornes and satellites. The 3DSD1280-323H is packaged in a 84-pin CQFJ. Pin Description A1 A0 Vcc A5 A4 A3 A2 Vcc A7 A6 GND NC GND NC/A12* DQM BS1 BS0 A11 A10 A9 A8 Pin configuration for 3DSD1024-0863S 84 64 63 1 Vcc DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 Vcc GND DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 GND TOP VIEW NC GND DQ24 DQ25 DQ26 DQ27 DQ28 NC Vcc DQ8 DQ9 DQ10 DQ11 DQ12 DQ29 DQ30 DQ31 GND DQ13 DQ14 DQ15 Vcc CS6# CS5# CS4# CS3# CS2# CS1# CS0# CKE GND RAS# CS9# CS8# CS7# Vcc NC GND 43 22 Vcc NC CLK WE# CAS# 21 DQ0-DQ31 Data Inputs/Outputs A0-A12* Address CAS# Column Address Select RAS# Row Address Select WE# Write Enable CS0# - CS9# Chip Select BS0,BS1 Bank Address Input CLK Clock CKE Clock Enable DQM Input/Output Mask Vcc Power (+3.3v) GND Ground NC No Connection Block Diagram VCC DQ[0...15] A[0...12] CLK RAS CAS WE 42 CLK RAS CAS WE CS[0...9] CKE UDQM LDQM * : A12 is a provision for 256Mb components extension VCC DQ[0...15] A[0...11] BSO BS1 A12/NC GND VCC CLK DQ[0...15] RAS CAS A[0...11] WE BSO CS[0...9] BS1 CKE A12/NC UDQM LDQM GND BSO BS1 CS[0...9] CKE DQM GND 3D PLUS, 641 rue Hélène Boucher - ZI F-78532 BUC Cedex FRANCE Tel : 33 (0)1 30 83 26 50 FAX : 33 (0)1 39 56 25 89 Web : http://www. 3d-plus.com 3DFP-0008 Rev : 2 December 1999 Page 1/2 1.28 Gbit SDRAM ELECTRONICS 3DSD1280-323H A e b Dimensions (mm) 34.29 ± 0.25 B 33.02 ± 0.50 b 0.432 typ. A A r 0.762 ref. h 18.35 ± 0.35 e 1.27 ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (Stressed greater than those listed may cause permanent damage to the device) (Voltage referenced to GND, Ta = -15°C to +80°C) Parameter Power Supply Voltage Power Supply Voltage for Output Input Voltage Output Voltage Symbol Rating Units Vcc - 0.3 to +4.6 V Power Supply Voltage Vccq - 0.3 to +4.6 V Vin - 0.3 to Vcc+0.3 V Vout - 0.3 to Vcc+0.3 V Symbol Min Typ Vcc, VccQ 3.0 Input High Voltage VIH 2.0 Input Low Voltage VIL -0.3 Operating Temperature Tope -15 ICC1 Parameter Max Units 3.3 3.6 V - Vcc+0.3 V - 0.8 V +80 °C 300 mA Storage temperature Tstg - 55 to +150 °C Operating with one bank oper-ation Short Circuit Output Current Iout TBD mA Standby in power down mode ICC2 20 mA Operating (burst) ICC3 300 mA TEST TOOLS PRODUCT MARKING 3DSD1280-323H Support YAMAICHI IC51-1004-405-1 - 3D PLUS Logo - Part Number - Date Code (ww,yy) PN : 3DSD1280-323H /883D-S DC : 2599 ORDERING INFORMATION - Serial Number on request 3DSD1280-323H/PROTO CQFJ 84 - prototype ( 0°C to +70°C ) 3DSD1280-323H/883D-S CQFJ 84 - MIL STD 883D - Class S ( -15°C to +80°C ) MAIN SALES OFFICE France 3D PLUS Tel : 33 (0)1 30 83 26 50 Fax : 33 (0)1 39 56 25 89 e-mail : [email protected] DISTRIBUTOR 3D PLUS S.A. reserves the right to change or cancel products or specifications without notice. C 3D PLUS, 1999 3D PLUS, 641 rue Hélène Boucher - ZI F-78532 BUC Cedex FRANCE Tel : 33 (0)1 30 83 26 50 FAX : 33 (0)1 39 56 25 89 Web : http://www. 3d-plus.com 3DFP-0008 Rev : 2 December 1999 Page 2/2