WS512K32BV-XXXE 512Kx32 3.3V SRAM MODULE PRELIMINARY* FEATURES ■ ■ ■ ■ ■ ■ Access Times of 15†, 17, 20ns ■ MIL-STD-883 Compliant Devices Available ■ Low Voltage Operation Commercial, Industrial and Military Temperature Ranges 3.3 Volt Power Supply BiCMOS TTL Compatible Inputs and Outputs Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation ■ Weight WS512K32BV-XG2XE - 8 grams typical WS512K32NBV-XH2XE - 13 grams typical ■ Packaging • 66-pin, PGA Type, 1.385 inch square Hermetic Ceramic HIP (Package 402) • 68 lead, Hermetic CQFP (G2), 22mm (0.880 inch) square (Package 500). Designed to fit JEDEC 68 lead 0.990" CQFJ footprint ■ Organized as 512Kx32; User Configurable as 1Mx16 or 2Mx8 ■ Radiation Tolerant with Epitaxial Layer Die * This data sheet describes a product under development, not fully characterized, and is subject to change without notice. † This speed is Advanced information. 4 PIN DESCRIPTION TOP VIEW 1 12 23 WE2 I/O8 CS2 I/O9 34 I/O15 I/O14 45 VCC I/O24 CS4 I/O25 56 I/O31 I/O0-31 Data Inputs/Outputs A0-18 Address Inputs WE1-4 Write Enables I/O30 CS1-4 Chip Selects I/O10 GND I/O13 I/O26 WE4 I/O29 OE Output Enable A13 I/O11 I/O12 A6 I/O27 I/O28 VCC Power Supply A14 A10 OE A7 A3 A0 A15 A11 A18 NC A4 A1 A16 A12 WE1 A8 A5 A2 A17 VCC I/O7 A9 WE3 I/O23 I/O0 CS1 I/O6 I/O16 CS3 I/O22 I/O1 NC I/O5 I/O17 GND I/O21 I/O4 I/O18 GND Ground NC Not Connected BLOCK DIAGRAM WE1 CS 1 512K x 8 I/O3 I/O2 11 22 33 I/O19 44 I/O20 55 WE3 CS 3 WE 4CS4 8 512K x 8 8 512K x 8 8 512K x 8 8 66 I/O0-7 February 1998 WE2 CS2 OE A0-18 1 I/O8-15 I/O16-23 I/O24-31 White Microelectronics • Phoenix, AZ • (602) 437-1520 SRAM MODULES PIN CONFIGURATION FOR WS512K32NBV-XH2XE WS512K32BV-XXXE TOP VIEW PIN DESCRIPTION NC A0 A1 A2 A3 A4 A5 CS3 GND CS4 WE1 A6 A7 A8 A9 A10 VCC PIN CONFIGURATION FOR WS512K32BV-XG2XE I/O0-31 Data Inputs/Outputs 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 0.940" WE1 CS 1 WE2 CS2 Write Enables CS1-4 Chip Selects OE Output Enable Vcc Power Supply GND Ground WE3 CS 3 WE 4CS4 A0-18 A16 CS1 OE CS2 A17 WE2 WE3 WE4 A18 NC NC A15 A14 A13 A12 SRAM MODULES A11 Address Inputs OE 512K x 8 8 I/O0-7 White Microelectronics • Phoenix, AZ • (602) 437-1520 A0-18 WE1-4 The White 68 lead G2 CQFP fills NC Not Connected the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2 has the TCE and lead inspection advantage of the BLOCK DIAGRAM CQFP form. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 VCC 4 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 2 512K x 8 8 I/O8-15 512K x 8 8 I/O16-23 512K x 8 8 I/O24-31 WS512K32BV-XXXE ABSOLUTE MAXIMUM RATINGS Parameter TRUTH TABLE Symbol Min Max Unit CS OE WE Mode Data I/O Power TA -55 +125 °C °C H L L L X L X H X H L H Standby Read Write Out Disable High Z Data Out Data In High Z Standby Active Active Active Operating Temperature TSTG -65 +150 Signal Voltage Relative to GND VG -0.5 4.6 V Junction Temperature TJ 150 °C 4.6 V Storage Temperature Supply Voltage VCC -0.5 CAPACITANCE (TA = +25°C) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Supply Voltage VCC 3.0 3.6 V OE capacitance COE VIN = 0 V, f = 1.0 MHz Input High Voltage VIH 2.2 V CC + 0.3 V CWE VIN = 0 V, f = 1.0 MHz Input Low Voltage VIL -0.3 +0.8 V WE1-4 capacitance HIP (PGA) CQFP G2 Parameter Symbol Conditions Max Unit 50 pF pF 20 20 CS1-4 capacitance CCS VIN = 0 V, f = 1.0 MHz 20 pF Data I/O capacitance CI/O VI/O = 0 V, f = 1.0 MHz 20 pF Address input capacitance CAD VIN = 0 V, f = 1.0 MHz 50 pF This parameter is guaranteed by design but not tested. Parameter Sym Conditions Units Min Max 10 µA Input Leakage Current ILI VIN = GND to VCC Output Leakage Current ILO CS = VIH, OE = VIH, VOUT = GND to VCC 10 µA ICC x 32 CS = VIL , OE = VIH, f = 5MHz, VCC = 3.6V 480 mA Standby Current ISB CS = VIH, OE = VIH, f = 5MHz, VCC = 3.6V 110 mA Output Low Voltage VOL IOL = 8mA 0.4 V Output High Voltage VOH IOH = -4.0mA Operating Supply Current (x 32 Mode) 2.4 V NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V 3 White Microelectronics • Phoenix, AZ • (602) 437-1520 SRAM MODULES DC CHARACTERISTICS (VCC = 3.3V ± 0.3V, VSS = 0V, TA = -55°C to +125°C) 4 WS512K32BV-XXXE AC CHARACTERISTICS (VCC = 3.3V, TA = -55°C to +125°C) Parameter Symbol -15* Read Cycle Min Read Cycle Time t RC Address Access Time t AA Output Hold from Address Change t OH Chip Select Access Time t ACS -17 Max 15 Min -20 Max 17 Min Max 20 15 ns 17 0 Units 0 20 ns 20 ns 10 ns 0 15 ns 17 Output Enable to Output Valid t OE Chip Select to Output in Low Z t CLZ 1 2 7 2 8 2 Output Enable to Output in Low Z t OLZ 1 0 0 0 Chip Disable to Output in High Z t CHZ 1 7 8 10 ns Output Disable to Output in High Z t OHZ 1 7 8 10 ns ns ns 1. This parameter is guaranteed by design but not tested. * Advanced information. AC CHARACTERISTICS (VCC = 3.3V, TA = -55°C to +125°C) 4 SRAM MODULES Parameter Symbol Write Cycle -15* Min -17 Max Min -20 Max Min Units Max Write Cycle Time t WC 15 17 20 ns Chip Select to End of Write t CW 10 12 14 ns Address Valid to End of Write t AW 10 12 14 ns Data Valid to End of Write t DW 8 9 10 ns Write Pulse Width t WP 12 14 14 ns Address Setup Time t AS 0 0 0 ns Address Hold Time t AH 0 0 0 ns Output Active from End of Write t OW 1 2 3 3 Write Enable to Output in High Z t WHZ 1 Data Hold Time 8 0 t DH ns 8 0 9 ns 0 ns 1. This parameter is guaranteed by design but not tested. * Advanced information. AC TEST CIRCUIT AC TEST CONDITIONS Parameter I OL Current Source VZ D.U.T. ≈ 1.5V (Bipolar Supply) C eff = 50 pf I OH Current Source White Microelectronics • Phoenix, AZ • (602) 437-1520 4 Typ Unit Input Pulse Levels VIL = 0, VIH = 2.5 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: V Z is programmable from -2V to +7V. I OL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω. V Z is typically the midpoint of VOH and V OL. I OL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. WS512K32BV-XXXE TIMING WAVEFORM - READ CYCLE tRC ADDRESS tAA CS tRC tCHZ tACS ADDRESS tCLZ tAA OE tOE tOLZ tOH DATA I/O PREVIOUS DATA VALID DATA I/O DATA VALID tOHZ DATA VALID HIGH IMPEDANCE READ CYCLE 1 (CS = OE = VIL, WE = VIH) READ CYCLE 2 (WE = VIH) 4 WRITE CYCLE - WE CONTROLLED SRAM MODULES tWC ADDRESS tAW tAH tCW CS tAS tWP WE tOW tWHZ tDW DATA I/O tDH DATA VALID WRITE CYCLE 1, WE CONTROLLED WRITE CYCLE - CS CONTROLLED tWC WS32K32-XHX ADDRESS tAS tAW tAH tCW CS tWP WE tDW DATA I/O tDH DATA VALID WRITE CYCLE 2, CS CONTROLLED 5 White Microelectronics • Phoenix, AZ • (602) 437-1520 WS512K32BV-XXXE PACKAGE 402: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2) 35.2 (1.385) ± 0.38 (0.015) SQ PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM 25.4 (1.0) TYP 5.7 (0.223) MAX 4 3.81 (0.150) ± 0.1 (0.005) 1.27 (0.050) ± 0.1 (0.005) 0.76 (0.030) ± 0.1 (0.005) SRAM MODULES 2.54 (0.100) TYP 1.27 (0.050) TYP DIA 15.24 (0.600) TYP 0.46 (0.018) ± 0.05 (0.002) DIA 25.4 (1.0) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES White Microelectronics • Phoenix, AZ • (602) 437-1520 6 WS512K32BV-XXXE PACKAGE 500: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2) 25.1 (0.990) ± 0.25 (0.010) SQ 5.1 (0.200) MAX 22.4 (0.880) ± 0.25 (0.010) SQ 0.25 (0.010) ± 0.1 (0.002) 0.25 (0.010) REF Pin 1 R 0.25 (0.010) 24.0 (0.946) ± 0.25 (0.010) 0.25 (0.010) ± 0.127 (0.005) 1° / 7° 1.0 (0.040) ± 0.127 (0.005) 23.87 (0.940) REF DETAIL A 1.27 (0.050) TYP 4 SEE DETAIL "A" 0.38 (0.015) ± 0.05 (0.002) 20.3 (0.800) REF 0.940" TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 7 White Microelectronics • Phoenix, AZ • (602) 437-1520 SRAM MODULES The White 68 lead G2 CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2 has the TCE and lead inspection advantage of the CQFP form. WS512K32BV-XXXE ORDERING INFORMATION W S 512K 32 X B V - XXX X X E X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads E = Epitaxial Layer DEVICE GRADE: M = Military Screened I = Industrial C = Commercial -55°C to +125°C -40°C to +85°C 0°C to +70°C PACKAGE TYPE: H2 = Ceramic Hex-In-line Package, HIP (Package 402) G2 = 22 mm Ceramic Quad Flat Pack, CQFP (Package 500) ACCESS TIME (ns) 4 Low Voltage Supply 3.3V ± 10% SRAM MODULES BiCMOS IMPROVEMENT MARK: N = No Connect at pin 21 and 39 in HIP for Upgrades ORGANIZATION, 512Kx32 User configurable as 1Mx16 or 2Mx8 SRAM WHITE MICROELECTRONICS White Microelectronics • Phoenix, AZ • (602) 437-1520 8