TI TAS5100A

SLES030 − FEBRUARY 2002
D Internet Music Appliance
D Mini/Micro Component Systems
FEATURES
D TAS5000 + TAS5100A TDAA System-High
D
D
D
D
D
D
D
D
Quality Digital Audio Amplification
93-dB Dynamic Range (TDAA System)
THD+N < 0.08% (1 kHz, 1 W to 30 W RMS
Into 6 Ω)
Power Efficiency > 90% Into 8-Ω Load
Low Profile, SMD 32-Pin PowerPAD Package
Requires No Heat-Sink When Using
Recommended Layout
30-W RMS Continuous Power Into 4 Ω to 8 Ω
Self-Protecting Design
3.3-V Digital Interface
EMI Compliant When Used With
Recommended System Design
DESCRIPTION
True digital audio amplifier (TDAA) is a new paradigm
in digital audio. The TDAA system currently consists of
the TAS5000 PCM-PWM modulator device +
TAS5100A PWM power output device. This system
accepts a serial PCM digital audio stream and converts
it to a 3.3-V PWM audio stream (TAS5000). The
TAS5100A device then provides a large-signal PWM
output. This digital PWM signal is then demodulated
providing power output for driving loudspeakers. This
patented technology provides low-cost, high-quality,
high-efficient digital audio applicable to many audio
systems developed for the digital age. The TAS5100A
is a single-channel PWM power audio device. It
contains integrated gate drivers, four matched and
electrically isolated enhancement- mode N-channel
power DMOS transistors. Also, included are protection
and fault-reporting circuitry. This device is optimized for
use with the TAS5000 digital modulator.
APPLICATIONS
D DVD Receiver
D Home Theater
D Car Audio Amplifiers and Head Units
TYPICAL TDAA STEREO AUDIO SYSTEM
Left
TAS5100
A
Digital Audio
• TAS3001
• DSP
• SPDIF
• 1394
•
•
•
•
•
Volume
EQ
DRC
Bass
Treble
L-C
Filter
TAS5000
Right
TAS5100
A
• Serial Audio Input Port
• Internal PLL
• PCM−PWM Modulator
L-C
Filter
• 2 H-Bridge Power Devices
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and Equibit are trademarks of Texas Instruments.
! "#$ %!&
% "! "! '! ! !( !
%% )*& % "!+ %! !!$* $%!
!+ $$ "!!&
Copyright  2002, Texas Instruments Incorporated
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1
SLES030 − FEBRUARY 2002
terminal assignments
The TAS5100A is offered in a thermally enhanced 32-pin HTSSOP surface-mount package (DAP).
DAP PACKAGE
(TOP VIEW)
PWM_AP
PWM_AM
ERR1
ERR0
SHUTDOWN
DVDD
DVSS
DVSS
DVSS
VRFILT
BIAS_A
BIAS_B
PWDN
RESET
PWM_BM
PWM_BP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PVDDA2
LDROUTA
BOOTSTRAPA
PVDDA1
PVDDA1
OUTPUTA
OUTPUTA
PVSS
PVSS
OUTPUTB
OUTPUTB
PVDDB1
PVDDB1
BOOTSTRAPB
LDROUTB
PVDDB2
ordering information
TA
0°C to 70°C
TAS5100ADAP
PACKAGE
−40°C to 85°C
TAS5100AIDAP
references
TAS5000 Digital Audio PWM Process Data Manual − TI Literature Number SLAS270
System Design Considerations for True Digital Audio Power Amplifiers − TI Literature Number SLAA117
Digital Audio Measurements − TI Literature Number SLAA114
PowerPAD Thermally Enhanced Package − TI Literature Number SLMA002
2
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SLES030 − FEBRUARY 2002
PVDDA1
PVDDA1
BOOTSTRAPA
PVDDA2
LDROUTA
functional block diagram
1/2 H-Bridge
LDR
OUTPUTA
PWM_AP
PWM_AM
DIFF
RCVR
OUTPUTA
Boot Strap
Gate Drive
PVSS
BIAS_A
PWDN
RESET
SHUTDOWN
ERR1
ERR0
Control/Sense
Circuit
Bandgap
Reference
LDROUTB
PVDDB2
VRFILT
BOOTSTRAPB
PVDDB1
1/2 H-Bridge
BIAS_B
PVDDB1
LDR
DIFF
RCVR
OUTPUTB
Boot Strap
Gate Drive
OUTPUTB
PVSS
DVSS
PWM_BP
DVDD
PWM_BM
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3
SLES030 − FEBRUARY 2002
suggested system block diagrams
See application note SLAA117 for more details.
Digital Audio
• USB
• IEEE 1394
• SPDIF
• ADC
• Automotive
MOST
Network
Left
TAS3001
IIC
Audio
Control
TAS5100A
TAS5000
Right
• Digital Parametric EQ • Serial Audio Input Port TAS5100A
• Volume
• Internal PLL
• DRC
• Two H-Bridges
• Bass
• Treble
Figure 1. System #1: Stereo Configuration With TAS3001 Digital Audio Processor
CH1
TAS5000
Home Theater
DVD 6-Channel
Encoded Digital
Audio Source
6
TI DSP
• Dolby AC-3
• DTS
• Volume
• EQ
• DRC
• Bass
• Treble
Left
TAS5100A
Right
TAS5100A
Surround Left
CH2
CH3
TAS5000
TAS5100A
CH4
TAS5100A
CH5
TAS5000
TAS5100A
Center
TAS5100A
Subwoofer
CH6
TAS5100A
Figure 2. System #3: 6-Channel Audio Playback
4
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Surround Right
SLES030 − FEBRUARY 2002
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
BIAS_A
11
I
Connect external resistor to DVSS. See application note SLAA117
BIAS_B
12
I
Connect external resistor to DVSS. See application note SLAA117
BOOTSTRAPA
30
O
Bootstrap capacitor pin for H-bridge A
BOOTSTRAPB
19
O
Bootstrap capacitor pin for H-bridge B
DVDD
6
I
3.3-V digital voltage supply for logic
DVSS
7, 8, 9
I
Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not
connected externally to PVSS. See Figure 5.
ERR1
3
O
Error/warning report indicator. This output is open drain with internal pullup resistor.
ERR0
4
O
Error/warning report indicator. This output is open drain with internal pullup resistor.
LDROUTA
31
O
Low voltage drop-out regulator output A (not to be used to supply current to external circuitry)
LDROUTB
18
O
Low voltage drop-out regulator output B (not to be used to supply current to external circuitry)
OUTPUTA
26, 27
O
H-bridge output A
OUTPUTB
22, 23
O
H-bridge output B
PVDDA1
28, 29
I
High voltage power supply, H-bridge A
PVDDA2
32
I
High voltage power supply for low-dropout voltage regulator A-side
PVDDB1
20, 21
I
High voltage power supply, H-bridge B
PVDDB2
17
I
High voltage power supply for low-dropout voltage regulator B-side
PVSS
24, 25
I
High voltage power supply ground
PWDN
13
I
Power down = 0, normal mode = 1
PWM_AP
1
I
PWM input A(+)
PWM_AM
2
I
PWM input A(−)
PWM_BP
16
I
PWM input B(+)
PWM_BM
15
I
PWM input B(−)
RESET
14
I
Reset and mute mode = 0, normal mode = 1, when in reset mode, H-bridge MOSFETs are in low-low
output state. Asserting the RESET signal low causes all fault conditions to be cleared.
SHUTDOWN
5
O
Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0, when device is in
shutdown mode the H-bridge MOSFETs are in low-low output state. The latched output can be
cleared by asserting the RESET signal. This output is open drain with internal pullup resistor.
VRFILT
10
O
A filter capacitor must be added between VRFILT and DVSS pins.
NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS5000 output pins, and never
left floating. Floating PWM input pins causes an illegal PWM input state signal to be asserted.
Dual pins: OUTPUTA, OUTPUTB, PVDDA1 and PVDDB1 must have both pins connected externally to the same point on the circuit board,
respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high current DMOS output
devices. Failure to connect all the multiple pins to the same respective node results in excessive current flow in the internal bond wires
and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins connected to the same
node, respectively.
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5
SLES030 − FEBRUARY 2002
functional description
PWM H-bridge state control
The digital interface control signals consists of PWM_AP, PWM_AM, PWM_BP, and PWM_BM. These signals
are a complementary differential signal format for the A-side H-bridge and the B-side H-bridge.
bootstrapped gate drive
The TAS5100A includes two dedicated bootstrapped power supplies. A bootstrap capacitor is connected
between the individual bootstrap pin and the associated output as described in the application note SLAA117.
For example, a capacitor is connected between the BOOTSTRAPA pin and OUTPUTA pin, and another
capacitor is connected between the BOOTSTRAPB pin and the OUTPUTB pin. The bootstrap power supply
minimizes the number of high voltage power supply levels externally supplied to the system while providing a
low noise supply level for driving the high-side N-channel DMOS transistors. See application note SLAA117 for
details.
low-dropout voltage regulator
Two on-chip low-dropout voltage regulators (LDO) are provided to minimize the number of external power
supplies needed for the system. These voltage regulators are for internal circuits only and cannot be used for
external circuitry. Each LDO is dedicated to an H-bridge and its gate driver. An LDO output capacitor is
connected between the individual LDO output pin and the associated output return as described in the
application note SLAA117. For example, a capacitor is connected between the LDROUTA pin and PVSS pin,
and another capacitor is connected between the LDROUTB pin and PVSS pin.
high-current H-bridge output stage
The positive outputs of the H-bridge are the two OUTPUTA pins. The negative outputs of the H-bridge are the
two OUTPUTB pins. The logic for the input command to H-bridge outputs is described in the H-bridge output
mapping section below. When the TAS5100A is in the normal mode, as seen in the H-bridge output mapping
tables, the outputs are decoded from the inputs. However, the TAS5100A is immediately shut down if any of
the following error conditions occur: over-current, over-temperature, low regulator output voltage, or an illegal
PWM input state is applied. For these conditions, the outputs are set to the appropriate disabled state as
specified in the H-bridge output mapping section, and the SHUTDOWN pin is set low.
H-bridge output mapping
The A-side H-bridge output is designed to the following truth table:
INPUTS
OUTPUTS
PWDN
PWM_AP
PWM_AM
SHUTDOWN
X
X
X
X
0
OUTPUTA
0 or Hi-Z†
X
0
X
X
1
Hi-Z
0
1
X
X
1
0
Reset
1
1
0
0
0
0
Shutdown
1
1
0
1
1
0
Normal
1
1
1
0
1
1
Normal
1
1
1
1
0
0
† Output is 0 for low voltage, over temperature, and illegal input. Hi-Z is for over current.
6
DESCRIPTION
RESET
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Shutdown
Powerdown
Shutdown
SLES030 − FEBRUARY 2002
H-bridge output mapping (continued)
The B-side H-bridge output is designed to the following truth table:
INPUTS
OUTPUTS
DESCRIPTION
RESET
PWDN
PWM_BP
PWM_BM
SHUTDOWN
X
X
X
X
0
OUTPUTB
0 or Hi-Z†
X
0
X
X
1
Hi-Z
Powerdown
0
1
X
X
1
0
Reset
1
1
0
0
0
0
Shutdown
1
1
0
1
1
0
Normal
1
1
1
0
1
1
Normal
1
1
1
1
0
0
Shutdown
Shutdown
† Output is 0 for low voltage, over temperature, or illegal input. Hi-Z is for over current.
control/sense circuitry
The control/sense circuitry consists of the following 3.3-V logic level pins: PWDN, RESET, ERR0, ERR1, and
SHUTDOWN. The active-low PWDN input pin powers down all internal circuitry and forces the H-bridge outputs
to the Hi-Z state. When the PWDN pin is low, the open drain ERR0, ERR1, and SHUTDOWN pins are also
disabled so that their outputs can be pulled high. The active-low RESET input pin forces the H-bridge outputs
to the low-low state and resets the over-current shutdown latch. The PWDN pin overrides the RESET pin. The
ERR0, ERR1, and SHUTDOWN outputs indicate the following conditions in the TAS5100A as shown in the table
below. These three outputs are open-drain connections with internal pullup resistors so that wire-ORed
connections can be made by the user with other external control devices. The short circuit protect error condition
latches the TAS5100A in this shutdown state and force the H-bridge outputs to the Hi-Z state until the device
is reset by means of the RESET pin. The illegal PWM input state, over-temperature, and low regulator voltage
error conditions do not latch the device in the shutdown condition. Instead the H-bridge outputs are forced to
the low-low state and the TAS5100A returns to normal operation as soon as the error condition ends. Loss of
clocking PWM signal is also considered an illegal PWM input state.
SHUTDOWN
ERR1
ERR0
OUTPUTA
OUTPUTB
0
0
0
Illegal PWM input state
FUNCTION
Low
Low
0
0
1
Short circuit protect (latch)
Hi-Z
Hi-Z
0
1
0
Over temperature protect
Low
Low
0
1
1
Low regulator voltage protect
Low
Low
1
0
0
Reserved
—
—
1
0
1
Reserved
—
—
1
1
0
High temperature − warning
Normal
Normal
1
1
1
Normal operation
Normal
Normal
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SLES030 − FEBRUARY 2002
device operation
power sequences
system power-up/power-down sequencing
The recommended power-up/power-down sequence is shown in Figure 3. For proper operation the RESET
signal should be kept LOW when both DVDD and output power (PVDDA1, PVDDA2, PVDDB1, and PVDDB2)
are being applied. The RESET signal should remain LOW for at least 1 ms after output power is applied.
DVDD†
PWDN
> 1 ms
> 1 ms
PVDDA1
PVDDA2
PVDDB1
PVDDB2
> 100 µs
RESET
† For most applications, it is recommended that pin 13 (PWDN) be connected directly to pin 6 (DVDD).
Figure 3. Power-Up/Power-Down Sequence
RESET function
The device is put into a reset condition when the (active low) RESET signal is asserted. While in the reset state,
the input H-bridge control signals consisting of PWM_AP, PWM_AM, PWM_BP, and PWM_BM are ignored, and
the H-bridge MOSFETs are placed in a state where OUTPUTA and OUTPUTB are both low. Asserting the
RESET signal low also causes the short circuit protection latch to be reset. The RESET signal is normally
connected to the VALID signal from the TAS5000.
reinitialization sequence
Proper initial conditions for this device include asserting the RESET signal until the reset operation has
completed (1 ms). Additionally, when using this device with the TAS5000 controller, this function can be
accomplished by asserting the reset pin on the TAS5000 during the reset sequence (see Figure 3).
audio application considerations
power supply decoupling
Power supply decoupling and layout optimization information should be obtained by following the detailed
information in the application note SLAA117.
optimal power transfer for H-bridge
The TAS5100A is a power H-bridge that is designed to deliver 30 W/rms into loads of 4 Ω to 8 Ω. Rather than
requiring the usual heatsink, the package is designed to deliver this wattage by careful layout as described in
the application note SLAA117. Careful attention must be given to the value of the high-voltage power supply
level for a given load resistance. See recommended operating conditions.
8
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SLES030 − FEBRUARY 2002
audio application considerations (continued)
reconstruction output filter
An output reconstruction filter is required between the H-bridge outputs and the loudspeaker load. This second
order low-pass filter passes the audio information to the loudspeaker, while filtering out the high frequency
out-of-band information contained in the H-bridge output PWM pulses. The values of the L and C components
selected are dependent on the loudspeaker load impedance. See application note SLAA117.
fault indicator usage
The TAS5100A is a self-protecting device that provides device fault reporting, including over-temperature
protect, under-voltage lockout (low-regulator voltage), and short circuit protection. The short circuit protection
protects against short circuits that may occur at the loudspeaker load when configured according to the
application note SLAA117. The TAS5100A is not recommended for driving loads less than 4 Ω, since the internal
current limit protection might be activated.
An under-voltage lockout signal occurs when an insufficient voltage level is present on the LDROUTA or
LDROUTB pins. During this condition gate drive levels are not sufficient for driving the power MOSFETs. Normal
operation is resumed when the minimum proper LDROUTA or LDROUTB level is obtained, and the low regulator
voltage protect signal is de-asserted. See the control/sense circuitry section for error and warning conditions.
A high temperature warning signal is asserted on pin ERR0 when the device temperature exceeds 130°C
typical.
If the internal device temperature exceeds 150°C typical, the over temperature protect signal is asserted and
the TAS5100A is shut down. The device re-enables once the temperature drops to 130°C typical. See the
control/sense circuitry section for error and warning conditions.
Detection of an illegal PWM input state or the loss of a clocking PWM input signal causes an illegal PWM input
state signal to be asserted on the ERR1and ERR0 pins and sets the SHUTDOWN pin to the low state.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
DC supply voltage range: DVDD to DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.2 V
PWM_AP, PWM_AM, PWM_BP, PWM_BM . . . . . . . . . . . . . . . . . −0.3 V to DVDD + 0.3 V
RESET, PWDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DVDD + 0.3 V
PVDDA1 to PVSS, PVDDB1 to PVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 28 V
PVDDA2 to PVSS, PVDDB2 to PVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 27 V
Output DMOS drain-to-source breakdown voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 V
Continuous DMOS RMS drain current, each output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A
Continuous source-to-drain RMS body diode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE
DISSIPATION DERATING TABLE
TA ≤ 25°C†
DERATING FACTOR
ABOVE TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
DAP
5.3 W
42.5 mW/°C
3.4 W
† See the Texas Instruments document, PowerPAD Thermally Enhanced Package Application
Report (literature number SLMA002), for more information on the PowerPAD package. The
thermal data was measured on a PCB layout based on the information in the section entitled Texas
Instruments Recommended Board for PowerPAD of the before mentioned document. Data in
table is for specified layout. Under other conditions the thermal performance may vary. See Texas
Instruments document SLAA117 for more detailed application information.
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9
SLES030 − FEBRUARY 2002
recommended operating conditions (nominal output power = 30 W (RMS), TA = 25°C)
thermal data†
MIN
PARAMETER
NOM
MAX
UNIT
Shutdown junction temperature, TJ(SD)
150
°C
Warning junction temperature, TJ(W)
130
°C
Operating ambient temperature, TA
0
25
70
°C
Thermal resistance junction-to-case, θjc
2 oz. trace and copper pad with solder
0.32
°C/W
Thermal resistance junction-to-ambient, θja
2 oz. trace and copper pad with solder
23.5
°C/W
Thermal resistance junction-to-case, θjc
2 oz. trace and copper pad without solder
0.32
°C/W
Thermal resistance junction-to-ambient, θja
2 oz. trace and copper pad without solder
44.3
°C/W
† One of the most influential components on the thermal performance of a package is board design. In order to take full advantage of the heat
dissipating abilities of the PowerPAD packages, a board must be used that acts similar to a heat sink and allows for the use of the exposed (and
solderable), deep downset pad. See Appendix A of the PowerPAD Thermally Enhanced Package application note, TI literature number SLMA002
and the Thermal Design of the PowerPad PCB Layout section of the System Design Considerations for True Digital Audio Power Amplifiers
application note, TI literature number SLAA117.
RL = 4 Ω to 8 Ω
Digital
Supply voltage
Regulator
PARAMETER
MIN
NOM
MAX
DVDD to DVSS
3
3.3
3.6
PVDDA2 to PVSS
16.5
22
24
PVDDB2 to PVSS
16.5
22
24
PVDDA2 to PVSS}
10.5
16.5
PVDDB2 to PVSS}
10.5
16.5
UNIT
V
V
‡ Connect LDROUTA to PVDDA2 and connect LDROUTB to PVDDB2. Under this condition H-Bridge forward on-state resistance is increased.
This increases internal power dissipation. Maximum output power may need to be reduced to meet thermal conditions.
RL = 8 Ω
PARAMETER
Supply voltage
Power
MIN
NOM
MAX
PVDDA1 to DVSS
0
26
27
PVDDB1 to PVSS
0
26
27
MIN
NOM
MAX
PVDDA1 to DVSS
0
23
24
PVDDB1 to PVSS
0
23
24
MIN
NOM
MAX
PVDDA1 to DVSS
0
20
21
PVDDB1 to PVSS
0
20
21
UNIT
V
RL = 6 Ω
PARAMETER
Supply voltage
Power
UNIT
V
RL = 4 Ω
PARAMETER
Supply voltage
10
Power
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UNIT
V
SLES030 − FEBRUARY 2002
static digital specifications
RESET, PWDN, PWM_AP, PWM_AM, PWM_BP, PWM_BM, TA = 25°C, DVDD = 3.3 V
PARAMETERS
MIN
High-level input voltage, VIH
MAX
2
Low-level input voltage, VIL
Input leakage current
UNIT
V
0.8
V
10
µA
−10
ERR0, ERR1, SHUTDOWN, (open drain with internal pullup resistor) TA = 25°C, DVDD = 3.3 V)
PARAMETERS
MIN
Internal pullup resistors from SHUTDOWN, ERR0, ERR1 to DVDD
MAX
15
Low-level output voltage (IO = 4 mA), VOL
UNIT
kΩ
0.4
V
TAS5000/TAS5100A system performance measured at the speaker terminals
See the TI Literature Number SLAA117 for TAS5000/TAS5100A system performance.
electrical characteristics
supply, TA = 25°C (Fswitching = 384 kHz, OUTPUTA and OUTPUTB not connected, DVDD = 3.3 V,
PVDDA1 = 25 V, PVDDB1 = 25 V, PVDDA2 = 22 V, PVDDB2 = 22 V, 50% input duty cycle)
PARAMETER
TYP
Operating
DVDD
PVDDA1
PVDDB1
Supply current
PVDDA2
PVDDB2
MAX
2
PWDN = 0
Operating†
mA
500
6.3
PWDN = 0
6.5
PWDN = 0
† 13-kΩ resistor from BIAS_A (pin 11) to DVSS and 13-kΩ resistor from BIAS_B (pin 12) to DVSS.
µA
mA
25
Operating
UNIT
µA
mA
250
µA
H-Bridge transistors, PVDDA2 = PVDDB2 = 22 V, DVDD = 3.3 V, TA = 25°C (unless otherwise noted)
PARAMETER
Drain-to-source breakdown voltage
TEST CONDITIONS
Forward on-state resistance, low side drivers
OUTPUTA and OUTPUTB to PVSS
ID = 1 mA,
PWDN = 0,
Hi-Z state
ISINK = 2.5 A,
PWM_AP = PWM_BP = 0,
See Notes 2, 3, and 4, PWM_AM = PWM_BM = 1
Forward on-state resistance, high side drivers
PVDDA1 to OUTPUTA, PVDDB1 to OUTPUTB
ISOURCE = 2.5 A,
See Notes 2, 3, and 5,
PWM_AP = PWM_BP = 1,
PWM_AM = PWM_BM = 0
MIN
TYP
28
MAX
UNIT
V
0.2
Ω
0.2
Ω
On-state resistance matching low-side drivers
98%
On-state resistance matching high-side drivers
98%
NOTES: 1. Test time should be < 1 ms to avoid temperature change.
2. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
3. Connect PVDDA2 and PVDDB2 to 22-V power supply with respect to PVSS. LDROUTA, LDROUTB, BOOTSTRAPA, and
BOOTSTRAPB pins open.
4. Connect PVDDA2 to 22-V power supply with respect to PVSS. LDROUTA, LDROUTB, BOOTSTRAPA and BOOTSTRAPB
capacitors are connected respectively. Clock PWM inputs to allow bootstrap capacitors to charge. 93−99% modulation must be used
on PWM_AP, PWM_AM, PWM_BP, and PWM_BM inputs to prevent the activity detector from shutting down the device during this
measurement. Note that Fswitching = 384 kHz.
www.ti.com
11
SLES030 − FEBRUARY 2002
electrical characteristics, voltage regulator, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IO = 5 mA,
See Note 6,
Output voltage (LDROUTA, LDROUTB)
PVDDA2 = PVDDB2 = 18 V to 27 V,
DVDD = 3.3 V
MIN
TYP
MAX
14.5
15.3
16
UNIT
V
NOTE 5: These voltage regulators are for internal gate drive circuits only and are not to be used under any circumstances to supply current to
external circuity.
THERMAL INFORMATION
The thermally enhanced DAP package is based on the 32-pin HTSSOP, but includes a thermal pad (see
Figure 4) to provide an effective thermal contact between the IC and the PWB.
Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down TO-220
type packages have leads formed as gull wings to make them applicable for surface-mount applications. These
packages, however, have two shortcomings: they do not address the low profile requirements (<2 mm) of many
of today’s advanced systems, and they do not offer a terminal-count high enough to accommodate increasing
integration. On the other hand, traditional low-power surface-mount packages require power-dissipation
derating that severely limits the usable range of many high-performance analog circuits.
The PowerPAD package (thermally enhanced HTSSOP) combines fine-pitch surface-mount technology with
thermal performance comparable to much larger power packages.
The PowerPAD package is designed to optimize the heat transfer to the PWB. Because of the very small size
and limited mass of a HTSSOP package, thermal enhancement is achieved by improving the thermal
conduction paths that remove heat from the component. The thermal pad is formed using a patented lead-frame
design and manufacturing technique to provide a direct connection to the heat-generating IC. When this pad
is soldered or otherwise thermally coupled to an external heat dissipater, high power dissipation in the ultrathin,
fine-pitch, surface-mount package can be reliably achieved. See dissipation derating table.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
Figure 4. Views of Thermally Enhanced DAP Package
12
www.ti.com
SLES030 − FEBRUARY 2002
APPLICATION INFORMATION
TAS5100A
1
TAS5000
2
3
Error
Reporting
RESET
PWM_M_L
4
5
3.3 V
6
PWM_P_L
C7
7
8
VALID
9
C2
10
R1
R2
11
12
PWM_AP
PVDDA2
PWM_AM
LDROUTA
ERR1
BOOTSTRAPA
ERR0
PVDDA1
SHUTDOWN
PVDDA1
OUTPUTA
DVDD
DVSS
OUTPUTA
32
22 V
31
30
C3
29
C4
Snubber
Circuit
28
27
L1
26
dc
C1
25
DVSS
PVSS
DVSS
PVSS
VRFILT
OUTPUTB
BIAS_A
OUTPUTB
BIAS_B
PVDDB1
PWDN
PVDDB1
RESET
BOOTSTRAPB
13
14
15
PWM_BM
LDROUTB
PWM_BP
PVDDB2
16
+
_
24
23
22
L2
21
Snubber
Circuit
20
19
C5
C6
18
17
22 V
Figure 5. Typical TAS5100A Application (One Channel Shown)
See the application note, TI literature number SLAA117 for detailed application information.
www.ti.com
13
SLES030 − FEBRUARY 2002
MECHANICAL DATA
DAP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
38 PINS SHOWN
0,30
0,19
0,65
38
0,13 M
20
Thermal Pad
(see Note D)
6,20
NOM
8,40
7,80
0,15 NOM
Gage Plane
1
19
0,25
A
0°−ā 8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
28
30
32
38
A MAX
9,80
11,10
11,10
12,60
A MIN
9,60
10,90
10,90
12,40
DIM
4073257/A 07/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads. Thermal pad size is 3,86 mm X 3,91 mm for the
32-pin TAS5100A device.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
14
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
28-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
TAS5100ADAP
NRND
HTSSOP
DAP
32
TBD
Call TI
Call TI
TAS5100ADAPR
NRND
HTSSOP
DAP
32
TBD
Call TI
Call TI
TAS5100ADAPRG4
NRND
HTSSOP
DAP
32
TBD
Call TI
Call TI
TAS5100AIDAP
NRND
HTSSOP
DAP
32
TBD
Call TI
Call TI
TAS5100AIDAPR
NRND
HTSSOP
DAP
32
TBD
Call TI
Call TI
TAS5100AIDAPRG4
NRND
HTSSOP
DAP
32
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TAS5100ADAPR
DAP
32
SITE 60
330
24
8.6
11.5
1.6
12
24
Q1
TAS5100AIDAPR
DAP
32
SITE 60
330
24
8.6
11.5
1.6
12
24
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
TAS5100ADAPR
DAP
32
SITE 60
367.0
367.0
45.0
TAS5100AIDAPR
DAP
32
SITE 60
367.0
367.0
45.0
Pack Materials-Page 2
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