Implementing the HIP1011 on Hot Swap CPCI Boards for High Availability (HA) Platforms TM Technical Brief P RE L I M I NA R Y August 2000 Introduction As the board is being connected onto the system bus, the ground plane and early power are first connected via the longest pins. The HIP1011 is ground referenced by way of the GND, PWRON and OCSET pins thus holding off the outputs during subsequent connection of the medium length pins that apply the chip and voltage rail bias. Once the system manager recognizes complete board insertion by the BD_SEL# (shortest pin) signal being pulled up to V(I/O), it signals that pin low turning on the HIP1011. With the PWRON, FLTN and the VOUT asserted, the HEALTHY# is pulled low indicating to the system manager HW that the board is powered and ready for use. The PCI_RST# signal is also generated and along with the Local_PCI_RST# initiates configuration of the remaining Hard Ware (HW) on the board. Once complete, ENUM# is asserted by the HW manager and the Soft Ware (SW) configuration starts, resulting in expected I/O activity. A significant enhancement from the BASIC AND FULL platforms to the HA platform is the change from BD_SEL# being hardwired to ground to being a back plane available signal to the system controller. Thus the controller can selectively power each and any board at any time as necessary. The October 1999 release of the CompactPCI Specification PICMG 2.0 R3.0 defines for the CPCI environment such developments as 66MHz operation, 3.3V signaling, the addition of the System Manager, further definition and differentiation of Hot Swap (PICMG 2.1 R1.0) and improved mechanical features. Until now, CPCI Hot Swap features were offered as a vendor proprietary feature with little or no interoperability. PICMG 2.1 R1.0 now defines three Hot Swap system models: Basic, Full and High Availability (HA) each of increasing complexity and automation. Intersil Tech Brief TB358 details the implementation of the HIP1011 on boards for the Basic and Full models. This Tech Brief details important specification enhancements as they pertain to Hot Swap and the HIP1011 solution for boards to be used in HA System platforms. HA Normal Insertion Sequence Figure 1 is a simple diagram illustrating the progression of a normal insertion. A more detailed state diagram can be found in PICMG 2.1 R1.0 section 2.4. In the following state diagrams Px = Physical connection state, Hx = Hardware connection state and Sx = Software connection state. P0 TB386 HA Normal Extraction Sequence Figure 2 illustrates the progression of a normal board extraction. A more detailed state diagram can be found in PICMG 2.1 R1.0 section 2.4. PHYSICAL BOARD INSERTION S3 S3Q P1 H0 BD_SEL# BOARD SEATED AND POWERED-ON BOARD EXTRACTION INITIATED BY EJECTOR HANDLE. SYSTEM MGR ENUM # DRIVES ENUM# TO INDICATE IMPENDING EXTRACTION. OS QUIESCES I/O ACTIVITY S2 S2Q H1 H1F HEALTHY # BOARD REPORTS PGOOD AND PCI_RST # IS RELEASED FROM PCI RESET S1 H2 S0 ENUM # ALL HW CONNECTED AND SW CONNECTION INITIATED H2 S0 I/O ACTIVITY HALTED LED ON PCI_RST# LOCAL PCI_RST# HW DISCONNECTION BY SW BD_SEL# HEALTHY # S1 H1 H1F S2 S2Q SW CONFIGURATION COMPLETED P1 H0 PHYSICAL EXTRACTION NORMAL I/O ACTIVITY S3 S3Q P0 FIGURE 1. 1 FIGURE 2. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 Technical Brief 386 The extraction process begins with the opening of the ejector handle. The SW connection control drives ENUM# low to indicate impending extraction of the board. The OS initiates the quiescing of I/O activity and disassociation from the board. An LED lights to indicate the H2 / S0 state has been reached and that removal can continue. The SW now electrically isolates the board by asserting PCI_RST# and deasserting BD_SEL#. Once the back end power drops, HEALTHY# is pulled up indicating the board has been powered down. The board is now electrically cold and ready for complete removal. HA Failed Process Figure 3 illustrates the progression of a Board failure. P0 PHYSICAL BOARD INSERTION P1 H0 BD_SEL# BOARD SEATED AND POWERED-ON H1 H1F H2 S0 HEALTHY # BOARD CANNOT SIGNAL HEALTHY STATUS UPON POWER-UP OR POWER FAILS DURING OPERATION. RESULTS IN BD_SEL# SIGNAL CYCLING OR BOARD REPLACEMENT. S1 Controlling the Connection Process As a specified enhancement in order to provide inter operability for all HA platforms, all Hot Swap boards must support the following signals. All of these signal considerations have been included in the HIP1011BEVAL5 demo board shown in Figure 4. The components and circuitry referenced below can also be found in Figure 4. BD_SEL# BD_SEL# is now an addressable signal in HA platforms. This signal is on 1 of 2 shortest pins. Thus upon sensing and subsequent addressing, all other pins have been connected and are stable. This pin is pulled high to V(I/O) by HW and signaled low to enable power-on. This is accomplished on the HIP1011BEVAL5 demo board through R5 and the inverting buffer on the HIP1011 PWRON pin along with SW1 simulating the signal. This enhancement to CPCI boards provides single board power control at any time necessary to the Hot Swap Controller. HEALTHY# A second signal has been added for HW control and is used to signal that a board has successfully powered-on and is ready to be released from reset and allowed onto the PCI bus. On the HIP1011BEVAL5 demo board this signal is generated by sensing the states of the FLTN, PWRON and 3VISEN pins of the HIP1011. This provides feedback from the 3 areas of concern: fault status, input state and output state respectively. HEALTHY# is low when all requirements are met. The HEALTHY# signal has a minimum requirement of monitoring the ‘PGOOD’ of the boards power supply and can be expanded to include other criteria. Local_PCI_RST# S2 S2Q BOARD EXHIBITS NORMAL ACTIVITY THEN FAILS THUS GOING TO H1F STATE. The third required signal is the Local_PCI_RST# signal, this signal is asserted after HEALTHY# is valid and the system generated PCI_RST# signal is also asserted. Local_PCI_RST# must be deasserted immediately with the loss of HEALTHY#. S3 S3Q FIGURE 3. BD_SEL# Once the system manager recognizes complete board insertion by the BD_SEL# (shortest pin) signal being pulled up to V(I/O) it signals that pin low which turns on the HIP1011. During power-up, if a failure occurs such that HEALTHY# remains high indicating to the system manager HW that the board has experienced a failure and cannot be successfully powered-up. The HW manager then either resets and retries a start-up cycle or returns to the P0 state for board replacement. At anytime during normal operation a failure can occur, resulting in a board being put into a H1F state with the HEALTHY# signal high indicating failure. 2 +12VOUT +5VOUT +3.3VOUT 5V/DIV. 10MS/DIV. -12VOUT HEALTHY# FIGURE 4. Technical Brief 386 Summary The HIP1011 along with a minimal number of power FETs, external logic and passives can be used for effective Hot Swap power control in the CompactPCI High Availability environment. LOAD CM12 100µF CP3 2200µF 3.3V MED C5 0.1µF Q1 ITF86130SK8T -12V MED RM12 RP12 240Ω 47Ω 100µF CP5 RP3 RP5 1.1Ω 2.4Ω 2200µF R1 R2 5mΩ 1% 5mΩ 1% 5V Q2 ITF86130SK8T C8 0.1µF MED HIP1011B C6 0.1µF +12V MED CP12 M12VIN M12VO FLTN M12VG 3V5VG 12VG VCC GND 12VIN 3VISEN C7 0.1µF 3VS OCSET C3 0.033µF 0.033µF C1 C2 0.033µF V(I/O) MED 12VO R5 1.2kΩ 5VISEN 5VS BD_SEL# PWRON R3 6kΩ SHORT V(I/O) R4 1.2kΩ MED R6 1.2kΩ C4 200pF R7 C9 4MΩ 0.01µF GND HEALTHY# MED LONG GND MED BACK PLANE CONNECTOR PIN LENGTH PCI_RST# LOCAL_PCI_RST# CARD SIDE MED FIGURE 5. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 3 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369