www.ti.com SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 TM FEATURES APPLICATIONS D DVD Receiver D Home Theatre D Mini/Micro Component Systems D Internet Music Appliance D 100-W RMS Power (BTL) Into 4 Ω With Less Than 10% THD+N D 80-W RMS Power (BTL) Into 4 Ω With Less Than 0.2% THD+N DESCRIPTION D 0.05% THD+N at 1 W Into 4 Ω The TAS5121 is a high-performance digital amplifier power stage designed to drive a 4-Ω speaker up to 100 W. The device incorporates PurePath Digital technology and can be used with a TI audio PWM processor and a simple passive demodulation filter to deliver high-quality, high-efficiency digital audio amplification. D Power Stage Efficiency Greater Than 90% Into 4 Ω Load D Self-Protecting Design D 36-Pin PSOP3 Package The efficiency of this digital amplifier can be greater than 90%, depending on the system design. Overcurrent protection, overtemperature protection, and undervoltage protection are built into the TAS5121, safeguarding the device and speakers against fault conditions that could damage the system. D 3.3-V Digital Interface D EMI Compliant When Used With Recommended System Design TOTAL HARMONIC DISTORTION + NOISE vs POWER 90 RL = 4 Ω TC = 75°C Gain = 3 dB 80 70 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 UNCLIPPED OUTPUT POWER vs H-BRIDGE VOLTAGE 1 0.1 4Ω 60 6Ω 50 40 30 8Ω 20 10 0.01 0.1 0 1 10 100 P − Power − W 0 4 8 12 16 20 24 28 32 PVDD_X − H-Bridge Voltage − V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PurePath Digital and PowerPAD are trademarks of Texas Instruments. Other trademarks are the property of their respective owners. ! "#$ %!& % "! "! '! ! !( ! %% )*& % "!+ %! !!$* $%! !+ $$ "!!& Copyright 2004, Texas Instruments Incorporated www.ti.com SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. GENERAL INFORMATION ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) Terminal Assignment DKD PACKAGE (TOP VIEW) GND PWM_BP GND RESET DREG_RTN GVDD M3 DREG DGND M1 M2 DVDD SD DGND OTW GND PWM_AP GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 UNITS TAS5121 The TAS5121 is offered in a thermally enhanced 36-pin PSOP3 (DKD) package. The DKD package has the thermal pad on top. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 GVDD_B GVDD_B GND BST_B PVDD_B PVDD_B OUT_B OUT_B GND GND OUT_A OUT_A PVDD_A PVDD_A BST_A GND GVDD_A GVDD_A DVDD TO DGND –0.3 V to 4.2 V GVDD_x TO GND 14.2 V PVDD_X TO GND (dc voltage) PVDD_X TO GND(2)) 33.5 V OUT_X TO GND (dc voltage) OUT_X TO GND(2)) 33.5 V BST_X TO GND (DC voltage) BST_X TO GND(2)) 46 V 48 V 48 V 53 V PWM_XP, RESET, M1, M2, M3, SD, OTW –0.3 V to DVDD + 0.3 V Maximum junction temperature range, TJ Storage temperature –40°C to 150°C –40°C to 125°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. (2) The duration should be less than 100 ns (see application note SLEA025). ORDERING INFORMATION TA PACKAGE TRANSPORT MEDIA DESCRIPTION 0°C to 70°C TAS5121DKD Tube 36-pin PSOP3 0°C to 70°C TAS5121DKDR Tape and reel 36-pin PSOP3 PACKAGE DISSIPATION RATINGS PACKAGE RθJC (°C/W) RθJA (°C/W) 36-Pin DKD PSOP3 0.85 See Note 1 (1) The TAS5121 package is thermally enhanced for conductive cooling using an exposed metal pad area. It is impractical to use the devices with the pad exposed to ambient air as the only heat sinking of the device. For this reason, RθJA, a system parameter that characterizes the thermal treatment, is provided in the Application Information section of the data sheet. An example and discussion of typical system RθJA values are provided in the Thermal Information section. This example provides additional information regarding the power dissipation ratings. This example should be used as a reference to calculate the heat dissipation ratings for a specific application. 2 www.ti.com SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 Terminal Functions TERMINAL NAME BST_A DKD FUNCTION(1) DESCRIPTION 22 P High-side bootstrap supply (BST), external resistor and capacitor to OUT_A required BST_B 33 P High-side bootstrap supply (BST), external resistor and capacitor to OUT_B required DGND 9, 14 P I/O reference ground DREG 8 P Digital supply voltage regulator decoupling pin, 1-µF capacitor connected to DREG_RTN DREG_RTN 5 P Decoupling return pin DVDD 12 P I/O reference supply input: 100 Ω to DREG, decoupled to GND, 0.1-µF capacitor connected to GND 1, 3, 16, 18, 21, 27, 28, 34 P Power ground, connected to system GND 6 P Local GVDD decoupling \pin GVDD_A 19, 20 P Gate drive input voltage GVDD_B 35, 36 P Gate drive input voltage M1 10 I Protection mode selection pin, connect to GND M2 11 I Protection mode selection pin, connect to DREG M3 7 I Output mode selection pin; connect to GND OTW 15 O Overtemperature warning output, open drain with internal pullup resistor, active-low when temperature exceeds 115°C OUT_A 25, 26 O Output, half-bridge A OUT_B 29, 30 O Output, half-bridge B PVDD_A 23, 24 P Power supply input for half-bridge A PVDD_B 31, 32 P Power supply input for half-bridge B PWM_AP 17 I PWM input signal, half-bridge A PWM_BP 2 I PWM input signal, half-bridge B RESET 4 I Reset signal, active-low SD 13 O Shutdown signal for half-bridges A and B (open drain with internal pullup resistor), active-low GND GVDD (1) I = input, O = Output, P = Power 3 www.ti.com SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 FUNCTIONAL BLOCK DIAGRAM GVDD_A GVDD_A BST_A PVDD_A OCH DREG Gate Drive DVDD DREG PWM_AP PWM Receiver Timing Control GVDD_A and Protection DGND OUT_A Gate Drive GND OCL GVDD_B RESET GVDD_B BST_B PVDD_B OCH DREG DVDD DVDD PWM_BP Gate Drive DREG PWM Receiver Timing Control GVDD_B and Protection DGND OUT_B Gate Drive GND OCL GVDD DREG OTW SD M1 M2 M3 4 DREG Protection Logic OT and UVP DREG DREG Internally Connected to GVDD_x DREG_RTN www.ti.com SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 RECOMMENDED OPERATING CONDITIONS DVDD Digital supply (1) Relative to DGND GVDD_x Supply for internal gate drive and logic regulators Relative to GND PVDD_x Half-bridge supply Relative to GND, RL= 4 Ω TJ Junction temperature (1) It is recommended for DVDD to be connected to DREG via a 100-Ω resistor. MIN TYP MAX UNIT 3 3.3 3.6 V 10.8 12 13.2 V 0 30.5 32 V 125 _C 0 ELECTRICAL CHARACTERISTICS PVDD_X = 30.5 V, GVDD_x = 12 V, DVDD connected to DREG via a 100-Ω resistor, RL = 4 Ω, 8X fs = 384 kHz, TAS5026 PWM processor, unless otherwise noted TYPICAL SYMBOL PARAMETER TEST CONDITIONS OVER TEMPERATURE TC=75°C UNITS MIN/TYP/ MAX RL = 4 Ω, THD = 10%, AES17 filter 100 W Typ RL = 4 Ω, THD = unclipped, AES17 filter 80 W Typ RL = 8 Ω, THD =unclipped, AD mode 44 W Typ Po = 1 W/ channel, RL = 4 Ω, AES17 filter 0.05 % Typ Po = 10 W/channel, RL = 4 Ω, AES17 filter 0.1 % Typ Po = 80 W/channel, RL = 4 Ω, AES17 filter 0.2 % Typ TA=25°C TA=25°C AC PERFORMANCE, BTL Mode, 1 kHz Po THD+N Output power Total harmonic distortion + noise Vn Output integrated noise voltage A-weighted, RL = 4 Ω, 20 Hz to 20 kHz, AES17 filter 300 µV Max SNR Signal-to-noise ratio A-weighted, AES17 filter 95 dB Typ DR Dynamic range f = 1 kHz, −60 dB, A-weighted, AES17 filter 95 dB Typ 5 www.ti.com SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 ELECTRICAL CHARACTERISTICS PVDD_X = 30.5 V, GVDD_x = 12 V, DVDD connected to DREG via a 100-Ω resistor, RL = 4 Ω, 8X fs = 384 kHz, TAS5026 PWM processor, unless otherwise noted TYPICAL SYMBOL PARAMETER TEST CONDITIONS TA=25°C OVER TEMPERATURE TA=25°C TC=75°C UNITS MIN/TYP/ MAX INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION V Min V Max 30 mA Max 1 5 mA Max 120 132 mΩ Max 120 132 mΩ Max 7 V Min 8.2 V Max DREG Voltage regulator Io = 1 mA 3.3 IGVDD_x Total GVDD supply current, operating fS = 384 kHz, no load, 50% duty cycle 24 IDVDD DVDD supply current, operating fS = 384 kHz, no load OUTPUT STAGE MOSFETs RDSon,LS Forward on-resistance, low side RDSon,HS Forward on-resistance, high side TJ = 25°C TJ = 25°C INPUT/OUTPUT PROTECTION Vuvp,G Undervoltage protection limit, GVDD 7.6 OTW Overtemperature warning Static 115 °C Typ OTE Overtemperature error Static 150 °C Typ OC Overcurrent protection See Note 1. 9.5 A Min STATIC DIGITAL INPUT SPECIFICATION, PWM, PROTECTION MODE SELECTION PINS AND OUTPUT MODE SELECTION PINS VIH High-level input voltage VIL Low-level input voltage Leakage Input leakage current 2 V Min DVDD V Max 0.8 V Max −10 µA Min 10 µA Max 22 kΩ Min OTW/SHUTDOWN (SD) Internal pullup resistor from OTW and SD to DVDD 32 VOL Low-level output voltage IO = 1 mA 0.4 V Max (1) To optimize device performance and prevent overcurrent (OC) protection activation, the demodulation filter must be designed with special care. See Demodulation Filter Design in the Application Information section of the data sheet and consider the recommended inductors and capacitors for optimal performance. It is also important to consider PCB design and layout for optimum performance of the TAS5121. 6 www.ti.com SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 TYPICAL APPLICATION AND CHARACTERIZATION CONFIGURATION USED WITH TAS5026 PWM PROCESSOR TAS5121DKD 1 2 PWM_AP_1 3 4 5 6 100 nF 7 8 9 1 µF 10 11 100 Ω 12 13 100 nF 14 15 16 PWM_BP_1 17 18 1 µF GND GVDD_B PWM_BP GVDD_B GND RESET DREG_RTN GVDD 34 GND 33 1Ω 100 nF BST_B 2.7 Ω 32 PVDD_B PVDD_B 31 75 nH LPCB‡ 33 nF 10 µH 30 OUT_B DREG OUT_B 29 DGND GND M1 GND 28 TVS Zener† 27 TVS Zener† 26 M2 OUT_A DVDD OUT_A 10 µH 1 µF 1 µF 4.7 kΩ H-Bridge Power Supply 1000 µF 4.7 kΩ 25 33 nF 75 nH LPCB‡ 24 SD PVDD_A DGND PVDD_A OTW BST_A GND GND GND 22 Ω 35 M3 PWM_AP Gate-Drive Power Supply 36 23 21 GVDD_A GVDD_A 2.7 Ω 22 20 1Ω 100 nF 22 Ω 19 33 µF 1 µF Microcontroller † Voltage suppressor diodes: 1SMA33CAT3 ‡ LPCB : Track in the PCB 1,0 mm wide and 50 mm long) 7 www.ti.com SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 TOTAL HARMONIC DISTORTION + NOISE vs POWER 90 RL = 4 Ω TC = 75°C Gain = 3 dB 80 70 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 UNCLIPPED OUTPUT POWER vs H-BRIDGE VOLTAGE 1 0.1 4Ω 60 6Ω 50 40 30 8Ω 20 10 0 0.01 0.1 1 10 0 100 P − Power − W 4 8 12 16 20 24 28 32 PVDD_X − H-Bridge Voltage − V Figure 1 Figure 2 POWER LOSS vs TOTAL OUTPUT POWER UNCLIPPED OUTPUT POWER vs CASE TEMPERATURE 14 100 90 12 80 PO − Output Power − W Power Loss − W 10 8 6 4 70 60 50 40 30 20 2 10 0 0 10 20 30 40 50 60 PO(Total) − Total Output Power − W Figure 3 8 70 80 0 −30 0 30 60 90 TC − Case Temperature − °C Figure 4 120 www.ti.com SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 EFFICIENCY vs TOTAL OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 THD+N − Total Harmonic Distortion + Noise − % 100 90 80 η − Efficiency − % 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 RL = 4 Ω TC = 75°C 75 W 0.1 10 W 1W 0.01 0.001 20 80 100 PO(Total) − Total Output Power − W Figure 6 AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 PO = 1 W TC = 75°C −20 0.3 8Ω −40 0.2 Amplitude − dBr A Amplitude − dBr A 10k 20k Figure 5 0.5 0.4 1k f − Frequency − Hz 6Ω 0.1 −0.0 0.0 −0.1 −0.2 4Ω −60 −80 −100 −120 −0.3 −140 −0.4 −0.5 10 −160 100 1k f − Frequency − Hz Figure 7 10k 20k 0 2 4 6 8 10 12 14 16 18 20 22 f − Frequency − kHz Figure 8 9 www.ti.com SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 THEORY OF OPERATION RECOMMENDATIONS FOR POWERING UP > 1 ms POWER SUPPLIES > 1 ms This power device requires only two power supply voltages, GVDD_x and PVDD_x. GVDD_x is the gate drive supply for the device, which is usually supplied from an external 12-V power supply. GVDD_x is also connected to an internal LDR that regulates the GVDD_x voltage down to the logic power supply, 3.3 V, for the TAS5121 internal logic blocks. Each GVDD_x pin is decoupled to system ground by a 1-µF capacitor. PVDD_x is the H-bridge power supply. Two power pins are provided for each half-bridge due to the high current density. It is important to follow the circuit and PCB layout recommendations for the design of the PVDD_x connection. For component suggestions, see the Typical System Configuration section in this document. For layout guidelines, see the reference design layout for the TAS5121. Following these recommendations is important because they influence key system parameters such as EMI, idle current, and audio performance. When GVDD_x is applied, while RESET is held low, the error latches are cleared, SHUTDOWN is set high, and the outputs are held in a high-impedance state. The bootstrap capacitor is charged by the current path through the internal bootstrap diode and external resistors placed on the PCB from each OUT_x pin to ground. A subsequent section describes the charging of the bootstrap capacitor. Ideally, PVDD_x is applied after GVDD_x. When GVDD_x and PVDD_x are applied, the TAS5121 is ready for operation. PWM input signals can then be applied any time during the power-on sequence, but they must be active and stable before RESET is set high. RESET GVDD PVDD_X PWM_xP The following table describes the input conditions and the output states of the device: INPUTS OUTPUTS RESET PWM PWM SHUT_AP _BP DOWN OUT_ A OUT_ B Condition Description X X X 0 Hi-Z Hi-Z Shutdown 0 X X 1 Hi-Z Hi-Z Reset 1 0 0 1 GND GND 1 0 0 1 PVDD PVDD 1 0 1 1 GND 1 1 1 1 PVDD PVDD PVDD Normal Normal Reserved After the previously mentioned conditions are met, the device output begins. If PWM_AP is equal to a high and PMW_BP is equal to a low, the high-side MOSFET in the A half-bridge of the output H-bridge conducts while the low-side MOSFET in the A half-bridge is not conducting. Because the source of the high-side MOSFET is referenced to the drain of the low-side MOSFET, a bootstrapped gate drive is used to eliminate the need for additional high-voltage power supplies. Under the above condition, the opposite is true for the B half-bridge of the output H-bridge. The low-side MOSFET in B half-bridge conducts while the high-side MOSFET is not conducting; therefore, the load connected between the OUT_A and OUT_B pins has PVDD applied to it from the A side while ground is applied from the B side for the period of time PWM_AP is high and PWM_BP is low. Furthermore, when the PWM signals change to the condition where PWM_AP is low and PWM_BP is high, the opposite condition exists. A constant high level is not permitted on the PWM inputs. This condition causes the bootstrap capacitors to discharge and can cause device damage. 10 www.ti.com SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 A digitally controlled dead-time circuit controls the transitions between the high-side and low-side MOSFETs to ensure that both devices in each half-bridge are not conducting simultaneously. POWERING DOWN For power down of the TAS5121, an opposite approach is necessary. The RESET must be asserted LOW before the valid PWM signal is removed. PRECAUTION The TAS5121 must always start up in the high-impedance (Hi-Z) state. In this state, the bootstrap (BST) capacitor is precharged by a resistor on each PWM output node to ground. See the system configuration. This ensures that the TAS5121 is ready for receiving PWM pulses, indicating either HIGH- or LOW-side turnon after RESET is de-asserted to the back end. With the following pulldown resistor and BST capacitor size, the BST charge time is: C = 33 nF, R = 4.7 kΩ R × C × 5 = 775.5 µs After GVDD has been applied, it takes approximately 800 µs to fully charge the BST capacitor. During this time, RESET must be kept low. After approximately 1 ms the back end BST is charged and ready. RESET can now be released if the PWM modulator is ready and is streaming valid PWM signals to the device. Valid PWM signals are switching PWM signals with a frequency between 350−400 kHz. A constant HIGH level on the PWM+ forces the high-side MOSFET ON until it eventually runs out of BST capacitor energy. Putting the device in this condition should be avoided. In practice this means that the DVDD-to-PWM processor (front-end) should be stable and initialization should be completed before RESET is de-asserted to the TAS5121. CONTROL I/O SD RESET DESCRIPTION 0 0 Reserved 0 1 Device in protection mode, i.e., UVP and/or OC and/or OT error 1(2) 0 Device set high-impedance (Hi-Z), SD forced high 1 1 Normal operation (2) SD is pulled high when RESET is asserted low independent of chip state (i.e., protection mode). This is desirable to maintain compatibility with some TI PWM front ends. Overtemperature Warning Pin: OTW The OTW pin gives a temperature warning signal when temperature exceeds the set limit. The pin is of the open-drain type with an internal pullup resistor to DVDD. OTW DESCRIPTION 0 Junction temperature higher than 115°C 1 Junction temperature lower than 115°C Overall Reporting The SD pin, together with the OTW pin, gives chip state information as described in Table 1. Table 1. Error Signal Decoding OTW SD DESCRIPTION 0 0 Overtemperature error (OTE) 0 1 Overtemperature warning (OTW) 1 0 Overcurrent (OC) or undervoltage (UVP) error 1 1 Normal operation, no errors/warnings Chip Protection The TAS5121 protection function is generally implemented in a closed loop control system with, for example, a system controller. The TAS5121 contains three individual systems protecting the device against fault conditions. All of the error events result in the output stage being set in a high-impedance state (Hi-Z) for maximum protection of the device and connected equipment. The device can be recovered by toggling RESET low and then high, after all errors are cleared. It is recommended that if the error persists, the device is held in reset until user intervention clears the error. Shutdown Pin: SD Overcurrent (OC) Protection The SD pin functions as an output pin and is intended for protection-mode signaling to, for example, a controller or other front-end device. The pin is open-drain with an internal pullup resistor to DVDD. The logic output is, as shown in the following table, a combination of the device state and RESET input: The device has individual current protection on both high-side and low-side power stage FETs. The OC protection works only with the demodulation filter present at the output. See Filter Demodulation Design in the Application Information section of the data sheet for design constraints. 11 www.ti.com SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 Overtemperature (OT) Protection Timing and Function The function of the autorecovery circuit is as follows: A dual temperature protection system asserts a warning signal when the device junction temperature exceeds 115°C and shuts down the device when the junction temperature exceeds 150°C. The OT protection circuit is shared by both half-bridges. 1. An error event occurs and sets the protection latch (output stage goes Hi-Z). 2. The counter is started. 3. After n/2 cycles, the protection latch is cleared but the output stage remains Hi-Z (identical to pulling RESET low). 4. After n cycles, operation is resumed (identical to pulling RESET high) (n = 512). Undervoltage Protection (UVP) Undervoltage lockout occurs when GVDD is insufficient for proper device operation. The UV protection system protects the device under fault power-up and power-down situations by shutting the device down. The UV protection circuits are shared by both half-bridges. Reset Function Error Protection Latch Shutdown SD The reset has two functions: Autorecovery D Reset is used for re-enabling operation after a latched error event. D Reset is used for disabling output stage switching, hard mute function. Use modulator control for soft mute. PWM Counter In protection modes where the reset input functions as the means to re-enable operation after an error event, the error latch is cleared on the falling edge of reset and normal operation is resumed on the rising edge of RESET. AR-RESET Figure 9. Autorecovery Function Latching Shutdown on All Errors (PMODE1) In latching shutdown mode, all error situations result in a power down (output stage Hi-Z). Re-enabling can be done by toggling the RESET pin. All Protection Systems Disabled (PMODE2) PROTECTION MODE In PMODE2, all protection systems are disabled. This mode is purely intended for testing and characterization purposes and thus not recommended for normal device operation. Autorecovery (AR) After Errors (PMODE0) MODE Pins Selection In autorecovery mode (PMODE0) the TAS5121 is self-supported in handling of error situations. All protection systems are active, setting the output stage in the high-impedance state to protect the output stage and connected equipment. However, after a short time the device autorecovers, i.e., operation is automatically resumed provided that the system is fully operational. The autorecovery timing is set by counting PWM input cycles, i.e., the timing is relative to the switching frequency. The AR system is common to both half-bridges. 12 The protection mode is selected by connecting M1/M2 to DREG or DGND according to Table 2. Table 2. Protection Mode Selection M1 M2 0 0 Autorecovery after errors (PMODE 0) PROTECTION MODE 0 1 Latched shutdown on all errors 1 0 Reserved 1 1 Reserved The output configuration mode is selected by connecting the M3 pin to DREG or DGND according to Table 3. www.ti.com SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 Table 3. Output Mode Selection M3 OUTPUT MODE 0 Bridge-tied load output stage (BTL) 1 Reserved APPLICATION INFORMATION In general, 10-µH inductors suffice for most applications. The frequency response of the amplifier is slightly altered by the change in output load resistance; however, unless tight control of frequency response is necessary (better than 0.5 dB), it is not necessary to deviate from 10 µH. The graphs in Figure 11 display the inductance vs current characteristics of two inductors that are suggested for use with the TAS5121. DEMODULATION FILTER DESIGN INDUCTANCE vs CURRENT The TAS5121 amplifier outputs are driven by high-current DMOS transistors in an H-bridge configuration. These transistors are either off or fully on. 11 The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio signal. It is recommended that a second-order LC filter be used to recover the audio signal. Output A L C1 R(Load) C2 Output B 9 L − Inductance − µH TAS5121 DBF1310A 10 DASL983XX−1023 8 7 6 5 L 4 0 5 10 15 I − Current − A Figure 10. Demodulation Filter The main purpose of the demodulation filter is to attenuate the high-frequency components of the output signals that are out of the audio band. Design of the demodulation filter affects the audio performance of the power amplifier significantly. As a result, to ensure proper operation of the overcurrent (OC) protection circuit and meet the device THD+N specifications, the selection of the inductors used in the output filter must be considered according to the following. The rule is that the inductance should remain stable within the range of peak current seen at maximum output power and deliver approximately 5 µH of inductance at 15 A. If this rule is observed, the TAS5121 should not have distortion issues due to the output inductors. This prevents device damage due to overcurrent conditions because of inductor saturation in the output filter. Another parameter to be considered is the idle current loss in the inductor. This can be measured or specified as inductor dissipation (D). The target specification for dissipation is less than 0.05. If this specification is not met, idle current increases. Figure 11. Inductance Saturation The selection of the capacitors that are placed from the output of each inductor to ground is simple. To complete the output filter, use a 1-µF capacitor with a voltage rating at least twice the voltage applied to the output stage (PVDD_x). This capacitor should be a good quality polyester dielectric. THERMAL INFORMATION The following is provided as an example. The thermally enhanced package provided with the TAS5121 are designed to be interfaced directly to heatsinks using a thermal interface compound (for example, Wakefield Engineering type 126 thermal grease.) The heatsink then absorbs heat from the ICs and transfers it to the ambient air. If the heatsink is carefully designed, this process can reach equilibrium and heat can be continually removed from the ICs without device overtemperature shutdown. Because of the efficiency of the TAS5121, heatsinks are smaller than those required for linear amplifiers of equivalent performance. 13 www.ti.com SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 RθJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with roughly the following components: D RθJC (the thermal resistance from junction to case, or in this case the metal pad) D Heatsink compound thermal resistance D Heatsink thermal resistance The thermal grease thermal resistance can be calculated from the exposed pad area and the thermal grease manufacturer’s area thermal resistance (expressed in °C-in2/W). The area thermal resistance of the example thermal grease with a 0.001-inch thick layer is about 0.054 °C-in2/W. The approximate exposed pad area is as follows: 36-pin PSOP3 0.116 in2 Dividing the example thermal grease area resistance by the area of the pad gives the actual resistance through the thermal grease for the device: 36-pin PSOP3 The following table indicates modeled parameters for one TAS5121 IC on a heatsink. The junction temperature is set at 110°C while delivering 70 W RMS into 4-Ω loads with no clipping. It is assumed that the thermal grease is about 0.001 inch thick (this is critical). Table 4. Example of Thermal Simulation 36-Pin PSOP3 Ambient temperature 25°C Power to load 70 W Delta T inside package 5.5°C Delta T through thermal grease 3.2°C Required heatsink thermal resistance 11.0°C/W Junction temperature 110°C System RθJA 12.3°C/W RθJA * power dissipation RθJC 85°C 0.85°C/W As an indication of the importance of keeping the thermal grease layer thin, if the thermal grease layer increases to 0.002 inches thick, the required heatsink thermal resistance increases to 5.2°C/W for the PSOP3 package. 0.47 °C/W REFERENCES The thermal resistance of thermally conductive pads is generally higher than a thin thermal grease layer. Thermal tape has an even higher thermal resistance and should not be used with this package. 1. Digital Audio Measurements application report—TI (SLAA114) 2. PowerPAD Thermally Enhanced technical brief—TI (SLMA002) Heatsink thermal resistance is generally predicted by the heatsink vendor, modeled using a continuous flow dynamics (CFD) model, or measured. 3. System Design Considerations for True Digital Audio Power Amplifiers application report—TI (SLAA117) Thus, for a single monaural IC, the system RθJA = RθJC + thermal grease resistance + heatsink resistance. 4. Voltage Spike Measurement Technique and Specification application note—TI (SLEA025) 14 Package www.ti.com SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 MECHANICAL DATA 15 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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