ETC EUA5202QIR

EUA5202
2-W Stereo Audio Power Amplifier
with Mute
DESCRIPTION
FEATURES
z
The EUA5202 is a stereo audio power amplifier that
delivering 2W of continuous RMS power per channel
into 3-Ω loads. When driving 1W into 8-Ω speakers, the
EUA5202 has less than 0.04% THD+N across its
specified frequency range. Included within this device is
integrated de-pop circuitry that virtually eliminates
transients that cause noise in the speakers.
Amplifier gain is externally configured by means of two
resistors per input channel and does not require external
compensation for settings of 2 to 20 in BTL mode (1 to
10 in SE mode). An internal input MUX allows two sets
of stereo inputs to the amplifier. In notebook
applications, where internal speakers are driven as BTL
and the line (often headphone drive) outputs are required
to be SE, the EUA5202 automatically switches into SE
mode when the SE/BTL inputs is activated. Consume
only 7mA of supply current during normal operation,
and the EUA5202 also features a shutdown function for
power sensitive applications, holding the supply current
at 1µA.
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APPLICATIONS
z Notebook Computers
z Multimedia Monitors
z Digital Radios and Portable TVs
Block Diagram
DS5202 Ver 1.4 Nov. 2004
Output Power at 3Ω Load
- 2W/ch at VDD=5V
- 800mW/ch at 3V
Low Supply Current and Shutdown Current
Integrated Depop Circuit
Mute and Shutdown Control Function
Thermal Shutdown Protection
Stereo Input MUX
Bridge-Tied Load (BTL) or Single-Ended (SE)
Modes.
TSSOP-24 with Thermal Pad
1
EUA5202
Typical Application Circuit
Figure 1. EUA5202 Minimum Configuration Application Circuit
Figure 2. EUA5202 Full Configuration Application Circuit
DS5202 Ver 1.4 Nov. 2004
2
EUA5202
Pin Configurations
Package
Pin Configurations
TSSOP-24 with Thermal
Pad, exposure on the bottom
of the package
Pin Description
PIN
PIN
I/O
HP/ LINE
16
LBYPASS
6
LHPIN
5
I
LLINE IN
LOUT+
LOUT-
I
O
O
LVDD
MUTE IN
MUTE OUT
NC
RBYPASS
4
3
10
1,12,13,
24
7
11
9
17,23
19
RHPIN
20
I
RLINEIN
ROUT+
ROUTRVDD
SE/BTL
SHUTDOWN
21
22
15
18
14
8
I
O
O
I
I
I
TJ
2
O
GND/HS
DS5202 Ver 1.4 Nov. 2004
I
DESCRIPTION
Input MUX control input, hold high to select LHP IN or RHP IN (5, 20), hold
low to select LLINE IN or RLINE IN (4, 21)
Tap to voltage divider for left channel internal mid-supply bias
Left channel headphone input, selected when HP/LINE terminal (16) is held
high
Left channel line input, selected when HP/LINE terminal (16) is held low
Left channel + output in BTL mode, + output in SE mode
Left channel - output in BTL mode, high-impedance state in SE mode
Ground connection for circuitry, directly connected to thermal pad
I
I
O
Supply voltage input for left channel and for primary bias circuits
Mute all amplifiers, hold low for normal operation, hold high to mute
Follows MUTE IN terminal (11), provides buffered output
No internal connection
Tap to voltage divider for right channel internal mid-supply bias
Right channel headphone input, selected when HP/LINE terminal (16) is held
high
Right channel line input, selected when HP/LINE terminal (16) is held low
Right channel + output in BTL mode, + output in SE mode
Right channel - output in BTL mode, high-impedance state in SE mode
Supply voltage input for high channel
Hold low foe BTL mod, hold high for SE mode
Places entire IC in shutdown mode when held high, IDD=5µA
Sources a current proportional to the junction temperature. This terminal should
be left unconnected during normal operation.
3
EUA5202
Ordering Information
Order Number
Package Type
Marking
Operating Temperature range
EUA5202QIR
TSSOP 24
xxxx
EUA5202
-40°C to 85°C
EUA5202QIT
TSSOP 24
xxxx
EUA5202
-40°C to 85°C
EUA5202
□ □ □
Packing
R: Tape& Reel
T: Tube
Operating temperature range
I: Industry Standard
Package Type
Q: TSSOP
DS5202 Ver 1.4 Nov. 2004
4
EUA5202
Absolute Maximum Ratings
„
„
„
„
„
„
„
Supply voltage , VDD------------------------------------------------------------------------------------------6V
Input voltage, V1----------------------------------------------------------------------------0.3V to VDD+0.3V
Continuous total power dissipation------------------------------------------------------------internally limited
Operating free-air temperature range ,TA ------------------------------------------------------- –40°C to 85°C
Operating junction temperature range, TJ ------------------------------------------------------- –40°C to 150°C
Storage temperature range, Tstg ---------------------------------------------------------------–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds-------------------------------------260°C
Recommended Operating Conditions
MIN NOM MAX UNIT
Supply Voltage, VDD
Operating free-air temperature,
TA
Common mode input voltage,
VICM
3
5
5.5
VDD = 5V,
250m W/Ch average
power,
4-Ω stereo BTL drive,
with proper PCB design -40
VDD = 5V,
2 W/Ch average power,
3-Ω stereo BTL drive,
with proper PCB design
-40
and 300 CFM
forced-air cooling
85
VDD = 5V
1.25
4.5
VDD = 3.3V
1.25
2.7
V
85
°C
V
DC Electrical Characteristics, TA=25°C
Symbol
Parameter
Conditions
Stereo BTL
Stereo SE
Stereo BTL
Stereo SE
7.1
3.9
5.7
3.1
11
6
9
5
mA
mA
mA
mA
VDD=5V, Gain=2
5
25
mV
VDD=5V
1.55
VDD=5V
1
VDD=5V
IDD
Supply Current
VDD=3.3V
VOO
IDD (Mute)
Output Offset Voltage
(measured differentially)
Supply Current in Mute
Mode
IDD(SD)
DS5202 Ver 1.4 Nov. 2004
EUA5202
Unit
Min. Typ Max.
IDD in Shutdown
5
mA
5
µA
EUA5202
Typical Ac Operating Characteristics, VDD=5V, TA=25°C, RL=3Ω
Symbol
PO
THD+N
BOM
Parameter
Output Power(each
channel)*1
Total Harmonic Distortion
Plus Noise
Maximum Output Power
Bandwidth
Supply Ripple Rejection
Ratio
Z1
VN
Mute Attenuation
Channel-to- Channel Output
Separation
Line/HP Input Separation
BTL Attenuation in SE
Mode
Input Impedance
Signal-to-Noise Ratio
Output Noise Voltage
Conditions
Typ.
Unit
THD=0.2%, BTL, See Figure 3
THD=1%, BTL, See Figure 3
2
2.2
W
PO=2W, f=1KHz ,See Figure5
200
m%
V1=1V, RL=10kΩ, AV=1V/V
100
m%
AV=10V/V THD <1%, See Figure5
>20
KHz
f=1KHz, See Figure37
65
f=20-20KHz, See Figure37
40
dB
85
dB
85
dB
88
dB
86
dB
2
101
22
MΩ
dB
µV(rms)
Conditions
Typ.
Unit
THD=0.2%, BTL, See Figure 10
THD=1%, BTL, See Figure 10
800
900
W
PO=2W, f=1KHz ,See Figure11
350
m%
V1=1V, RL=10kΩ, AV =1V/V
200
m%
AV=10V/V THD <1%, See Figure11
>20
KHz
f=1KHz, See Figure37
60
f=20-20KHz, See Figure37
40
f=1KHz, See Figure 39
PO=2W,BTL, 5V
See Figure 35
*1: Output Power is measured at the output terminals of the IC at 1 KHz
Typical Ac Operating Characteristics, VDD=3.3V, TA=25°C, RL=3Ω
Symbol
PO
THD+N
BOM
Parameter
Output Power(each
channel)*1
Total Harmonic Distortion
Plus Noise
Maximum Output Power
Bandwidth
Supply Ripple Rejection
Ratio
Z1
VN
Mute Attenuation
Channel-to- Channel Output
Separation
Line/HP Input Separation
BTL Attenuation in SE
Mode
Input Impedance
Signal - to - Noise Ratio
Output Noise Voltage
f=1KHz, See Figure 40
PO=700mW,BTL, 5V
See Figure 36
*1: Output Power is measured at the output terminals of the IC at 1 KHz
DS5202 Ver 1.4 Nov. 2004
6
dB
85
dB
80
dB
88
dB
86
dB
2
96
22
MΩ
dB
µV(rms)
EUA5202
Typical Operating Characteristics
(Table of Graphs)
No
Item
Conditions
Figure Page
1
THD+N vs. Output Power
VDD=5V，RL=3 & 8 ohm，BTL，f=1KHz
3
9
2
THD+N vs. Frequency
VDD=5V，RL=4 ohm，BTL，Po=1.5W
f=20 to 20KHz，Av= -2 & -10 & -20V/V
4
9
3
THD+N vs. Frequency
VDD=5V，RL=3 & 4 ohm，BTL，Po=1.5W ，f=20 to 20KHz
5
9
4
THD+N vs. Output Power
VDD=5V，RL=3 ohm，BTL，f=20 & 1K & 20KHz
6
9
5
THD+N vs. Frequency
VDD=5V，RL=8 ohm，BTL，f=20 to 20KHz，Av=-2V/V
7
9
6
THD+N vs. Output Power
VDD=5V，RL=8 ohm，BTL，Po=1W， Av= -2 &-10 & -20V/V，f=20
to 20KHz
8
9
7
THD+N vs. Output Power
VDD=5V，RL=8 ohm，BTL，f=20 & 1K & 20KHz
9
10
8
THD+N vs. Output Power
VDD=3.3V，RL=3 & 8 ohm，BTL，f=1KHz
10
10
9
THD+N vs. Frequency
11
10
12
10
10 THD+N vs. Frequency
VDD=3.3V，RL=4 ohm，BTL，Po=0.75W，Av= -2 &-10 &-20V/V，
f=20 to 20KHz
VDD=3.3V，RL=4 ohm，BTL，Av=-2V/V， Po=0.1 & 0.35 & 0.75W
& 800mW(RL=3 ohm)
11 THD+N vs. Output Power
VDD=3.3V，RL=3 ohm，BTL，Av=-2V/V，f=20 & 1K & 20KHz
13
10
12 THD+N vs. Frequency
VDD=3.3V，RL=8 ohm，BTL，Po=0.4W ，Av=-2 &-10 & -20V/V
14
10
13 THD+N vs. Frequency
VDD=3.3V，RL=8 ohm，BTL，Av=-2V/V ，Po=0.1 & 0.25 & 0.4W
15
11
14 THD+N vs. Output Power
VDD=3.3V，RL=8 ohm，BTL，Av= -2V/V，f=20 & 1K &20KHz
16
11
15 THD+N vs. Frequency
VDD=5V，RL=4 ohm，SE，Po=0.5W，Av= -1&-5&-10V/V
17
11
16 THD+N vs. Frequency
VDD=5V，RL=4 ohm，SE，Av= -2V/V，Po=0.1 & 0.25 & 0.5W
18
11
17 THD+N vs. Output Power
VDD=5V，RL=4 ohm，SE，Av= -2V/V，f=100 & 1K & 20KHz
19
11
18 THD+N vs. Frequency
VDD=5V，RL=8 ohm，SE，Po=0.25W，Av= -1 &-5 &-10V/V
20
11
19 THD+N vs. Frequency
VDD=5V，RL=8 ohm，SE，Av= -2V/V，Po=0.05 & 0.1 & 0.25W
21
12
20 THD+N vs. Output Power
VDD=5V，RL=8 ohm，SE，Av= -2V/V，f=100 &1K & 20KHz
22
12
21 THD+N vs. Frequency
VDD=5V，RL=32 ohm，SE，Po=0.075W，Av= -1 &-5 &-10V/V
23
12
22 THD+N vs. Frequency
VDD=5V，RL=32 ohm，SE，Av= -1V/V，Po=25 & 50 & 75mW
24
12
23 THD+N vs. Output Power
VDD=5V，RL=32 ohm，SE，Av= -1V/V，f=20 & 1K & 20KHz
25
12
24 THD+N vs. Frequency
VDD=3.3V，RL=4 ohm，SE，Po=0.2W，Av= -1 &-5 &-10V/V
26
12
25 THD+N vs. Frequency
VDD=3.3V，RL=4 ohm，SE，Av= -1V/V，Po=0.05 & 0.1 & 0.2W
27
13
26 THD+N vs. Output Power
VDD=3.3V，RL=4 ohm，SE，Av= -2V/V，f=100 & 1K & 20KHz
28
13
27 THD+N vs. Frequency
VDD=3.3V，RL=8 ohm，SE，Po=100mW，Av= -1 &-5 &-10V/V
29
13
28 THD+N vs. Frequency
VDD=3.3V，RL=8 ohm，SE，Av= -1V/V，Po=25 & 50 &100mW
30
13
29 THD+N vs. Output Power
VDD=3.3V，RL=8 ohm，SE，Av= -1V/V，f=100 & 1K & 20KHz
31
13
30 THD+N vs. Frequency
VDD=3.3V，RL=32 ohm，SE，Po=30mW，Av= -1 &-5 &-10V/V
32
13
31 THD+N vs. Frequency
VDD=3.3V，RL=32 ohm，SE，Av= -1V/V，Po=10 & 20 & 30mW
33
14
32 THD+N vs. Output Power
VDD=3.3V，RL=32 ohm，SE，Av=-1V/V，f=20 & 1K & 20KHz
34
14
DS5202 Ver 1.4 Nov. 2004
7
EUA5202
33 Output Noise Voltage vs. Frequency VDD=5V，BW=22Hz to 22kHz，RL=4
35
14
34 Output Noise Voltage vs. Frequency VDD=3.3V，BW=22Hz to 22kHz，RL=4
36
14
37
14
38
14
Supply Ripple Rejection Ratio vs.
RL=4 ohm，CB=4.7uF，BTL，VDD=3.3 & 5V
Frequency
Supply Ripple Rejection Ratio vs.
RL=4 ohm，CB=4.7uF，SE，VDD=3.3 & 5V
36
Frequency
35
37 Crosstalk vs .Frequency
VDD=5V，Po=1.5W，RL=4 ohm，BTL，Right to Left & Left to Right
39
15
38 Crosstalk vs .Frequency
VDD=3.3V，Po=0.75W，RL=4 ohm，BTL，Right to Left & Left to Right
40
15
39 Crosstalk vs .Frequency
VDD=5V，Po=75mW，RL=32 ohm，SE，Right to Left & Left to Right
41
15
40 Crosstalk vs .Frequency
VDD=3.3V，Po=35mW，RL=32 ohm，SE，Right to Left & Left to Right
42
15
41 Closed Loop Response
VDD=5V，Av=-2V/V，Po=1.5W，BTL，Gain & Phase
43
15
42 Closed Loop Response
VDD=3.3V，Av= -2V/V，Po=0.75W，BTL，Gain &Phase
44
15
43 Closed Loop Response
VDD=5V，Av=-1V/V，Po=0.5W，SE，Gain &Phase
45
16
44 Closed Loop Response
VDD=3.3V，Av= -1V/V，Po=0.25W，SE，Gain &Phase
46
16
45 Supply Current vs. Supply Voltage
Stereo BTL & Stereo SE
47
16
46 Output Power vs. Supply Voltage
THD+N=1%，BTL，Each Channel，RL=3 & 4 & 8 ohm
48
16
47 Output Power vs. Supply Voltage
THD+N=1%，SE，Each Channel，RL=3 & 4 & 8 ohm
49
16
48 Output Power vs. Load Resistance
THD+N=1%，BTL，Each Channel，VDD=3.3 & 5V
50
16
49 Output Power vs. Load Resistance
THD+N=1%，SE，Each Channel，VDD=3.3 & 5V
51
17
50 Power Dissipation vs. Output Power VDD=5V，BTL，Each Channel，RL=3 & 4 & 8ohm
52
17
51 Power Dissipation vs. Output Power VDD=3.3V，BTL，Each Channel，RL=3 & 4 & 8ohm
53
17
52 Power Dissipation vs. Output Power VDD=5V，SE，Each Channel，RL=4 & 8 &32 ohm
54
17
53 Power Dissipation vs. Output Power VDD=3.3V，SE，Each Channel，RL=4 & 8 &32 ohm
55
17
DS5202 Ver 1.4 Nov. 2004
8
EUA5202
DS5202 Ver 1.4 Nov. 2004
Figure 3.
Figure 4.
Figure5.
Figure6.
Figure7.
Figure8.
9
EUA5202
Figure9.
Figure10.
Figure11.
Figure12.
Figure13.
DS5202 Ver 1.4 Nov. 2004
Figure14.
10
EUA5202
Figure15.
DS5202 Ver 1.4 Nov. 2004
Figure16.
Figure17.
Figure18.
Figure19.
Figure20.
11
EUA5202
Figure21.
Figure22.
Figure23.
Figure24.
Figure25.
DS5202 Ver 1.4 Nov. 2004
Figure26.
12
EUA5202
Figure27.
Figure28.
Figure29.
Figure30.
Figure31.
DS5202 Ver 1.4 Nov. 2004
Figure32.
13
EUA5202
Figure33.
DS5202 Ver 1.4 Nov. 2004
Figure34.
Figure35.
Figure36.
Figure37.
Figure38.
14
EUA5202
Figure39.
Figure40.
Figure41.
Figure42.
Figure43.
DS5202 Ver 1.4 Nov. 2004
Figure44.
15
EUA5202
Figure45.
Figure46.
Figure47.
Figure48.
Figure49.
DS5202 Ver 1.4 Nov. 2004
Figure50.
16
EUA5202
Figure51.
Figure52.
Figure53.
Figure54.
Figure55.
DS5202 Ver 1.4 Nov. 2004
17
EUA5202
Application Information
Input Capacitor, CI
In the typical application an input capacitor, CI, is
required to allow the amplifier to bias the input signal to
the proper dc level for optimum operation. In this case,
CI and RI form a high-pass filter with the corner
frequency determined in equation 4.
Gain Setting Resistors, RF and RI
The gain for each audio input of the EUA5202 is set by
resistors by resistors RF and RI according to equation 1
for BTL mode.
R 
 F
BTL Gain = −2
 R 
 I
-------------------------------- (1)
f
BTL mode operation brings about the factor 2 in the gain
equation due to the inverting amplifier mirroring the
voltage swing across the load. Given that the EUA5202
is a MOS amplifier, the input impedance is very high,
value of RF increases. In addition, a certain range of RF
values is required for proper start-up operation of the
amplifier. Taken together it is recommended that the
effective impedance seen by the inverting node of the
amplifier be set between 5kΩ and 20kΩ .The effective
impedance is calculated in equation 2.
F I
R +R
F
-------------------- (2)
I
1
C =
I
2π R f
I C
As an example consider an input resistance of 10kΩ and
a feedback resistor of 50kΩ. The BTL gain of the
amplifier would be -10 and the effective impedance at
the inverting terminal would be 8.3kΩ, which is well
within the recommended range. For high performance
applications metal film resistors are recommended
because they tent to have lower noise levels than carbon
resistors. For values of RF above 50kΩ the amplifier
tends to become unstable due to a pole formed from RF
and the inherent input capacitance of the MOS input
structure. For this reason, a small compensation
capacitor of approximately 5pF should be places in
parallel with RF when RF is greater than 50kΩ. This, in
effect, creates a low pass filter network with the cutoff
frequency defined in equation 3.
1
f (lowpass) =
c
2π R C
F F
1
2π R C
I I
------------------- (4)
------------------------------------ (5)
In this example, CI is 0.40 µF so one would likely
choose a value in the range of 0.47µF to 1µF. A further
consideration for this capacitor is the leakage path from
the input source through the input network (RI, CI) and
the feedback resistor (RF) to the load. This leakage
current creates a dc offset voltage at the input to the
amplifier that reduces useful headroom, especially in
high gain applications. For this reason a low-leakage
tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the
capacitor should face the amplifier input in most
applications as the dc level there is held at VDD/2, which
is likely higher that the source dc level. Please note that
it is important to confirm the capacitor polarity in the
application.
-------------------- (3)
For example, if RF is 100kΩ and CF is 5 pF then fC is 318
KHz, which is well outside of the audio range.
DS5202 Ver 1.4 Nov. 2004
=
The value of CI is important to consider as it directly
affects the bass (low frequency) performance of the
circuit. Consider the example where RI is 10kΩ and the
specification calls for a flat bass response down to 40Hz.
Equation 8 is reconfigured as equation 5.
R R
EffectiveImpedance =
c(highpass )
18
EUA5202
Power Supply Decoupling, CS
The main disadvantage, from a performance standpoint,
is the load impedances are typically small, which drives
the low-frequency corner higher degrading the bass
response. Large values of CC are required to pass low
frequencies into the load. Consider the example where a
CC of 330 µF is chosen and loads vary from 3Ω, 4Ω, 8Ω,
32Ω, 10kΩ, to 47kΩ. Table 1 summarizes the frequency
response characteristics of each configuration.
The EUA5202 is a high-performance CMOS audio
amplifier that requires adequate power supply
decoupling to ensure the output total harmonic distortion
(THD) is as low as possible. Power supply decoupling
also prevents oscillations for long lead lengths between
the amplifier and the speaker. The optimum decoupling
is achieved by using two capacitors of different types of
noise on the power supply leads. For higher frequency
transients, spikes, or digital hash on the line, a good low
equivalent – series - resistance (ESR) ceramic capacitor,
typically 0.1µF placed as close as possible to the device
VDD lead works best. For filtering lower – frequency
noise signals, a larger aluminum electrolytic capacitor of
10 µF or greater placed near the audio power amplifier is
recommended.
Bypass Capacitor, CB
The bypass capacitor, CB, is the most critical capacitor
and serves several important functions. During startup or
recovery from shutdown mode, CB determines the rate at
which the amplifier starts up. The second function is to
reduce noise produced by the power supply caused by
coupling into the output drive signal. This noise is from
the midrail generation circuit internal to the amplifier,
which appears as degraded PSRR and THD+N. Bypass
capacitor, CB, values of 0.1 µF to 1 µF ceramic of
tantalum low-ESR capacitors are recommended for the
best THD and noise performance.
In Figure 2, the full feature configuration, two bypass
capacitors are used. This provides the maximum
separation between right and left drive circuits.When
absolute minimum cost and/or component space is
required, one bypass capacitor can be used as shown in
Figure 1. It is critical that terminals 6 and 19 be tied
together in this configuration.
Output Coupling Capacitor, CC
In the typical single-supply SE configuration, and output
coupling capacitor (CC) is required to block the dc bias
at the output of the amplifier thus preventing dc currents
in the load. As with the input coupling capacitor and
impedance of the load form a high-pass filter governed
by equation 6
Table1. Common Load Impedances vs Low Frequency Output
Characteristics in SE Mode
2π R C
L
CC
Lowest Frequency
3Ω
330 µF
161 Hz
4Ω
330 µF
120 Hz
8Ω
330 µF
60 Hz
32 Ω
330 µF
15 Hz
10000 Ω
330 µF
0.05 Hz
47000 Ω
330 µF
0.01 Hz
As Table 1 indicates, most of the bass response is
attenuated into 4–Ω load, an 8–Ω load is adequate,
headphone response is good, and drive into line level
inputs (a home stereo for example) is exceptional.
Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this
applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series
with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor
in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an
ideal capacitor.
Bridged-tied Load Versus Single-ended Mode
Figure 56 show a linear audio power amplifier (APA) in
a BTL configuration. The EUA 5202 BTL amplifier
consists of two linear amplifiers driving both ends of the
load. There are several potential benefits to this
differential drive configuration, but initially consider
power to the load. The differential drive to the speaker
means that as one side is slewing up, the other side is
slewing down, and vice versa. This in effect doubles the
voltage swing on the load as compared to a ground
referenced load. Plugging 2 × VO(PP) into the power
equation, where voltage is squared, yields 4 × the output
power from the same supply rail and load impedance
(see equation 7 )
1
fc(high)=
RL
---------------------------- (6)
C
V(rms)＝
DS5202 Ver 1.4 Nov. 2004
19
V
O(PP)
2 2
Power ＝
V
(rms)
R
L
2
------ (7)
EUA5202
Increasing power to the load does carry a penalty of
increased internal power dissipation. The increased
dissipation is understandable considering that the BTL
configuration produces 4 × the output power of the SE
configuration. Internal dissipation versus output power is
discussed further in the crest factor and thermal
considerations section.
Single-Ended Operation
In SE mode (see Figure56 and Figure57), the load is
driven from the primary amplifier output for each
channel (OUT+, terminals 22 and 3).
In SE mode the gain is set by the RF and RI resistors and
is shown in equation 9. Since the inverting amplifier is
not used to mirror the voltage swing on the load, the
factor of 2, from equation 5, is not included.
In a typical computer sound channel operating at 5V,
bridging raises the power into an 8-Ω speaker from a
singled -ended (SE, ground reference) limit of 250 mW
to 1W. In sound power that is a 6-dB improvement—
which is loudness that can be heard. In addition to
increased power there are frequency response concerns.
Consider the single-supply SE configuration shown in
Figure 57. A coupling capacitor is required to block the
dc offset voltage from reaching the load. These
capacitors can be quite large (approximately 33µF to
1000µF) so they tend to be expensive, heavy, occupy
valuable PCB area, and have the additional drawback of
limiting low-frequency performance of the system.
This frequency limiting effect is due to the high pass
filter network created with the speaker impedance and
the coupling capacitance and is calculated with equation
8.
fC=
1
2 π R LCC
R 
SE Gain = −  F  -------------------------------------- (9)
 R 
 I
The output coupling capacitor required in single-supply
SE mode also places additional constraints on the
selection of other components in the amplifier circuit.
The rules described earlier still hold with the addition of
the following relationship (see equation 10):
1
 C × 25 k Ω
 B

------------------------------------ (8)
For example, a 68µF capacitor with an 8-Ω speaker
would attenuate low frequencies below 293 Hz. The
BTL configuration cancels the dc offsets, which
eliminates the need for the blocking capacitors.
Low-frequency performance is then limited only by the
input network and speaker response. Cost and PCB
space are also minimized by eliminating the bulky
coupling capacitor.
DS5202 Ver 1.4 Nov. 2004
20
≤
1
 C R 
 I I
<
1
R C
L C
--------------- (10)
EUA5202
Input MUX operation
SE/BTL Operation
The ability of the EUA5202 to easily switch between
BTL and SE modes is one of its most important cost
saving features. This feature eliminates the requirement
for an additional headphone amplifier in applications
where internal stereo speakers are driven in BTL mode
but external headphone or speakers must be
accommodated. Internal to the EUA5202, two separate
amplifiers drive LOUT- and ROUT- (terminals 10 and
15).When SE/ BTL is held high, the OUT- amplifier
are in high output impedance state, which configures the
EUA5202 as an SE driver from LOUT + and ROUT +
(terminal 3 and 22). IDD is reduced by approximately
one-half in SE mode. Control of the SE/ BTL input can
be from a logic-level CMOS source, or, more typically,
from a resistor divider network as shown in Figure 59.
Working in concert with the SE/ BTL feature, the
HP/LINE MUX feature gives the audio designer the
flexibility of a multichip design in a single IC (see
Figure 58). The primary function of the MUX is to allow
different gain settings for BTL versus SE mode.
Speakers typically require approximately a factor of 10
more gain for similar volume listening levels as
compared to headphones. To achieve headphone and
speaker listening parity, the resistor values would need
to be set as follows:
SE Gain
R

 F(HP) 
= −
(HP)
 R I (HP) 


-------------------------- (11)
If, for example RI (HP) = 10 kΩ and RF (HP) = 10kΩ then
SE Gain (HP) = -1
R

F (LINE)  -------------------- (12)
BTL Gain
= −2
(LINE)
 R I (LINE) 


If, for example RI (LINE) = 10kΩ and RF (LINE) = 50kΩ then
BTL Gain (LINE) = -10
Using a readily available 1/8-in. (3.5mm) stereo
headphone jack, the control switch is closed when no
plug is inserted. When closed the 100-kΩ/1-kΩ divider
pulls the SE/ BTL input low. When a plug is inserted,
the OUT- amplifier is shutdown causing the speaker to
mute (virtually open-circuits the speaker). The OUT+
amplifier then drives through the output capacitor (CO)
into the headphone jack. As shown n the full feature
application (Figure 2), the input MUX control can be
tied to the SE/ BTL input. The benefits of doing this are
described in the following input MUX operation section.
Another advantage of using the MUX feature is setting
the gain of the headphone channel to -1. This provides
the optimum distortion performance into the headphones
where clear sound is more important. Refer to the
SE/ BTL operation section for a description of the
headphone hack control circuit.
DS5202 Ver 1.4 Nov. 2004
Mute and Shutdown Mode
The EUA5202 employs both a mute and a shutdown
mode of operation designed to reduce supply current, IDD,
to the absolute minimum level during periods of nonuse
for battery-power conservation. The SHUTDOWN input
terminal should be held low during normal operation
when the amplifier is in use. Pulling SHUTDOWN high
causes the outputs to mute and the amplifier to enter a
low-current state, IDD = 5 µA. SHUTDOWN or MUTE
IN should never be left unconnected because amplifier
operation would be unpredictable. Mute mode alone
reduces IDD to 1.5 mA.
21
EUA5202
Package Information
Use as much
copper area
as possible
Bottom view
Exposed Pad
NOTE
1. Package body sizes exclude mold flash protrusions or gate burrs
2. Tolerance ± 0.1mm unless otherwise specified
3. Coplanarity :0.1mm
4. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.
5. Die pad exposure size is according to lead frame design.
6. Standard Solder Map dimension is millimeter.
7. Followed from JEDEC MO-153
SYMBOLS
A
A1
A2
b
C
D
E
E1
e
L
y
θ
DS5202 Ver 1.4 Nov. 2004
DIMENSIONS IN MILLIMETERS
MIN.
NOM.
MAX.
----------1.15
0.00
-----0.10
0.80
1.00
1.05
0.19
-----0.30
0.09
-----0.20
7.70
7.80
7.90
-----6.40
----4.30
4.40
4.50
-----0.65
----0.45
0.60
0.75
----------0.10
0
-----8
22
DIMENSIONS IN INCHES
MIN.
NOM.
MAX.
----------0.045
0.000
-----0.004
0.031
0.039
0.041
0.007
-----0.012
0.004
-----0.008
0.303
0.307
0.311
-----0.252
-----0.169
0.173
0.177
-----0.026
-----0.018
0.024
0.030
----------0.004
0
-----8