ETC EUA6029

芯美电子
Preliminary
EUA6029
2.5-W Stereo Audio Power Amplifier
with Advanced DC Volume Control
DESCRIPTOIN
FEATURES
The EUA6029 is a stereo audio power amplifier that drives
2.5 W/channel of continuous RMS power into a 4-Ω load.
Advanced dc volume control minimizes external components
and allows BTL (speaker) volume control and SE (headphone)
volume control.
The 20-pin DIP package allows for the use of a heatsink
which provides higher output power.
To ensure a smooth transition between active and shutdown
modes, a fade mode ramps the volume up and down.
z
z
z
2.5 W into 4-Ω Speakers With External Heatsink
DC Volume Control with 2-dB
Step from -40dB to 20dB
-Fade Mode
- -85-dB Mute Mode
Differential Inputs
z
1μA Shutdown Current (Typical)
z
z
Headphone Mode
RoHS Compliant and 100% Lead (Pb)-Free
APPLICATIONS
z
DS6029 Ver 0.1 May. 2007
LCD Monitors
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Preliminary
EUA6029
Block Diagram
DS6029 Ver 0.1 May. 2007
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Preliminary
EUA6029
Typical Application Circuit
Figure 1. Application circuit using single-ended inputs and input MUX
Figure 2. Application circuit using differential inputs
DS6029 Ver 0.1 May. 2007
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Preliminary
EUA6029
Pin Configurations
Package
Pin Configurations(Top View)
DIP-20
Pin Description
PIN
PIN
I/O
DESCRIPTION
BYPASS
16
I
FADE
15
I
AGND
LINLIN+
LOUTLOUT+
NC
PGND
PVDD
RINRIN+
ROUTROUT+
17
7
8
10
12
13
1,11
3,9
5
4
2
20
I
I
O
O
I
I
O
O
SE/ BTL
19
I
Tap to voltage divider for internal midsupply bias generator used for analog reference
Places the amplifier in fade mode if a logic low is placed on this terminal; normal
operation if a logic high is placed on this terminal.
Analog power supply ground
Left channel negative input for fully differential input.
Left channel positive input for fully differential input.
Left channel negative audio output.
Left channel positive audio output.
No connection
Power ground
Supply voltage terminal for power stage
Right channel negative input for fully differential input.
Right channel positive input for fully differential input.
Right channel negative audio output
Right channel positive audio output
Output control. When this terminal is high, SE outputs are selected. When this
terminal is low, BTL outputs are selected.
SHUTDOWN
14
I
Places the amplifier in shutdown mode if a TTL logic low is placed on this terminal
VDD
VOLUME
6
18
I
Supply voltage terminal
Terminal for dc volume control. DC voltage range is 0 to VDD.
DS6029 Ver 0.1 May. 2007
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Preliminary
EUA6029
Ordering Information
Order Number
Package Type
Marking
Operating Temperature range
EUA6029IIR1
DIP-20
xxxxx
EUA6029
-40 °C to 85°C
EUA6029IIT1
DIP-20
xxxxx
EUA6029
-40 °C to 85°C
EUA6029
□ □ □ □
Lead Free Code
1: Lead Free 0: Lead
Packing
R: Tape& Reel
T: Tube
Operating temperature range
I: Industry Standard
Package Type
I: DIP
DS6029 Ver 0.1 May. 2007
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EUA6029
Preliminary
Absolute Maximum Ratings
„
„
„
„
„
„
„
Supply voltage, VDD------------------------------------------------------------------------------------------------ 6V
Input voltage, VI------------------------------------------------------------------------------ –0.3 V to VDD +0.3 V
Continuous total power dissipation --------------------------------------------------------------- internally limited
Operating free-air temperature range, TA--------------------------------------------------------- –40°C to 85° C
Operating junction temperature range, TJ ------------------------------------------------------ - –40°C to 150°C
Storage temperature range, Tstg------------------------------------------------------------------ -- –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds----------------------------------------- 260°C
PACKAGE
PWP
Dissipation Rating Table
TA≦25°C
DERATING FACTOR
1.97 W
17.24 mW/°C
TA = 70°C
1.19 W
TA = 85°C
0.935W
Recommended Operating Conditions
Min
Max
Unit
4
5.5
V
Supply voltage, VDD
High-level input voltage, VIH
Low-level input voltage, VIL
SE/ BTL
4
SHUTDOWN
2
V
SE/ BTL
3
SHUTDOWN
0.8
Operating free-air temperature, TA
-40
V
85
°C
Electrical Characteristics at Specified Free-air Temperature, VDD = PVDD=5.5V, TA = 25°C
Symbol
Parameter
VOO
Output offset voltage
(measured differentially)
PSRR
Conditions
Power supply rejection ratio
EUA6029
Min.
Typ. Max.
Unit
VDD= 5.5V,Gain=0 dB, SE/ BTL =0V
30
mV
VDD= 5.5V,Gain=20 dB, SE/ BTL =0V
50
mV
VDD= PVDD= 4 V to 5.5 V
-40
-68
dB
IIH
High-level input current
( SE/ BTL , SHUTDOWN , VDD= PVDD=5.5V, VI = VDD =PVDD
FADE ,VOLUME,)
1
µA
IIL
Low-level input current
1
µA
IDD
IDD
IDD(SD)
VDD= PVDD=5.5V, VI = 0V
VDD= PVDD=5.5V, , SE/ BTL =0V,
SHUTDOWN =2V
Supply current, no load
VDD= PVDD=5.5V, , SE/ BTL =5.5V
SHUTDOWN =2V
V = PVDD=5.5V, , SE/ BTL =0V,
Supply current, max power into a DD
SHUTDOWN =2V,RL=3Ω,
3-Ω load
Po=2 W, stereo
Supply current, shutdown mode SHUTDOWN =0V
DS6029 Ver 0.1 May. 2007
7.3
mA
4.4
1.5
1
ARMS
20
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µA
芯美电子
EUA6029
Preliminary
Operating Characteristics, VDD =PVDD= 5V, TA = 25°C, RL = 4Ω, Gain =6 dB
Symbol
Parameter
PO
Output power
THD+N
Total harmonic distortion plus
noise
VOH
VOL
V(Bypass)
BOM
Conditions
Min.
Typ.
THD=1%, f=1kHz
1.85
THD=10%, f=1kHz,VDD=5V
2.5
PO=1W, RL=8Ω,f=1 kHz
RL =8Ω,Measured between output
and VDD
RL =8Ω,Measured between output
Low-level output voltage
and GND
Measured at pin 17,No load,
Bypass voltage (Nominally VDD/2)
VDD=5.5V
Maximum output power
THD=5%
bandwidth
Noise output voltage
f =1kHz,Gain=0 dB
C(BYP)=0.47µF
f=20 Hz to 20 kHz,
Gain=0 dB,
C(BYP)=0.47µF,
Input impedance (see Figure 25) VOLUME=5 V
DS6029 Ver 0.1 May. 2007
Max.
Unit
W
<0.4%
High-level output voltage
Supply ripple rejection ratio
ZI
EUA6029
2.65
2.75
700
mV
400
mV
2.85
V
＞20
kHz
BTL mode
-63
dB
SE mode
-57
dB
BTL mode
36
µVRMS
14
kΩ
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DS6029 Ver 0.1 May. 2007
Preliminary
EUA6029
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
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Preliminary
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
DS6029 Ver 0.1 May. 2007
EUA6029
Figure 14
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DS6029 Ver 0.1 May. 2007
Preliminary
EUA6029
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
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Preliminary
EUA6029
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
DS6029 Ver 0.1 May. 2007
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EUA6029
Preliminary
Application Information
Table 1 . SE/ BTL , and Shutdown Function
VOLUME Operation
The VOLUME pin controls the BTL volume when driving
speakers, and the SE volume when driving headphones.
This pin is controlled with a dc voltage, which should not
exceed VDD.
The output volume increases in discrete steps as the dc
voltage increases and decreases in discrete steps as the dc
voltage decreases. There are a total of 32 discrete gain steps
of the amplifier and range from -85 dB to 20 dB for BTL
operation and -85 dB to 14 dB for SE operation.
A pictorial representation of the typical volume control can
be found in Figure 26.
Inputs
SE/ BTL SHUTDOWN
X
Low
High
Low
High
X
Line
Line
HP
HP
Mute
BTL
SE
BTL
SE
X= Do not care
FADE Operation
For design flexibility, a fade mode is provided to slowly
ramp up the amplifier gain when coming out of shutdown
mode and conversely ramp the gain down when going into
shutdown. This mode provides a smooth transition
between the active and shutdown states and virtually
eliminates any pops or clicks on the outputs.
When the FADE input is a logic low, the device is placed
into fade-on mode. A logic high on this pin places the
amplifier in the fade-off mode. The voltage trip levels for
a logic low (VIL) or logic high (VIH) can be found in the
recommended operating conditions table.
When a logic low is applied to the FADE pin and a logic
low is then applied on the SHUTDOWN pin, the channel
gain steps down from gain step to gain step at a rate of
two clock cycles per step. With a nominal internal clock
frequency of 58HZ,this equates to 34 ms (1/24 Hz) per
step. The gain steps down until the lowest gain step is
reached .The time it takes to reach this step depends on the
gain setting prior to placing the device in shutdown. For
example, if the amplifier is in the highest gain mode of
20dB, the time it takes to ramp down the channel gain is
1.05 seconds. This number is calculated by taking the
number of steps to reach the lowest gain from the highest
gain, or 31 steps , and multiplying by the time per step, or
34 ms.
After the channel gain is stepped down to the lowest gain,
the amplifier begins discharging the bypass capacitor from
the nominal voltage of VDD/2 to ground.
This time is dependent on the value of the bypass
capacitor. For a 0.47-µF capacitor that is used in the
application diagram in Figure 1, the time is approximately
500ms. This time scales linearly with the value of bypass
capacitor. For example, if a 1-µF capacitor is used for
bypass, the time period to discharge the capacitor to
ground is twice that of the 0.47-µF capacitor, or 1 second.
Figure 26. Typical DC Volume Control Operation
Shutdown Modes
The EUA6029 employs a shutdown mode of operation
designed to reduce supply current, IDD, to the absolute
minimum level during periods of nonuse for
battery-power conservation. The SHUTDOWN input
terminal should be held high during normal operation
when the amplifier is in use. Pulling SHUTDOWN low
causes the outputs to mute and the amplifier to enter a
low-current state, IDD=20µA.SHUTDOWN should never
be left unconnected because amplifier operation would be
unpredictable.
DS6029 Ver 0.1 May. 2007
Low
High
High
High
High
Amplifier State
INPUT OUTPUT
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EUA6029
Preliminary
When a logic high is placed on the SHUTDOWN pin
and the FADE pin is still held low, the device begins the
start-up process, the bypass capacitor will begin charging.
Once the bypass voltage reaches the final value of
VDD/2 ,the gain increases in2-dB steps from the lowest
gain level to the gain level set by the dc voltage applied to
the VOLUME pins.
In the fade-off mode, the output of the amplifier
immediately drops to VDD/2 and the bypass capacitor
begins a smooth discharge to ground When shutdown is
released, the bypass capacitor charges up to VDD/2 and
the channel gain returns immediately to the value on the
VOLUME terminal.
The power-up sequence is different from the shutdown
sequence and the voltage on the FADE pin does not
change the power-up sequence. Upon a power-up
condition, the EUA6029 begins in the lowest gain
setting and steps up 2 dB every 2 clock cycles until the
final value is reached as determined by the dc voltage
applied to the VOLUME pins.
In a typical computer sound channel operating at 5V,
bridging raises the power into an 8-Ω speaker from a
singled-ended (SE, ground reference) limit of 250 mW to
1W. In sound power that is a 6-dB improvement, which is
loudness that can be heard . In addition to increased power
there are frequency response concerns. Consider the
single-supply SE configuration shown in Figure 28.
A coupling capacitor is required to block the dc offset
voltage from reaching the load. These capacitors can be
quite large (approximately 33µF to 1000µF) so they tend
to be expensive, heavy, occupy valuable PCB area, and
have the additional drawback of limiting low-frequency
performance of the system. This frequency limiting effect
is due to the high pass filter network created with the
speaker impedance and the coupling capacitance and is
calculated with equation 2.
Bridged-Tied Load Versus Single-Ended Mode
Figure 27 show a Class-AB audio power amplifier (APA)
in a BTL configuration. The EUA6029 BTL amplifier
consists of two Class-AB amplifiers driving both ends of
the load. There are several potential benefits to this
differential drive configuration, but initially consider
power to the load. The differential drive to the speaker
means that as one side is slewing up, the other side is
slewing down, and vice versa. This in effect doubles the
voltage swing on the load as compared to a ground
referenced load. Plugging 2×VO(PP) into the power
equation, where voltage is squared, yields 4× the output
power from the same supply rail and load impedance(see
equation 1)
For example, a 68µF capacitor with an 8-Ω speaker would
attenuate low frequencies below 293 Hz. The BTL
configuration cancels the dc offsets, which eliminates the
need for the blocking capacitors. Low-frequency
performance is then limited only by the input network and
speaker response. Cost and PCB space are also minimized
by eliminating the bulky coupling capacitor.
V(rms) = VO(PP)
Power =
2 2
V(rms)
2
fC =
2 π R LCC
----------------------------------(2)
------(1)
RL
Figure 28. Single-Ended configuration and
Frequency Response
Increasing power to the load does carry a penalty of
increased internal power dissipation. The increased
dissipation is understandable considering that the BTL
configuration produces 4 × the output power of the SE
configuration. Internal dissipation versus output power is
discussed further in the crest factor and thermal
considerations section.
Single-Ended Operation
In SE mode the load is driven from the primary amplifier
output for each channel. The amplifier switches
single-ended operation when the SE/ BTL terminal is held
high. This puts the negative outputs in a high-impedance
state, and reduces the amplifier’s gain to 1V/V.
Figure 27.Bridge-Tied Load configuration
DS6029 Ver 0.1 May. 2007
1
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EUA6029
Preliminary
SE/BTL Operation
The ability of the EUA6029 to easily switch between BTL
and SE modes is one of its most important cost saving
features. This feature eliminates the requirement for an
additional headphone amplifier in applications where
internal stereo speakers are driven in BTL mode but
external headphone or speakers must be accommodated.
Internal to the EUA6029 , two separate amplifiers drive
OUT+ and OUT- .The SE/ BTL input control the
operation of the follower amplifier that drives LOUT- and
ROUT-.When SE/ BTL is held low, the amplifier is on and
the EUA6029 is in the BTL mode. When SE/ BTL is held
high, the OUT- amplifiers are in a high output impedance
state, which configures the EUA6029 as an SE driver from
LOUT+ and ROUT+. IDD is reduced by approximately
one-half in SE mode. Control of the SE/ BTL input can be
from a logic-level CMOS source or, more typically, from a
resistor divider network as shown in Figure 29.
Input Resistance
Each gain setting is achieved by varying the input
resistance of the amplifier, which can range from its
smallest value to over 6 times that value. As a results, if a
single capacitor is used in the input high-pass filter, the –3
dB or cut-off frequency will also change by over 6 times.
Figure 30. Input Resistor
The-3dB frequency can be calculated using equation
3:
1
f-3dB =
2 π C (R || R i )
---------------------- (3)
If the filter must be more accurate, the value of the
capacitor should be increased while the value of the resistor
to ground should be decreased. In addition, the order of the
filter could be increased.
Input Capacitor, Ci
In the typical application an input capacitor, Ci, is required
to allow the amplifier to bias the input signal to the proper
dc level for optimum operation. In this case, Ci and the input
impedance of the amplifier, Zi, from a high-pass filter with
the corner frequency determined in equation 4.
Figure 29. Resistor divider Network circuit 2
Using a readily available 1/8-in. (3.5mm) stereo headphone
jack, the control switch is closed when no plug is inserted.
When closed the 100-kΩ /1-kΩ divider pulls the
SE/ BTL input low. When a plug is inserted, the 1-kΩ
resistor is disconnected and the SE/ BTL input is pulled
high. When the input goes high, the OUT- amplifier is shut
down causing the speaker to mute(virtually open-circuits
the speaker).The OUT+ amplifier then drives through the
output capacitor (CO) into the headphone jack.
fc(highpass)=
1
-----------------(4)
2 π Zi Ci
The value of Ci is important to consider as it directly affects
the bass (low frequency) performance of the circuit.
Consider the example where Zi is 70kΩ and the
specification calls for a flat bass response down to 40Hz.
Ci =
1
----------------------------- (5)
2 π Z fC
i
DS6029 Ver 0.1 May. 2007
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In this example, Ci is 56nF so one would likely choose a
value in the range of 56nF to 1µF. A further consideration
for this capacitor is the leakage path from the input source
through the input network (Ci) and the feedback network
to the load. This leakage current creates a dc offset voltage
at the input to the amplifier that reduces useful headroom,
especially in high gain applications. For this reason, a
low- leakage tantalum or ceramic capacitor is the best
choice. When polarized capacitors are used, the positive
side of the capacitor should face the amplifier input in
most applications as the dc level there is held at VDD/2,
which is likely higher than the source dc level. Note that it
is important to confirm the capacitor polarity in the
application.
Output Coupling Capacitor, (CC)
For general signal-supply SE configuration, the output
coupling capacitor (CC) is required to block the dc bias at
the output of the amplifier thus preventing dc currents in
the load. As with the input coupling capacitor, the output
coupling capacitor and impedance of the load form a
high-pass filter governed by equation 6.
fc(high)=
Decoupling Capacitor, (CS)
The EUA6029 is a high-performance CMOS audio
amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD) is as
low as possible. Power supply decoupling also prevents
oscillations for long lead lengths between
the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that
target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on
the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1µF placed as close as
possible to the device VDD lead, works best. For filtering
lower-frequency noise signals, a larger aluminum
electrolytic capacitor of 10µF or greater placed near the
audio power amplifier is recommended.
1
2π R C
L C
------------------------ (6)
The main disadvantage, from a performance standpoint, is
the load impedances are typically small, which drives the
low-frequency corner higher, degrading the bass response.
Large values of CC are required to pass low frequencies
into the load. Consider the example where a
CC of 330µF is chosen and loads vary from 3Ω, 4Ω, 8Ω,
32Ω, 10kΩ, to 47kΩ. Table 2 summarizes the frequency
response characteristics of each configuration.
Bypass Capacitor, (CB)
The bypass capacitor, CB, is the most critical capacitor and
serves several important functions. During start-up or
recovery from shutdown mode, CB determines the rate at
which the amplifier starts up. The second function is to
reduce noise produced by the power supply caused by
coupling into the output drive signal. This noise is from the
midrail generation circuit internal to the amplifier, which
appears as degraded PSRR and THD+N. Bypass capacitor,
CB, values of 0.47µF to 1µF ceramic or tantalum low-ESR
capacitors are recommended for the best THD and noise
performance.
DS6029 Ver 0.1 May. 2007
EUA6029
Preliminary
Table 2. Common Load Impedances vs Low Frequency
Output characteristics in SE Mode
CC
Lowest
RL
Frequency
3Ω
330µF
161Hz
4Ω
330µF
120Hz
8Ω
330µF
60Hz
32Ω
330µF
15Hz
10000Ω
330µF
0.05Hz
47000Ω
330µF
0.01Hz
As Table 2 indicates, most of the bass response is
attenuated into a 4-Ω load and 8-Ω load is adequate,
headphone response is good, and drive into line level
inputs (a home stereo for example) is exceptional.
Using Low- ESR Capacitors
Low- ESR capacitors are recommended throughout this
applications section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal
capacitor. The voltage drop across this resistor minimizes
the beneficial effects of the capacitor in the circuit. The
lower the equivalent value of this resistance the more the
real capacitor behaves like an ideal capacitor.
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EUA6029
Preliminary
Package Information
DIP-20
SYMBOLS
A
A1
b
b1
D
E
E1
e1
L
eB
DS6029 Ver 0.1 May. 2007
MILLIMETERS
MIN
MAX
5.33
0.38
0.36
0.56
1.14
1.78
26.16
7.62
6.35
2.54
2.92
3.81
8.51
9.53
INCHES
MIN
0.015
0.014
0.045
MAX
0.210
0.022
0.070
1.030
0.300
0.250
0.100
0.115
0.335
0.150
0.375
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