APA2030/2031 Stereo 2.6W Audio Amplifier(With Gain Control) Features General Description • Low operating current with 6mA APA2030/1 is a monolithic integrated circuit, which provides internal gain control, and a stereo bridged audio power amplifiers capable of producing 2.6W (1.9W) into 3Ω with less than 10% (1.0%) THD+N. By control the two gain setting pins, Gain0 and Gain1, The amplifier can provide 6dB, 10dB, 15.6dB, and 21.6dB gain settings. The advantage of internal gain setting can be less components and PCB area. Both • Improved depop circuitry to eliminate turn-on transients in outputs • High PSRR • Internal gain control, eliminate external components. • 2.6W per channel output power into 3Ω load at 5V, BTL mode • Multiple input modes allowable selected by HP of the depop circuitry and the thermal shutdown protection circuitry are integrated in APA2030/1, that reduces pops and clicks noise during power up or shutdown mode operation. It also improved the power off pop noise and protects the chip from being de- /LINE pin (APA2030) • Two output modes allowable with BTL and SE modes selected by SE/BTL pin (for APA2030 only) • Low current consumption in shutdown mode (50µ stroyed by over temperature and short current failure. A) • NoteBook PC To simplify the audio system design APA2030 combines a stereo bridge-tied loads (BTL) mode for speaker drive and a stereo single-end (SE) mode for headphone drive into a single chip, where both modes are easily switched by the SE/BTL input control pin signal. Besides the multiple input selections is used for portable audio system. APA2031 eliminates both input selection and single-end (SE) mode function to • LCD Monitor simplifying the design and save the PCB space. • Short Circuit Protection • TSSOP-24-P (APA2030) and TSSOP-20-P (APA2031) with thermal pad package. Applications Ordering and Marking Information P ackage C ode R : TS S O P-P * Tem p. R ange I : - 40 to 85 ° C H andling C ode TU : Tube TR : Tape & R eel TY : Tray Lead Free C ode L : Lead Free D evice B lank : O riginal D evice APA2030/1 Lead Free C ode H andling C ode Tem p. R ange P ackage C ode A P A 2030/1 R : A P A 2030/1 XXXXX XXXXX - D ate C ode ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 -Apr., 2004 1 www.anpec.com.tw APA2030/2031 Pin Assignment 24 GND GND 1 GA IN0 2 23 RLINEIN GA IN1 3 22 SHUTDOWN LOUT+ 4 LLINEIN 5 LHPIN 6 20 RHPIN T OP V ie w (A PA 2030) GA IN0 2 19 SHUTDOWN GA IN1 3 18 ROUT+ LOUT+ 4 19 V D D 17 HP/LINE PV D D 6 LOUT- 9 16 ROUT- RIN+ 7 LIN+ 10 15 SE/BTL RIN+ 8 GND 12 13 GND 16 V D D T OP V ie w (A PA 2031) 15 PV D D 14 ROUT13 GND LOUT- 8 LIN+ 9 14 PCBEEP BY PA SS 11 17 RIN- LIN- 5 18 PV D D PV D D 7 20 GND GND 1 21 ROUT+ 12 NC BY PA SS 10 11 GND A P A 2030_P inOut Block Diagram LLINEIN LHPIN LOUT+ MUX LIN+ BY PA SS Vb ias LOUTGA IN0 GIA N1 G ain select ab le RLINEIN RHPIN ROUT+ MUX RIN+ HP/LINE H P/L IN E SE/BTL SHUTDOW N PCBEEP Vb ias SE /B T L ROUT- Sh u t d o w n ckt PC - B EEP ckt A P A 2030_B lock APA2030 Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 2 www.anpec.com.tw APA2030/2031 Block Diagram LIN- LOUT+ LIN+ BY PA SS Vb ias SHUTDOWN Sh u td o w n ckt LOUT- GA IN0 GA IN1 G ain select ab le RIN- ROUT+ RIN+ Vb ias ROUTAPA2031_Block APA2031 Absolute Maximum Ratings (Over operating free-air temperature range unless otherwise noted.) Parameter Supply voltage range, VDD, PVDD Input voltage range at SE/BTL, HP/LINE, SHUTDOWN, Operating ambient temperature range, TA Maximum junction temperature, T J Storage temperature range, TSTG Soldering Temperature, 10 seconds, TS Electrostatic Discharge, VESD Power dissipation, PD Note: Rating -0.3V to 6V -0.3V to VDD -40°C to 85°C Internal Limited -65°C to 150°C 260°C -3000 to 3000*1 -200 to 200*2 Internal Limited *1. Human body model: C=100pF, R=1500Ω, 3 positives pulse plus 3 negative pulses *2. Machine model: C=200pF, L=0.5mH, 3 positive pulses plus 3 negative pulses Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 3 www.anpec.com.tw APA2030/2031 Recommended Operating Conditions Supply Voltage, VDD………………………………………………………………………….…………..4.5V to 5.5V Thermal Characteristics Symbol RTHJA Parameter Thermal Resistance from Junction to Ambient in Free Air TSSOP-P24* TSSOP-P20* Value Unit 45 48 °C/W * 5 in2 printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias. The thermal pad on the TSSOP_P package with solder on the printed circuit board. Electrical Characteristics (VDD=5V,-20°C<TA<85°C, unless otherwise noted.) Symbol Parameter VDD Supply Voltage IDD Supply current ISD Supply current in shutdown mode VIH High level threshold Voltage VIL Low level threshold Voltage II Input current Test Condition Min. Typ. 3.3 Max. Unit 5.5 V SE/BTL = 0V 6 12 mA SE/BTL = 5V 4 8 mA SHUTDOWN = 0V 50 300 µA SHUTDOWN, GAIN0, GAIN1 2 V SE/BTL, HP/LINE SHUTDOWN, GAIN0, GAIN1 4 V SE/BTL, HP/LINE SHUTDOWN, SE/BTL, HP/LINE, GAIN0, GAIN1 5 V 3 V nA VICM Common mode Input voltage VOS Output differential voltage 5 mV PC_beep trigger level 1 Vp.p Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 VDD-1.0 0.8 4 V www.anpec.com.tw APA2030/2031 Electical Characteristics (Cont.) Operating Characteristics, BTL mode Vdd=5V, TA=25°C, Rl=4Ω, Gain=6dB, (Unless otherwise noted) Symbol PO Parameter Maximum output power Test Condition PSRR xtalk S/N Total harmonic distortion plus noise Typ. Max. Unit THD=10%, Fin=1khz, RL=3Ω 2.6 W THD=10%, Fin=1khz, RL=4Ω 2.3 W THD=10%, Fin=1khz, RL=8Ω 1.5 W THD=1%, Fin=1khz, RL=3Ω 1.9 W THD=1%, Fin=1khz, RL=4Ω 1.7 W 1.1 W Po=1.1W, RL=4Ω Fin=1khz 0.05 % Po=0.7W, RL=8Ω, Fin=1khz 0.04 % THD=1%, Fin=1khz, RL=8Ω THD+N Min. 1 85 dB Channel separation Vin=0.2Vrms, Rl=8Ω, Cb=0.47µf, f=120Hz f=1khz, Cb=0.47µf, 95 dB HP/LINE input separation f=1khz, Cb=0.47µf, 80 dB Signal to noise ratio Po=1.1W, Rl=8Ω , A_weight 105 dB Power ripple rejection ratio Operating Characteristics, SE mode ( for APA2030 only) Vdd=5V, TA=25°C, Rl=32Ω, Gain=4, 1dB, (Unless otherwise noted) Symbol PO THD+N PSRR xtalk S/N Parameter Maximum output power Test Condition Typ. Max. Unit THD=10%, Fin=1khz, RL=32Ω 110 mW THD=1%, Fin=1khz, RL=32Ω 90 mW 0.03 % 55 dB 80 dB Total harmonic distortion plus Po=75mW, RL=32Ω .Fin=1khz noise Vin=0.2Vrms, Rl=32Ω, Power ripple rejection ratio Cb=0.47µf, f=120, SE/BTL attenuation Min. Channel separation f=1khz, Cb=0.47µf, 65 dB HP/LINE input separation f=1khz, Cb=0.47µf, BTL 80 dB Signal to noise ratio Po=75mW, Rl=32Ω, A_weight, 100 dB Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 5 www.anpec.com.tw APA2030/2031 Pin Descriptions APA2030 Pin Config. Function Description no. 1, 12, G ND G round connection, Connected to therm al pad. 13, 24 G AIN0 2 I/P Input signal for internal gain setting G AIN1 3 I/P Input signal for internal gain setting LOUT+ 4 O /P Left channel positive output in BTL m ode and SE m ode LLINEIN 5 I/P Left channel line input term inal, selected when HP/LINE is held low. RLINEIN 23 I/P Right channel line input term inal, selected when HP/LINE is held low. LHPIN 6 O /P Left channel headphone input term inal, selected when HP/LINE is held high. 7, PV DD Supply voltage only for power am plifier 18 RIN+ 8 I/P Right channel positive signal input, when differential signal is accepted. LOUT9 O /P Left channel negative output in BTL m ode and high im pedance in SE m ode LIN+ 10 I/P Left channel positive signal input, when differential signal is accepted. BYPASS 11 Bypass voltage PCBEEP 14 I/P PC-beep signal input O utput m ode control input pin, high for SE output m ode and low for BTL 15 I/P SE/BTL m ode Right channel negative output in BTL m ode and high im pedance in SE ROUT16 O /P m ode Multi-input selection input, headphone m ode when held high, line-in m ode HP/LINE 17 I/P when held low V DD 19 Supply voltage for internal circuit excepting power am plifier. Right channel headphone input term inal, selected when HP/LINE is held RHPIN 20 I/P high. ROUT+ 21 O /P Right channel positive output in BTL m ode and SE m ode 22 I/P SHUTDOW N It will be into shutdown m ode when pull low 23 I/P RLINEIN Right channel line input term inal, selected when HP/LINE is held low Pin name APA2031 Pin name GND GAIN0 GAIN1 LOUT+ LINPVDD RIN+ LOUTLIN+ BYPASS NC ROUTVDD Pin Config. Function Description no. 1, 11, Ground connection, Connected to thermal pad. 13, 20 2 I/P Input signal for internal gain setting 3 I/P Input signal for internal gain setting 4 O/P Left channel positive output 5 I/P Left channel negative audio signal input 6,15 Supply voltage only for power amplifier 7 I/P Right channel positive audio signal input 8 O/P Left channel negative output 9 I/P Left channel positive audio signal input 10 Bypass voltage 12 No connection 14 O/P Right channel negative output 16 Supply voltage for internal circuit excepting power amplifier Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 6 www.anpec.com.tw APA2030/2031 Pin Description APA2031 Pin name RIN+ ROUT+ Pin Config. Function Description no. 17 I/P Right channel negative audio signal input 18 O/P Right channel positive output SHUTDOWN 19 I/P It will be into shutdown mode when pull low Control Input Table ( for APA2030 only) SE/BTL X L L H H X HP/ LINE X L H L H X SHUTDOWN L H H H H X PCBEEP Operating mode Disable Disable Disable Disable Disable Enable Shutdown mode Line input, BTL out HP input, BTL out Line input, SE out HP input, SE out PCBEEP input, BTL out Gain Setting Table (for both APA2030 and APA2031) GAIN0 GAIN1 Ri Rf Av 0 0 90KΩ 90KΩ 6dB 0 1 69KΩ 111KΩ 10dB 1 0 42KΩ 138KΩ 15.6dB 1 1 25.7KΩ Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 154.3KΩ 21.6dB 7 www.anpec.com.tw APA2030/2031 Typical Application Circuit (f (for APA2030 using SE input signal) VDD 0.1µF VDD 0.47µF L-LINE L-HP 0.47µF 0.47µF 0.47µF LLINEIN LHPIN 0Ω 100µF GND PVDD LOUT+ MUX 220µF LIN+ 1kΩ BYPASS Vbias 4Ω GAIN0 GAIN1 0.47µF RLINEIN RHPIN R-LINE R-HP 0.47µF 0.47µF 100kΩ Shutdown Signal 100kΩ SE/BTL SHUTDOWN PCBEEP BEEP Signal LOUT- Sleeve Tip Headphone Jack ROUT+ MUX 220µF VDD SE/BTL Signal SE/BTL Signal Gain selectable RIN+ HP/LINE HP/LINE Control Signal Control Pin Ring 1kΩ HP/LINE Vbias 4Ω SE/BTL ROUT- Shutdown ckt PC-BEEP ckt 0.47µF APA2030AppCkt APA 2030 Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 8 www.anpec.com.tw APA2030/2031 Typical Application Circuit (for APA2031 using SE input signal) V DD 0Ω 0 .1 µ F V DD L -INP UT 0 .4 7 µ F 100 µ F G ND P V DD L IN- 0 .4 7µ F L O UT + L IN+ BYPASS Vbias 0 .4 7 µ F 4Ω G A IN0 G A IN1 R-INP UT 0 .4 7µ F 0 .4 7 µ F L O UT Gain se l e cta b l e RIN- RO UT + RIN+ Vbias 4Ω S h u td o wn S ig na l S HUT DO WN RO UT - S h u td o wn ckt APA 2031 Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 9 www.anpec.com.tw APA2030/2031 Typical Characteristics THD+N vs. Output Power THD+N vs. Output Power 10 10 VDD=5V AV=4.1dB f=1kHz COUT=330µF SE RL=8Ω 1 RL=3Ω RL=4Ω THD+N (%) THD+N (%) VDD=5V AV=6dB f=1kHz BTL 0.1 0.01 0 0.5 1 1.5 2.5 2 1 RL=32Ω 0.1 0.01 3 0 50 Output Power (W) 150 200 250 THD+N vs. Output Power 10 10 VDD=5V AV=6dB RL=3Ω BTL f=15kHz f=15kHz 1 1 THD+N (%) THD+N (%) 100 Output Power (mW) THD+N vs. Output Power f=1kHz 0.1 f=1kHz 0.1 f=30Hz 0.01 10m RL=16Ω 0.01 100m 1 5 10m Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 f=30Hz VDD=5V AV=15.6dB RL=3Ω BTL 100m 1 2 5 Output Power (W) 10 www.anpec.com.tw APA2030/2031 Typical Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 10 VDD=5V AV=6dB RL=4Ω BTL f=15kHz f=15kHz 1 THD+N (%) THD+N (%) 1 f=1kHz 0.1 f=1kHz 0.1 f=30Hz 0.0 1 10m 100m 1 2 0.01 10m 5 Output Power (W) 10 5 VDD=5V AV=15.6dB RL=8Ω BTL 1 THD+N (%) THD+N (%) 2 f=15kHz f=15kHz 0.1 1 THD+N vs. Frequency VDD=5V AV=6dB RL=8Ω BTL 1 100m Output Power (W) THD+N vs. Output Power 10 f=30Hz VDD=5V AV=15.6dB RL=4Ω BTL f=1kHz f=30Hz 0.1 f=1kHz f=30Hz 0.01 10m 100m 1 2 0.01 10m 5 1 2 5 Output Power (W) Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 100m 11 www.anpec.com.tw APA2030/2031 Typical Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 10 VDD=5V AV=4dB RL=16Ω COUT=1000µF SE f=30Hz 1 THD+N (%) 1 THD+N (%) VDD=5V AV=4.1dB RL=32Ω COUT=1000µF SE f=15kHz 0.1 f=15kHz 0.1 f=30Hz f=1kHz 0.01 10m 10 50m 100m f=1kHz 0.01 10m 200m 300m 100m 200m 300m Output Power (W) Output Power (W) THD+N vs. Frequency THD+N vs. Frequency 10 VDD=5V PO=1.75W RL=3Ω BTL VDD=5V AV=6dB RL=3Ω BTL 1 THD+N (%) 1 THD+N (%) 50m PO=1.75W 0.1 0.01 20 AV=15.6dB AV=6dB 0.1 PO=1W 100 1k 0.01 20 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 100 1k 10k 20k Frequency (Hz) 12 www.anpec.com.tw APA2030/2031 Typical Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Frequency 10 10 VDD=5V PO=1.5W RL=4Ω BTL VDD=5V AV=6dB RL=4Ω BTL 1 THD+N (%) THD+N (%) 1 PO=1.5W 0.1 AV=15.6dB 0.1 AV=6dB PO=0.75W 0.01 0.01 20 100 1k 10k 20 20k 100 Frequency (Hz) THD+N vs. Frequency 10 VDD=5V AV=6dB RL=8Ω BTL VDD=5V PO=1W RL=8Ω BTL THD+N (%) THD+N (%) 1 PO=1W 0.1 1 AV=6dB 0.1 PO=0.5W 0.01 20 10k 20k Frequency (Hz) THD+N vs. Frequency 10 1k 100 AV=15.6dB 1k 10k 0.01 20k 20 1k 10k 20k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 100 13 www.anpec.com.tw APA2030/2031 Typical Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Frequency 10 VDD=5V AV=4.1dB RL=16Ω COUT=1000µF SE 1 THD+N (%) 0.1 VDD=5V AV=4.1dB RL=32Ω COUT=1000µF SE 1 0.1 PO=75mW PO=25mW PO=150mW 0.01 20 100 PO=75mW 1k 10k 0.01 20 20k 100 Frequency (Hz) Gain +4 +240 +20 +230 +18 +260 +250 +16 +190 +180 Phase +170 -4 +160 VDD=5V RL=4Ω AV=6dB PO=1W BTL -6 -8 10 100 +150 Gain (dB) -0 10k +220 +210 +200 +10 +190 +180 +8 +130 +2 +120 100k 200k -0 +170 Phase V DD=5V RL=4Ω AV=15.6dB PO=1W BTL +4 Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 +230 +12 +6 +140 1k +240 Gain +14 Phase (Degress) Gain (dB) +200 -10 +270 +210 -2 20k Frequency Response +220 +2 10k Frequency (Hz) Frequency Response +6 1k 10 100 Phase (Degress) THD+N (%) 10 +160 +150 +140 +130 1k 10k +120 100k 200k Frequency (Hz) 14 www.anpec.com.tw APA2030/2031 Typical Characteristics (Cont.) Frequency Response Frequency Response +260 Gain +9 +8 +220 +210 +6 +200 +5 +190 +180 +4 Phase +170 +160 VDD=5V RL=8Ω AV=10dB PO=0.5W BTL +1 +240 +1 +220 +0 +200 +180 -1 Phase -3 +140 -4 +130 100 1k 10k 10 Crosstalk (dB) -40 100 +100 100k 200k 10k +0 6 VDD=5V RL=4Ω AV=6dB PO=1.5W SE -80 -10 -20 -30 Left to Right -100 VDD=5V RL=32Ω AV=4.1dB V IN =1V COUT=330µF SE -40 -50 -60 Left to Right -70 -80 -120 Right to Left 20 1k Crosstalk vs. Frequency -60 -140 +120 Frequency (Hz) Crosstalk (dB) -20 +140 -5 +120 100k 200k Crosstalk vs. Frequency 6 +160 VDD=5V RL=32Ω AV=4.1dB V IN =1V SE Frequency (Hz) +0 +260 +2 -2 +150 -0 10 Gain (dB) Gain (dB) +7 Phase (Degress) +230 +2 Gain +3 +240 +3 +280 +4 +250 Phase (Degress) +270 +10 +300 +5 100 1k -100 20 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 Right to Left -90 100 1k 10k 20k Frequency (Hz) 15 www.anpec.com.tw APA2030/2031 Typical Characteristics (Cont.) PSRR vs. Frequency PSRR vs. Frequency +0 +0 -20 -30 -30 -40 -40 -50 -60 -70 -50 -60 -70 -80 -80 -90 -90 -100 20 100 VDD=5V RL=32Ω CB=0.47µF SE -10 PSRR (dB) PSRR (dB) VDD=5V -10 RL=4Ω CB=0.47µF -20 BTL 1k -100 20 10k 20k 100 100 100 50 50 Filter BW < 22kHz 20 10 A-Weight 5 VDD=5V RL=4Ω 2 AV=6dB BTL 100 1k 10k Filter BW < 22kHz 20 A-Weight 10 5 VDD=5V RL=32Ω AV=4.1dB SE 2 1 20k 20 100 1k 10k 20k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 10k 20k Output Noise Voltage vs. Frequency Output Noise Voltage (µV) Output Noise Voltage (µV) Output Noise Voltage vs. Frequency 1 20 1k Frequency (Hz) Frequency (Hz) 16 www.anpec.com.tw APA2030/2031 Typical Characteristics (Cont.) Power Dissipation vs. Output Power Supply Current vs. Supply Voltage 2.0 7 No Load 1.8 BTL 6 VDD=5V BTL RL=3Ω Power Dissipation (W) Supply Current (mA) 1.6 5 4 SE 3 2 1 1.4 1.2 RL=4Ω 1.0 0.8 0.6 RL=8Ω 0.4 0.2 0.0 0 3.0 3.5 4.0 4.5 5.0 5.5 0.0 6.0 Supply Voltage (V) 0.5 1.0 1.5 2.0 2.5 Output Power (W) Power Dissipation vs. Output Power 200 VDD =5V SE Power Dissipation (mW) 180 160 RL=8Ω 140 120 100 80 RL=16Ω 60 40 RL=32Ω 20 0 0 50 100 150 200 250 300 Output Power (mW) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 17 www.anpec.com.tw APA2030/2031 Application Descriptions BTL Operation Single-Ended Operation (for APA2030 only) The APA2030/1 has two pairs of operational amplifiers internally, allowed for different amplifier configurations. Consider the single-supply SE configuration shown Application Circuit. A coupling capacitor is required to block the DC offset voltage from reaching the load. These capacitors can be quite large (approximately 33µF to 1000µF) so they tend to be expensive, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system (refer to the Output Coupling Capacitor). IN PU T- - IN PU T+ + OUT+ OP1 V bias The rules described should be following relationship: 1 Cbypass ×125k Ω - DIF F _AM P _CONF IG OUTOP2 Output SE/BTL Operation (for APA2030 only) The ability of the APA2030 to easily switch between BTL and SE modes is one of its most important costs saving features. This feature eliminates the requirement for an additional headphone amplifier in applications where internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated. + Figure 1: APA2030 internal configuration (each channel) The OP1 and OP2 are all differential drive configuration, The differential drive configuration doubling the voltage swing on the load compare to the single-ending configuration, the differential gain for each channel is 2X(Gain of SE mode). Internal to the APA2030, two separate amplifiers drive OUT+ and OUT- (see Figure 1). The SE/BTL input controls the operation of the follower amplifier that drives LOUT- and ROUT-. By driving the load differentially through outputs OUT+ and OUT-, an amplifier configuration commonly referred to as bridged mode is established. BTL mode operation is different from the classical single-ended SE amplifier configuration where one side of its load is connected to ground. • • A BTL amplifier design has a few distinct advantages over the SE configuration, as it provides differential drive to the load, thus doubling the output swing for a specified supply voltage. Four times the output power is possible as compared to a SE amplifier under the same conditions. A BTL configuration, such as the one used in APA2030/1, also creates a second advantage over SE amplifiers. Since the differential outputs, ROUT+, ROUT-, LOUT+, and LOUT-, are biased at half-supply, no need DC voltage exists across the load. This eliminates the need for an output coupling capacitor which is required in a single supply, SE configuration. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 ≤ R1iCi << R 1C L C When SE/BTL is held low, the OP2 is actived and the APA2030 is in the BTL mode. When SE/BTL is held high, the OP2 is in a high output impedance state, which configures the APA2030 as SE driver from OUT+. IDD is reduced by approximately one-half in SE mode. Control of the SE/BTL input can be a logic-level TTL source or a resistor divider network or the stereo headphone jack with switch pin as shown in Application Circuit. 18 www.anpec.com.tw (1) APA2030/2031 Application Descriptions Vdd SE/BTL 100K Ω Control Pin 1K Ω the HP/LINE pin, enabling the headphone input function. Ring 100K Ω Differential Input Operation SE/BTL_Switc h Tip APA2030/1 can accepted the differential input signal, and it’s can improve the CMRR (Common Mode Rejection ratio). For example: when apply differential input signals to APA2031, connect positive input signals to the IN+ (LIN+ and RIN+) of APA2031 and negative input signals to the IN- (LIN- and RIN-) of APA2031. When input signals are single-end, just connect IN+ (LIN+ and RIN+) to ground via a capacitor. Sleeve Headphone Jack Figure 2: SE/BTL input selection by phonejack plug In Figure 2, input SE/BTL operates as follows: When the phonejack plug is inserted, the 1kΩ resistor is disconnected and the SE/BTL input is pulled high and enables the SE mode. When the input goes high level, the OUT- amplifier is shutdown causing the speaker to mute. The OUT+ amplifier then drives through the output capacitor (CO) into the headphone jack. Input Resistance, Ri The APA2030/1 provides four gain setting decided by GAIN0 and GAIN1 input ins in Differential mode and it become 4.1dB fixed gain when SE mode is selected (for APA2030). In table 1,internal resistors Ri and Rf according to BTL operation set the gain for each audio input of the APA2030/1. When there is no headphone plugged into the system, the contact pin of the headphone jack is connected from the signal pin, the voltage divider set up by resistors 100kΩ and 1kΩ. Resistor 1kΩ then pulls low the SE/BTL pin, enabling the BTL function. Input HP/LINE Operation (for APA2030 only) APA2030 amplifier has two separate inputs for each of the left and right stereo channels. An internal multiplexer selects which input will be connected to the amplifier based on the state of the HP/LINE pin on the IC. • • To select the line inputs, set HP/LINE pin tied to low level To enable the headphone inputs, set HP/ LINE pin tied to high level GAIN1 Ri Rf SE/BTL Av 0 0 90KΩ 90KΩ 0 6dB 0 1 69KΩ 111KΩ 0 10dB 1 0 42KΩ 138KΩ 0 15.6dB 1 1 0 21.6dB X X 1 4.1dB 25.7KΩ 154.3KΩ 69KΩ 111KΩ Table 1: The close loop gain setting resistance Ri/Rf BTL mode operation brings about the factor 2 in the gain equation due to the inverting amplifier mirroring the voltage swing across the load. The input resistance has wide variation (+/-10%) caused by manufacture. Refer to the application circuit, the voltage divider of 100kΩ and 1kΩ sets the voltage at the HP/LINE pin to be approximately 50mV when there are no headphones plugged into the system. This logic low voltage at the HP/LINE pin enables the APA2030 and places it LINE input mode operation. When a set of headphones is plugged into the system, the contact pin of the headphone jack is disconnected from the signal pin, interrupting the voltage divider set up by resistors 100kΩ. Resistor 100kΩ then pulls-up Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 GAIN0 Input Capacitor, Ci In the typical application an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri form a high-pass filter with the corner frequency determined in the follow equation: 19 www.anpec.com.tw APA2030/2031 Application Descriptions fC (highpass)= 1 2πRimin× Ci To avoid start-up pop noise occurred, the bypass voltage should be rise slower then the input bias voltage and the relationship shown in equation should be maintained. (2) The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the example where Ri is 90kΩ when 6dB gain is setting and the specification calls for a flat bass response down to 40Hz . Equation is reconfigured as follow: Ci= 1 2πRifc 1 Cbypass × 125kȍ << 1 Ci × 180k ȍ The capacitor is fed from a 125kΩ source inside the amplifier. Bypass capacitor, Cb, values of 3.3µF to 10µF ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance. (3) Consider to input resistance variation, the Ci is 0.04µF so one would likely choose a value in the range of 0.1µF to 1.0µF. The bypass capacitance also effect to the start up time. It is determined in the follow equation: Tstart up =5x(Cbypassx125kΩ) A further consideration for this capacitor is the leakage path from the input source through the input network (Ri+Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level there is held at VDD/2, which is likely higher that the source DC level. Please note that it is important to confirm the capacitor polarity in the application. (5) Output Coupling Capacitor, Cc (for APA2030 only) In the typical single-supply SE configuration, an output coupling capacitor (Cc) is required to block the DC bias at the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by equation. fc(highpass)= Effective Bypass Capacitor, Cbypass As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. 1 2 πRLCC (6) For example, a 330µF capacitor with an 8Ω speaker would attenuate low frequencies below 60.6Hz. The main disadvantage, from a performance standpoint, is the load impedance is typically small, which drives the low-frequency corner higher degrading the bass response. Large values of CC are required to pass low frequencies into the load. The capacitor location on both the bypass and power supply pins should be as close to the device as possible. The effect of a larger half supply bypass capacitor is improved PSRR due to increased halfsupply stability. Typical applications employ a 5V regulator with 1.0µF and a 0.1µF bypass capacitors which aid in supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA2030/1. The selection of bypass capacitors, especially Cb, is thus dependent upon desired PSRR requirements, click and pop performance. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 (4) Power Supply Decoupling, Cs The APA2030/1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. 20 www.anpec.com.tw APA2030/2031 Application Descriptions Power supply decoupling also prevents the oscillations causing by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different type capacitors that target on different type of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance(ESR) ceramic capacitor, typically 0.1µF placed as close as possible to the device VDD lead works best. For filtering lowerfrequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater placed near the audio power amplifier is recommended. Optimizing Depop Circuitry Circuitry has been included in the APA2030/1 to minimize the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops. (Refer to Effective Bypass Capacitance) The bypass voltage rise up should be slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of Cb can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of Cb, turn-on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship between the size of Cb and the turn-on time. Shutdown Function In order to reduce power consumption while not in use, the APA2030/1 contains a shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the SHUTDOWN pin. The trigger point between a logic high and logic low level is typically 2.0V. It is best to switch between ground and the supply VDD to provide maximum device performance. In a SE(for APA2030) configuration, the output coupling capacitor, CC, is of particular concern. This capacitor discharges through the internal 10kΩ resistors. Depending on the size of CC, the time constant can be relatively large. To reduce transients in SE mode, an external 1kΩ resistor can be placed in parallel with the internal 10kΩ resistor. The tradeoff for using this resistor is an increase in quiescent current. By switching the SHUTDOWN pin to low, the amplifier enters a low-current state, IDD<50µA. APA2030 is in shutdown mode, except PC-BEEP detect circuit. On normal operating, SHUTDOWN pin pull to high level to keeping the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a definite voltage to avoid unwanted state changes. In the most cases, choosing a small value of Ci in the range of 0.33µF to 1µF, Cb being equal to 0.47µF and an external 1kΩ resistor should be placed in parallel with the internal 10kΩ resistor should produce a virtually clickless and popless turn-on. PC-BEEP Detection ( for APA2030 only) APA2030 integrates a PCBEEP detect circuit for NOTEBOOK PC used. When PC-BEEP signal drive to PCBEEP input pin, and PCBEEP mode is active. APA2030 will force to BTL mode and the internal gain fixed as -10dB. The PCBEEP signal becomes the amplifier input signal and play on the speaker without coupling capacitor. If the amplifier in the shutdown mode, it will out of shutdown mode whenever PCBEEP mode enable. The APA2030 will return to previous setting when it is out of PC-BEEP mode. A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. So it is advantageous to use low-gain configurations. BTL Amplifier Efficiency An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. The following equations are the basis for calculating amplifier efficiency. The input impedance is 100kΩ on PCBEEP input pin. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 21 www.anpec.com.tw APA2030/2031 Application Descriptions Efficiency = PO A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage whenpossible. Note that in equation, VDD is in the dominator. This indicates that as VDD goes down,efficiency goes up. In other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. (7) PSUP Where: PO = VOrms× VOrms VOrms = RL VP = VP × VP 2RL (8) 2 Power Dissipation Psup = VDD * IDDAVG = 2VP Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. In equation11 states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving a specified load. πRL Efficiency of a BTL configuration: PO PSUP =( VP × VP 2RL ) / (VDD x 2VP πRL )= πVP 2 (10) 4VDD SE mode : PD,MAX = Table 2 calculates efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1W audio system with 8Ω loads and a 5V supply, the maximum draw on the power supply is almost 3W. Po (W) Efficiency (%) IDD(A) VPP(V) PD (W) 0.25 31.25 0.16 2.00 0.55 0.50 47.62 0.21 2.83 0.55 1.00 66.67 0.30 4.00 0.5 1.25 78.13 0.32 4.47 0.35 2π 2RL (11) In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus the maximum power dissipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. 2 4V DD BTL mode : PD,MAX = 2ʌ2 RL (12) Since the APA2030/1 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both of equations depending on the mode of operation. Even with this substantial increase in power dissipation, the APA2030/1 does not require extra heatsink. The power dissipation from equation12, assuming a 5V-power supply and an 8Ω load, must not be greater than the power dissipation that results from the equation13: PD,MAX = TJ.MAX − TA θJA (13) For TSSOP-24 (APA2030) and TSSOP-20 (APA2031) package with and without thermal pad, the thermal resistance (θJA ) is equal to 45 oC/W and 48oC/W, respectively. **High peak voltages cause the THD to increase. Since the maximum junction temperature (TJ,MAX) of APA2030/1 is 150oC and the ambient temperature (TA) is defined by the power system design, the maximum Table 2. Efficiency Vs Output Power in 5V/8Ω BTL Systems Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 VDD 22 www.anpec.com.tw APA2030/2031 Application Descriptions To calculate maximum ambient temperatures, first consideration is that the numbers from the Power Dissipation vs. Output Power graphs (page17) are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given θJA, the maximum allowable junction temperature (TJ, ), and the total internal dissipation (PD), the maxiMAX mum ambient temperature can be calculated with the following equation. The maximum recommended junction temperature for the APA2030/1 is 150°C. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graphs. (Page17) power dissipation which the IC package is able to handle can be obtained from equation13. Once the power dissipation is greater than the maximum limit (P D,MAX ), either the supply voltage (V DD ) must bedecreased, the load impedance (RL) must be increased or the ambient temperature should be reduced. Thermal Pad Considerations The thermal pad must be connected to ground. The package with thermal pad of the APA2030/1 requires special attention on thermal design. If the thermal design issues are not properly addressed, the APA2030/1 4Ω will go into thermal shutdown when driving a 4Ω load. TA,Max = TJ,Max -θϑAPD (14) 150 - 45(0.8*2) = 78°C (TSSOP-P24) The thermal pad on the bottom of the APA2030/1 should be soldered down to a copper pad on the circuit board. Heat can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on the top surface of the circuit board, 8 to 10 vias of 13 mil or smaller in diameter should be used to thermally couple the thermal pad to the bottom plane. For good thermal conduction, the vias must be plated through and solder filled. The copper plane used to conduct heat away from the thermal pad should be as large as practical. 150 - 48(0.8*2) = 73.2°C (TSSOP-P20) The APA2030/1 is designed with a thermal shutdown protection that turns the device off when the junction temperature surpasses 150°C to prevent damaging the IC. If the ambient temperature is higher than 25°C, a larger copper plane or forced-air cooling will be required to keep the APA2030/1 junction temperature below the thermal shutdown temperature (150°C). In higher ambient temperature, higher airflow rate and/ or larger copper area will be required to keep the IC out of thermal shutdown. Thermal Considerations Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 23 www.anpec.com.tw APA2030/2031 Packaging Information T S S O P / T S S O P -P ( R eference JE D E C R egistration M O -153) e N 2x E/2 E1 1 2 3 E e/2 D A2 A ( A1 b D1 2) GAUGE PLANE S EXPOSED THERMAL PAD =ONE E2 0.25 L 1 (L1) ( 3) BOTTOM VIEW (THERMALLY ENHANCED VARIATIONDS ONLY) D im A A1 A2 D D1 e E E1 E2 L L1 R R1 S φ1 φ2 φ3 M illim eters Inches M in. M ax. 1.2 0.00 0.15 0.80 1.05 6.4 (N =20P IN ) 6.6 (N =20P IN ) 7.7 (N =24P IN ) 7.9 (N =24P IN ) 9.6 (N =28P IN ) 9.8 (N =28P IN ) 4.2 B S C (N =20P IN ) 4.7 B S C (N =24P IN ) 3.8 B S C (N =28P IN ) 0.65 B S C 6.40 B S C 4.30 4.50 3.0 B S C (N =20P IN ) 3.2 B S C (N =24P IN ) 2.8 B S C (N =28P IN ) 0.45 0.75 1.0 R E F 0.09 0.09 0.2 0° 8° 12° R E F 12° R E F Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 24 M in. M ax. 0.047 0.000 0.006 0.031 0.041 0.252 (N =20P IN ) 0.260 (N =20P IN ) 0.303 (N =24P IN ) 0.311 (N =24P IN ) 0.378 (N =28P IN ) 0.386 (N =28P IN ) 0.165 B S C (N =20P IN ) 0.188 B S C (N =24P IN ) 0.150 B S C (N =28P IN ) 0.026 B S C 0.252 B S C 0.169 0.177 0.118 B S C (N =20P IN ) 0.127 B S C (N =24P IN ) 0.110 B S C (N =28P IN ) 0.018 0.030 0.039R E F 0.004 0.00 4 0.008 0° 8° 12° R E F 12° R E F www.anpec.com.tw APA2030/2031 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical =one T L to T P Temperature Ram p-up TL tL Tsm ax Tsm in Ram p-down ts Preheat 25 t 25 °C to Peak Tim e Classificatin Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Large Body Small Body Average ramp-up rate 3°C/second max. (TL to TP) Preheat Temperature Min (Tsmin) 100°C Temperature Mix (Tsmax) 150°C Time (min to max)(ts) 60-120 seconds Tsmax to TL - Ramp-up Rate Tsmax to TL Temperature(TL) 183°C Time (tL) 60-150 seconds Peak Temperature(Tp) 225 +0/-5°C 240 +0/-5°C Time within 5°C of actual Peak 10-30 seconds 10-30 seconds Temperature(tp) Ramp-down Rate 6°C/second max. 6 minutes max. Time 25°C to Peak Temperature Pb-Free Assembly Large Body Small Body 3°C/second max. 150°C 200°C 60-180 seconds 3°C/second max 217°C 60-150 seconds 245 +0/-5°C 250 +0/-5°C 10-30 seconds 20-40 seconds 6°C/second max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 25 www.anpec.com.tw APA2030/2031 Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 SEC 1000 Hrs Bias #125°C 168 Hrs, 100%RH, 121°C -65°Ca150°C, 200 Cycles VHBM ! 2KV, VMM ! 200V 10ms, 1tr ! 100mA Carrier Tape & Reel Dimensions t D P Po E P1 W Bo F Ao D1 Ko T2 J C A B T1 Application TSSOP- 24 A B C J T1 T2 W P E 330 ±1 100 ref 13 ±0.5 2 ±0.5 16.4 ±0.2 2 ±0.2 16 ±0.3 12 ±0.1 1.75±0.1 F D D1 Po P1 Ao Bo Ko t 7.5 ±0.1 1.5 +0.1 1.5 min 4.0 ±0.1 2.0 ±0.1 6.9 ±0.1 8.3 ±0.1 1.5 ±0.1 0.3±0.05 (mm) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 26 www.anpec.com.tw APA2030/2031 Cover Tape Dimensions Application TSSOP- 24 Carrier Width 16 Cover Tape Width 21.3 Devices Per Reel 2000 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 27 www.anpec.com.tw