OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 1 OMAP3515/03 Applications Processor • • • OMAP3515/03 Applications Processor: – OMAP™ 3 Architecture – MPU Subsystem • 600-MHz ARM Cortex™-A8 Core • NEON™ SIMD Coprocessor – 2D/3D Graphics Accelerator (OMAP3515 Device Only) • Tile Based Architecture Delivering up to 10 MPoly/sec • Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality • Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0 and Direct3D Mobile • Fine Grained Task Switching, Load Balancing, and Power Management • Programmable High Quality Image Anti-Aliasing – Fully Software-Compatible With ARM9™ – Commercial and Extended Temperature Grades ARM Cortex™-A8 Core – ARMv7 Architecture • Trust Zone® • Thumb®-2 • MMU Enhancements – In-Order, Dual-Issue, Superscalar Microprocessor Core – NEON™ Multimedia Architecture – Over 2x Performance of ARMv6 SIMD – Supports Both Integer and Floating Point SIMD – Jazelle® RCT Execution Environment Architecture – Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack – Embedded Trace Macrocell (ETM) Support for Non-Invasive Debug ARM Cortex™-A8 Memory Architecture: – 16K-Byte Instruction Cache (4-Way Set-Associative) – 16K-Byte Data Cache (4-Way Set-Associative) – 256K-Byte L2 Cache • • • • • • 112K-Byte ROM 64K-Byte Shared SRAM Endianess: – ARM Instructions - Little Endian – ARM Data – Configurable External Memory Interfaces: – SDRAM Controller (SDRC) • 16, 32-bit Memory Controller With 1G-Byte Total Address Space • Interfaces to Low-Power Double Data Rate (LPDDR) SDRAM • SDRAM Memory Scheduler (SMS) and Rotation Engine – General Purpose Memory Controller (GPMC) • 16-bit Wide Multiplexed Address/Data Bus • Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin • Glueless Interface to NOR Flash, NAND Flash (With ECC Hamming Code Calculation), SRAM and Pseudo-SRAM • Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, etc.) • Nonmultiplexed Address/Data Mode (Limited 2K-Byte Address Space) System Direct Memory Access (sDMA) Controller (32 Logical Channels With Configurable Priority) Camera Image Signal Processing (ISP) – CCD and CMOS Imager Interface – Memory Data Input – RAW Data Interface – BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface – A-Law Compression and Decompression – Preview Engine for Real-Time Image Processing – Glueless Interface to Common Video Decoders – Histogram Module/Auto-Exposure, Auto-White Balance, and Auto-Focus Engine – Resize Engine Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. is a trademark of ~ Texas Instruments. All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2008–2008, Texas Instruments Incorporated PRODUCT PREVIEW 1.1 Features OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 • PRODUCT PREVIEW • • 2 • Resize Images From 1/4x to 4x • Separate Horizontal/Vertical Control Display Subsystem – Parallel Digital Output • Up to 24-Bit RGB • HD Maximum Resolution • Supports Up to 2 LCD Panels • Support for Remote Frame Buffer Interface (RFBI) LCD Panels – 2 10-Bit Digital-to-Analog Converters (DACs) Supporting: • Composite NTSC/PAL Video • Luma/Chroma Separate Video (S-Video) – Rotation 90-, 180-, and 270-degrees – Resize Images From 1/4x to 8x – Color Space Converter – 8-bit Alpha Blending Serial Communication – 5 Multichannel Buffered Serial Ports (McBSPs) • 512 Byte Transmit/Receive Buffer (McBSP1/3/4/5) • 5K-Byte Transmit/Receive Buffer (McBSP2) • SIDETONE Core Support (McBSP2 and 3 Only) For Filter, Gain, and Mix Operations • Direct Interface to I2S and PCM Device and TDM Buses • 128 Channel Transmit/Receive Mode – Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports – High-Speed/Full-Speed/Low-Speed USB OTG Subsystem (12-/8-Pin ULPI Interface) – High-Speed/Full-Speed/Low-Speed Multiport USB Host Subsystem • 12-/8-Pin ULPI Interface or 6-/4-/3-Pin Serial Interface • Supports Transceiverless Link Logic (TLL) – One HDQ/1-Wire Interface – Three UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes) – Three Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers Removable Media Interfaces: – Three Multimedia Card (MMC)/ Secure OMAP3515/03 Applications Processor www.ti.com • • • • • • • • • • • • Digital (SD) With Secure Data I/O (SDIO) Comprehensive Power, Reset, and Clock Management – SmartReflex™ Technology – Dynamic Voltage and Frequency Scaling (DVFS) Test Interfaces – IEEE-1149.1 (JTAG) Boundary-Scan Compatible – Embedded Trace Macro Interface (ETM) – Serial Data Transport Interface (SDTI) 12 32-bit General Purpose Timers 2 32-bit Watchdog Timers 1 32-bit 32-kHz Sync Timer Up to 188 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) 65-nm CMOS Technology Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package) Discrete Memory Interface (Not Available in CBC Package) Packages: – 515-pin PBGA package (CBB Suffix), .5mm Ball Pitch (Top), .4mm Ball Pitch (Bottom) – 515-pin S-PBGA package (CBC Suffix), .65mm Ball Pitch (Top), .5mm Ball Pitch (Bottom) – 423-pin PBGA package (CUS Suffix), .65mm Ball Pitch 1.8-V I/O and 3.0-V (MMC1 only), 0.8-V to 1.35-V Adaptive Processor Core Voltage, 0.8-V to 1.15-V Adaptive Core Logic Voltage Applications: – Portable Navigation Devices – Portable Media Player – Advanced Portable Consumer Electronics – Digital TV – Digital Video Camera – Portable Data Collection – Point-of-Sale Devices – Gaming – Web Tablet – Smart White Goods – Smart Home Controllers – Ultra Mobile Devices Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 1.2 Description OMAP3515 and OMAP3503 high-performance, applications processors are based on the enhanced OMAP™ 3 architecture. The device supports high-level operating systems (OSs), such as: • Windows CE • Symbian OS • Linux • Palm OS This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products. The following subsystems are part of the device: • Microprocessor unit (MPU) subsystem based on the ARM Cortex™-A8 microprocessor • SGX subsystem for 2D and 3D graphics acceleration to support display and gaming effects (3515only) • Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors • Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC/PAL video out. • Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals The device also offers: • A comprehensive power and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex™ adaptative voltage control. This power management technique for automatic control of the operating voltage of a module reduces the active power consumption. • Memory stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only) OMAP15/03 devices are available in a 515-pin PBGA package (CBB suffix), 515-pin S-PBGA package (CBC suffix), and a 423-pin PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. Table 1-1 lists the differences between the CBB, CBC, and CUS packages. Submit Documentation Feedback OMAP3515/03 Applications Processor 3 PRODUCT PREVIEW The OMAP™ 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following: • Streaming video • 2D/3D mobile gaming • Video conferencing • High-resolution still image • Video capture in 2.5G wireless terminals, 3G wireless terminals, and rich multimedia-featured handsets, and high-performance personal digital assistants (PDAs). OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 1-1. Differences Between CBB, CBC, and CUS Packages FEATURE CBB PACKAGE CBC PACKAGE For CBC package pin assignments see Table 2-2, Ball Characteristics (CBC Pkg.) For CUS package pin assignments see Table 2-3, Ball Characteristics (CUS Pkg.) POP interface supported POP interface supported POP interface not available Discrete Memory Interface supported Discrete Memory Interface not supported Discrete Memory Interface supported Eight chip select pins available Eight chip select pins available Chip select pins gpmc_ncs1 and gpmc_ncs2 are not available Four wait pins available Four wait pins available Wait pins gpmc_wait1 and gpmc_wait2 are not available UART1 CTS signal is available on 3 pins (triple muxed): uart2_cts (AG22 / W8 / T21), uart2_rts (AH22 / AA9), uart2_tx (F28 / Y8 / AE7), uart2_rx (E26 / AA8) The following signals are available on one pin only: uart2_cts (AE21 / T19), uart2_rts (AE22 / R2), uart2_tx (H3 / H25 / AE4), uart2_rx (L4 / G26) CTS signal is available on 3 pins (triple muxed): uart2_cts (AC19 / AC2 / AA18), uart2_rts (W6 / AB19), uart2_tx (E23 / V7 / AC3), uart2_rx (D24 / W7) UART2 The following signals are available on two pins (double muxed): uart2_cts (AF6/AB26), uart2_rts (AE6/AB25), uart2_tx (AF5/AA25), uart2_rx (AE5/AD25) The following signals are available on one pin only: uart2_cts (Y24), uart2_rts (AA24), uart2_tx (AD22), uart2_rx (AD21) The following signals are available on one pin only: uart2_cts (V6), uart2_rts (V5), uart2_tx (W4), uart2_rx (V4) McBSP3 The following signals are available on three pins (triple muxed): mcbsp3_dx (AF6 / AB26 / V21), mcbsp3_dr (AE6 / AB25 / U21), mcbsp3_clkx (AF5 / AA25 / W21), and mcbsp3_fsx (AE5 / AD25 / K26) The following signals are available on two pins (double muxed): mcbsp3_dx (U17/ Y24), mcbsp3_dr (T20/ AA24), mcbsp3_clkx (T17/ AD22), mcbsp3_fsx (P20/ AD21) The following signals are available on two pins only (double muxed): mcbsp3_dx (TBD), mcbsp3_dr (TBD), mcbsp3_clkx (TBD), and mcbsp3_fsx (TBD) GP Timer The following signals are available on three pins (triple muxed): gpt8_pwm_evt (N8 / AD25 / V3), gpt9_pwm_evt (T8 / AB26 / Y2), gpt10_pwm_evt (R8 / AB25 / Y3), and gpt11_pwm_evt (P8 / AA25 / Y4) The following signals are available on three pins (triple muxed): gpt8_pwm_evt (C5/AD21/V9), gpt9_pwm_evt (B4/W8/Y24), gpt10_pwm_evt(C4/U8/AA24), gpt11_pwm_evt(B5/V8/AD22) The following signals are available on two pins only (double muxed): gpt8_pwm_evt (TBD), gpt9_pwm_evt (TBD), gpt10_pwm_evt (TBD), and gpt11_pwm_evt (TBD) McBSP4 The following signals are available on two pins (double muxed): mcbsp4_clkx (T8/AE1), mcbsp4_dr (R8/AD1), mcbsp4_dx (P8/AD2), mcbsp4_fsx (N8/AC1) The following signals are available on one pin only: mcbsp4_clkx (B4), mcbsp4_dr (C4), mcbsp4_dx (B5), mcbsp4_fsx (C5) The following signals are available on one pin only: mcbsp4_clkx (TBD), mcbsp4_dr (TBD), mcbsp4_dx (TBD), mcbsp4_fsx (TBD) HSUSB3_TLL Supported Supported Not supported MM_FSUSB3 Supported Supported Not supported McSPI1 Four chip select pins are available Four chip select pins are available Chip select pins mcspi1_cs1 and mcspi_cs2 are not available MMC3 The following signals are available on two pins (double muxed): mmc3_cmd (AC3 / AE10), and mmc3_clk (AB1 / AF10) The following signals are available on two pins (double muxed): mmc3_cmd (R8 / AB3), mmc3_clk (R9 / AB2) The following signals are available on one pin only: mmc3_cmd (TBD), and mmc3_clk (TBD) Pin Assignments Package-On-Package (POP) Interface Discrete Memory Interface GPMC PRODUCT PREVIEW 4 CUS PACKAGE For CBB package pin assignments seeTable 2-1, Ball Characteristics (CBB Pkg.) OMAP3515/03 Applications Processor Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 1-1. Differences Between CBB, CBC, and CUS Packages (continued) FEATURE CBB PACKAGE CBC PACKAGE CUS PACKAGE A maximum of 170 GPIO pins are supported. TBD Pin muxing restricts the total number of GPIO pins available at one time. For more details, see Table 2-6, Multiplexing Characteristics (CUS Pkg.). This OMAP3515/03 Applications Processor data manual presents the electrical and mechanical specifications for the OMAP3515/03 Applications Processor. The information contained in this data manual applies to both the commercial and extended temperature versions of the OMAP3515/03 Applications Processor unless otherwise indicated. It consists of the following sections: • A description of the OMAP3515/03 terminals: assignment, electrical characteristics, multiplexing, and functional description (Section 2) • A presentation of the electrical characteristics requirements: power domains, operating conditions, power consumption, and dc characteristics (Section 3) • The clock specifications: input and output clocks, DPLL and DLL (Section 4) • The video DAC specification (Section 5) • The timing requirements and switching characteristics (ac timings) of the interfaces (Section 6) • A description of thermal characteristics, device nomenclature, and mechanical data about the available packaging (Section 7) 1.3 Functional Block Diagram Figure 1-1 shows the functional block diagram of the OMAP3515/03 Applications Processor. Submit Documentation Feedback OMAP3515/03 Applications Processor 5 PRODUCT PREVIEW A maximum of 188 GPIO pins are supported. GPIO The following GPIO pins are not available: gpio_112, gpio_113, gpio_114, gpio_115, gpio_52, gpio_53, gpio_63, gpio_64, gpio_144, gpio_145, gpio_146, gpio_147, gpio_152, gpio_153, gpio_154, gpio_155, gpio_175, and gpio_176. OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com OMAP Applications Processor LCD Panel MPU Subsystem Amp Parallel ARM CortexA8TM Core 16K/16K L1$ 2D/3D Graphics Accelerator (3515 Only) L2$ 256K 64 64 DualCamera (serial and Parallel) CVBS or S-Video 32 32 32 Channel System DMA 32 32 TV Camera ISP Image Capture Hardware Image Pipeline and Preview Dual Output 3-Layer Display Processor (1xGraphics, 2xVideo) Temporal Dithering SDTV®QCIF Support 32 64 HS USB Host (with USB TTL) HS USB OTG 32 PRODUCT PREVIEW Async 64 64 L3 Interconnect Network-Hierarchial, Performance, and Power Driven 32 32 64K On-Chip RAM 2KB Public/ 62KB Secure 112K On-Chip ROM 80KB Secure/ 32KB BOOT 64 SMS: SDRAM Memory Scheduler/ Rotation SDRC: SDRAM Memory Controller 32 32 32 L4 Interconnect GPMC: General Purpose Memory Controller NAND/ NOR Flash, SRAM External and Stacked Memories Peripherals: 3xUART, 3xHigh-Speed I2C, 5xMcBSP (2x with Sidetone/Audio Buffer) 4xMcSPI, 6xGPIO, 3xHigh-Speed MMC/SDIO, HDQ/1 Wire, 2xMailboxes 12xGPTimers, 2xWDT, 32K Sync Timer System Controls PRCM 2xSmartReflexTM Control Module External Peripherals Interfaces Emulation Debug: SDTI, ETM, JTAG, CoresightTM DAP Figure 1-1. OMAP3515/03 Functional Block Diagram 6 OMAP3515/03 Applications Processor Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Contents OMAP3515/03 Applications Processor .............. 1 1.1 Features .............................................. 1 1.2 Description ............................................ 3 1.3 Functional Block Diagram ............................ 5 4.3 5 DPLL and DLL Specifications ...................... 141 VIDEO DAC SPECIFICATIONS ..................... 148 5.1 5.2 Revision History ............................................... 8 2 TERMINAL DESCRIPTION.............................. 9 Interface Description ............................... 148 Electrical Specifications Over Recommended Operating Conditions .............................. 150 5.3 Analog Supply (vdda_dac) Noise Requirements 2.1 Terminal Assignment ................................. 9 5.4 External Component Value Choice ................ 153 2.2 Ball Characteristics .................................. 14 2.3 Multiplexing Characteristics ......................... 67 2.4 Signal Description ................................... 90 3 4 6 ELECTRICAL CHARACTERISTICS ................ 118 3.1 Power Domains .................................... 118 3.2 Absolute Maximum Ratings ........................ 120 3.3 Recommended Operating Conditions 3.4 DC Electrical Characteristics....................... 125 3.5 Core Voltage Decoupling .......................... 128 3.6 Power-up and Power-down ........................ 130 ............. 123 CLOCK SPECIFICATIONS ........................... 133 4.1 4.2 ......................... Output Clock Specifications........................ Input Clock Specifications Submit Documentation Feedback 134 139 7 .. 152 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS .................................. 154 ............................ ..................... 6.3 Timing Parameters ................................. 6.4 External Memory Interfaces........................ 6.5 Video Interfaces .................................... 6.6 Serial Communications Interfaces ................. 6.7 Removable Media Interfaces ...................... 6.8 Test Interfaces ..................................... PACKAGE CHARACTERISTICS .................... 7.1 Package Thermal Resistance ...................... 7.2 Device Support..................................... 6.1 Timing Test Conditions 154 6.2 Interface Clock Specifications 154 Contents 155 156 185 202 235 250 256 256 256 7 PRODUCT PREVIEW 1 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the technical changes made to the SPRS505A device-specific data manual to make it an SPRS505B revision. SEE Global • Added applicable updates for CBC package. Table 2-1 Updated/Changed signal name from "VDDS" to "VDDS_MMC1a" for ball numbers P27, P26, R27, and R25. Table 2-3 Updated/Changed signal name from "VDDS" to "VDDS_MMC1a" for ball numbers N22, N21, N20, and P24. PRODUCT PREVIEW Section 2.4.1 Updated/Changed Table 2-7, External Memory Interfaces – GPMC Signals Description Section 2.4.3 Updated/Changed Table 2-17, Serial Communication Interfaces – McBSP LP Signals Description Section 2.4.3 Updated/Changed Table 2-13, Serial Communication Interfaces – USB Signals Description Section 2.4.4 Updated/Changed Table 2-20, Removable Media Interfaces – MMC/SDIO Signals Description Section 2.4.8 Updated/Changed Table 2-28, System and Miscellaneous Signals Description Section 2.4.8 Updated/Changed Table 2-28, Power Supplies Signals Description Section 3.2 Updated/Changed Table 3-1, Absolute Maximum Ratings Over Operating Junction Temperature Range Section 3.3 Updated/Changed Table 3-3, Recommended Operating Conditions Section 3.4 Updated/Changed Table 3-4, DC Electrical Characteristics Section 4.1.3 Section 4.2 Section 4.3.3 8 ADDITIONS/MODIFICATIONS/DELETIONS Revision History Updated/Changed Table 4-5, 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz Input Clock Squarer Timing Requirements Updated/Changed Table 4-10, sys_clkout1 Output Clock Electrical Characteristics and Table 4-13, sys_clkout2 Output Clock Switching Characteristics Updated/Changed Table 4-14, DPLL Characteristics Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 2 TERMINAL DESCRIPTION 2.1 Terminal Assignment Figure 2-1, Figure 2-2, and Figure 2-5 show the ball locations for the 515- and 423- ball plastic ball grid array (PBGA) packages. Table 2-1 through Table 2-29 indicate the signal names and ball grid numbers for both packages. Note: There are no balls present on the top of the 423-ball PBGA package. AH AG AF PRODUCT PREVIEW AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 030-001 Figure 2-1. OMAP3515/03 Applications Processor CBB S-PBGA-N515 Package (Bottom View) Submit Documentation Feedback TERMINAL DESCRIPTION 9 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com AC AB AA Y W V U T R P PRODUCT PREVIEW N M L K J H G F E D C B A 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 030-002 Balls A1, A2, A22, A23, AB1, AB2, AB22, AB23, AC1, AC2, AC22, AC23, B1, B2, B22, and B23 are unused. Figure 2-2. OMAP3515/03 Applications Processor CBB S-PBGA-N515 Package (Top View) 10 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 PRODUCT PREVIEW AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Figure 2-3. OMAP3515/03 Applications Processor CBC-SBGA-515 Package (Bottom View) Submit Documentation Feedback TERMINAL DESCRIPTION 11 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com AA Y W V U T R P N M PRODUCT PREVIEW L K J H G F E D C B A 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 2-4. OMAP3515/03 Applications Processor CBC-SBGA-515 Package (Top View) 12 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 AD AC AB AA Y W V U T R P PRODUCT PREVIEW N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Figure 2-5. OMAP3515/03 Applications Processor CUS-PBGA-N423 Package (Bottom View) Submit Documentation Feedback TERMINAL DESCRIPTION 13 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 2.2 Ball Characteristics Table 2-1 through Table 2-3 describe the terminal characteristics and the signals multiplexed on each pin for the CBB, CBC, and CUS packages, respectively. The following list describes the table column headers. 1. BALL BOTTOM: Ball number(s) on the bottom side associated with each signal(s) on the bottom. 2. BALL TOP: Ball number(s) on the top side associated with each signal(s) on the top. 3. PIN NAME: Names of signals multiplexed on each ball (also notice that the name of the pin is the signal name in mode 0). PRODUCT PREVIEW Note: Table 2-1 through Table 2-3 do not take into account subsystem pin multiplexing options. Subsystem pin multiplexing options are described in Section 2.4, Signal Descriptions. 4. MODE: Multiplexing mode number. a. Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pin corresponds to the name of the pin. There is always a function mapped on the primary mode. Notice that primary mode is not necessarily the default mode. Note: The default mode is the mode which is automatically configured on release of the internal GLOBAL_PWRON reset; also see the RESET REL. MODE column. b. Modes 1 to 7 are possible modes for alternate functions. On each pin, some modes are effectively used for alternate functions, while some modes are not used and do not correspond to a functional configuration. 5. TYPE: Signal direction – I = Input – O = Output – I/O = Input/Output – D = Open drain – DS = Differential – A = Analog Note: In the safe_mode, the buffer is configured in high-impedance. 6. BALL RESET STATE: The state of the terminal at reset (power up). – 0: The buffer drives VOL (pulldown/pullup resistor not activated) 0(PD): The buffer drives VOL with an active pulldown resistor. – 1: The buffer drives VOH (pulldown/pullup resistor not activated) 1(PU): The buffer drives VOH with an active pullup resistor. – Z: High-impedance – L: High-impedance with an active pulldown resistor – H : High-impedance with an active pullup resistor 7. BALL RESET REL. STATE: The state of the terminal at reset release. – 0: The buffer drives VOL (pulldown/pullup resistor not activated) 0(PD): The buffer drives VOL with an active pulldown resistor. – 1: The buffer drives VOH (pulldown/pullup resistor not activated) 1(PU): The buffer drives VOH with an active pullup resistor. – Z: High-impedance – L: High-impedance with an active pulldown resistor – H : High-impedance with an active pullup resistor 8. RESET REL. MODE: This mode is automatically configured on release of the internal GLOBAL_PWRON reset. 9. POWER: The voltage supply that powers the terminal’s I/O buffers. 10. HYS: Indicates if the input buffer is with hysteresis. 11. BUFFER STRENGTH: Drive strength of the associated output buffer. 12. PULL U/D - TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and 14 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 pulldown resistors can be enabled or disabled via software. Note: The pullup/pulldown drive strength is equal to 100 µA except for CBB balls P27, P26, R27, and R25 and CUB balls N22, N21, N20, and P24, which the pulldown drive strength is equal to 1.8 kΩ. 13. IO CELL: IO cell information. Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration. Table 2-1. Ball Characteristics (CBB Pkg.) (1) BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] D6 J2 sdrc_d0 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C6 J1 sdrc_d1 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B6 G2 sdrc_d2 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C8 G1 sdrc_d3 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C9 F2 sdrc_d4 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A7 F1 sdrc_d5 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B9 D2 sdrc_d6 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A9 D1 sdrc_d7 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C14 B13 sdrc_d8 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B14 A13 sdrc_d9 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C15 B14 sdrc_d10 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B16 A14 sdrc_d11 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D17 B16 sdrc_d12 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C17 A16 sdrc_d13 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B17 B19 sdrc_d14 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D18 A19 sdrc_d15 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D11 B3 sdrc_d16 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B10 A3 sdrc_d17 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C11 B5 sdrc_d18 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D12 A5 sdrc_d19 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C12 B8 sdrc_d20 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A11 A8 sdrc_d21 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B13 B9 sdrc_d22 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D14 A9 sdrc_d23 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C18 B21 sdrc_d24 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A19 A21 sdrc_d25 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B19 D22 sdrc_d26 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B20 D23 sdrc_d27 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D20 E22 sdrc_d28 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A21 E23 sdrc_d29 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B21 G22 sdrc_d30 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C21 G23 sdrc_d31 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS H9 AB21 sdrc_ba0 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS H10 AC21 sdrc_ba1 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS A4 N22 sdrc_a0 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS B4 N23 sdrc_a1 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS B3 P22 sdrc_a2 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C5 P23 sdrc_a3 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C4 R22 sdrc_a4 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D5 R23 sdrc_a5 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C3 T22 sdrc_a6 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C2 T23 sdrc_a7 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C1 U22 sdrc_a8 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D4 U23 sdrc_a9 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS (1) PRODUCT PREVIEW BALL BOTTOM [1] NA in this table stands for Not Applicable. Submit Documentation Feedback TERMINAL DESCRIPTION 15 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] D3 V22 sdrc_a10 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D2 V23 sdrc_a11 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D1 W22 sdrc_a12 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS E2 W23 sdrc_a13 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS E1 Y22 sdrc_a14 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS H11 M22 sdrc_ncs0 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H12 M23 sdrc_ncs1 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS A13 A11 sdrc_clk 0 IO L 0 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A14 B11 sdrc_nclk 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H16 J22 sdrc_cke0 0 O H 1 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS safe_mode 7 O H 1 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS PRODUCT PREVIEW BALL BOTTOM [1] H17 sdrc_cke1 0 safe_mode 7 H14 L23 sdrc_nras 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H13 L22 sdrc_ncas 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H15 K23 sdrc_nwe 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS B7 C1 sdrc_dm0 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS A16 A17 sdrc_dm1 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS B11 A6 sdrc_dm2 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C20 A20 sdrc_dm3 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS A6 C2 sdrc_dqs0 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A17 B17 sdrc_dqs1 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A10 B6 sdrc_dqs2 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A20 B20 sdrc_dqs3 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS N4 AC15 gpmc_a1 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_34 4 IO safe_mode 7 gpmc_a2 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_35 4 IO safe_mode 7 gpmc_a3 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_36 4 IO safe_mode 7 gpmc_a4 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_37 4 IO safe_mode 7 gpmc_a5 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_38 4 IO safe_mode 7 gpmc_a6 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_39 4 IO safe_mode 7 gpmc_a7 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_40 4 IO safe_mode 7 gpmc_a8 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_41 4 IO safe_mode 7 gpmc_a9 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS sys_ ndmareq2 1 I IO H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS M4 L4 K4 T3 R3 N3 M3 L3 K3 16 J23 AB15 AC16 AB16 AC17 AB17 AC18 AB18 AC19 AB19 gpio_42 4 safe_mode 7 gpmc_a10 0 O sys_ ndmareq3 1 I TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] IO gpio_43 4 safe_mode 7 BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] K1 M2 gpmc_d0 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS L1 M1 gpmc_d1 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS L2 N2 gpmc_d2 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS P2 N1 gpmc_d3 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS T1 R2 gpmc_d4 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS V1 R1 gpmc_d5 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS V2 T2 gpmc_d6 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS W2 T1 gpmc_d7 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS H2 AB3 gpmc_d8 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_44 4 IO safe_mode 7 gpmc_d9 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_45 4 IO safe_mode 7 gpmc_d10 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_46 4 IO safe_mode 7 gpmc_d11 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_47 4 IO safe_mode 7 gpmc_d12 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_48 4 IO safe_mode 7 gpmc_d13 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_49 4 IO safe_mode 7 gpmc_d14 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_50 4 IO safe_mode 7 gpmc_d15 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_51 4 IO K2 P1 R1 R2 T2 W1 Y1 AC3 AB4 AC4 AB6 AC6 AB7 AC7 safe_mode 7 G4 Y2 gpmc_ncs0 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H3 Y1 gpmc_ncs1 0 O H 1 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_52 4 IO H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS V8 U8 T8 R8 NA NA NA NA safe_mode 7 gpmc_ncs2 0 O gpio_53 4 IO safe_mode 7 gpmc_ncs3 0 O sys_ ndmareq0 1 I IO gpio_54 4 safe_mode 7 gpmc_ncs4 0 O sys_ ndmareq1 1 I mcbsp4_ clkx 2 IO gpt9_pwm_evt 3 IO gpio_55 4 IO safe_mode 7 gpmc_ncs5 0 O sys_ ndmareq2 1 I mcbsp4_dr 2 I Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW BALL BOTTOM [1] 17 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] P8 BALL TOP [2] NA N8 NA PRODUCT PREVIEW T4 W2 PIN NAME [3] MODE [4] TYPE [5] gpt10_pwm_evt 3 IO gpio_56 4 IO safe_mode 7 gpmc_ncs6 0 O sys_ ndmareq3 1 I mcbsp4_dx 2 IO gpt11_pwm_evt 3 IO gpio_57 4 IO safe_mode 7 gpmc_ncs7 0 O gpmc_io_dir 1 O mcbsp4_fsx 2 IO gpt8_pwm_evt 3 IO gpio_58 4 IO safe_mode 7 gpmc_clk 0 O gpio_59 4 IO BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS L 0 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS safe_mode 7 F3 W1 gpmc_nadv_ale 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS G2 V2 gpmc_noe 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS F4 V1 gpmc_nwe 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS G3 AC12 gpmc_nbe0_cle 0 O L 0 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_60 4 IO L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS L 0 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS U3 NA safe_mode 7 gpmc_nbe1 0 O gpio_61 4 IO safe_mode H1 AB10 7 gpmc_nwp 0 O gpio_62 4 IO safe_mode 7 M8 AB12 gpmc_wait0 0 I H H 0 VDDS_ MEM Yes NA PU/ PD LVCMOS L8 AC10 gpmc_wait1 0 I H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_63 4 IO H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS No 4 PU/ PD LVDS/ CMOS K8 NA J8 NA D28 NA D26 NA D27 NA E27 NA AG22 18 BALL RESET STATE [6] NA safe_mode 7 gpmc_wait2 0 I gpio_64 4 IO safe_mode 7 gpmc_wait3 0 I sys_ ndmareq1 1 I IO gpio_65 4 safe_mode 7 dss_pclk 0 O gpio_66 4 IO safe_mode 7 dss_hsync 0 O gpio_67 4 IO safe_mode 7 dss_vsync 0 O gpio_68 4 IO safe_mode 7 dss_acbias 0 O gpio_69 4 IO safe_mode 7 dss_data0 0 TERMINAL DESCRIPTION IO Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 AH22 AG23 AH23 AG24 AH24 E26 F28 F27 G26 AD28 AD27 AB28 AB27 AA28 AA27 BALL TOP [2] NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA PIN NAME [3] MODE [4] TYPE [5] uart1_cts 2 I gpio_70 4 IO safe_mode 7 dss_data1 0 IO uart1_rts 2 O IO gpio_71 4 safe_mode 7 dss_data2 0 IO gpio_72 4 IO safe_mode 7 dss_data3 0 IO gpio_73 4 IO safe_mode 7 dss_data4 0 IO uart3_rx_ irrx 2 I IO gpio_74 4 safe_mode 7 dss_data5 0 IO uart3_tx_ irtx 2 O IO gpio_75 4 safe_mode 7 dss_data6 0 IO uart1_tx 2 O IO gpio_76 4 safe_mode 7 dss_data7 0 IO uart1_rx 2 I IO gpio_77 4 safe_mode 7 dss_data8 0 IO gpio_78 4 IO safe_mode 7 dss_data9 0 IO gpio_79 4 IO safe_mode 7 dss_data10 0 IO gpio_80 4 IO safe_mode 7 dss_data11 0 IO gpio_81 4 IO safe_mode 7 dss_data12 0 IO gpio_82 4 IO safe_mode 7 dss_data13 0 IO gpio_83 4 IO safe_mode 7 dss_data14 0 IO gpio_84 4 IO safe_mode 7 dss_data15 0 IO gpio_85 4 IO safe_mode 7 Submit Documentation Feedback BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] L L 7 VDDS No 4 PU/ PD LVDS/ CMOS L L 7 VDDS No 4 PU/ PD LVDS/ CMOS L L 7 VDDS No 4 PU/ PD LVDS/ CMOS L L 7 VDDS No 4 PU/ PD LVDS/ CMOS L L 7 VDDS No 4 PU/ PD LVDS/ CMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS TERMINAL DESCRIPTION 19 PRODUCT PREVIEW Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] G25 NA dss_data16 0 IO L L 7 VDDS Yes 8 PU/ PD LVCMOS gpio_86 4 IO L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS H27 H26 PRODUCT PREVIEW H25 E28 J26 AC27 AC28 NA NA NA NA NA NA safe_mode 7 dss_data17 0 IO gpio_87 4 IO safe_mode 7 dss_data18 0 IO mcspi3_clk 2 IO dss_data0 3 IO gpio_88 4 IO safe_mode 7 dss_data19 0 IO mcspi3_ simo 2 IO dss_data1 3 IO gpio_89 4 IO safe_mode 7 dss_data20 0 O mcspi3_ somi 2 IO dss_data2 3 IO gpio_90 4 IO safe_mode 7 dss_data21 0 O mcspi3_cs0 2 IO dss_data3 3 IO gpio_91 4 IO safe_mode 7 dss_data22 0 O mcspi3_cs1 2 O dss_data4 3 IO gpio_92 4 IO safe_mode 7 dss_data23 0 O dss_data5 3 IO IO gpio_93 4 safe_mode 7 W28 NA tv_out2 0 O Z 0 0 VDDADAC 8 NA 10-bit DAC Y28 NA tv_out1 0 O Z 0 0 VDDADAC 8 NA 10-bit DAC Y27 NA tv_vfb1 0 O Z NA 0 VDDADAC NA 10-bit DAC W27 NA tv_vfb2 0 O Z NA 0 VDDADAC NA 10-bit DAC W26 NA tv_vref 0 I Z NA 0 VDDADAC NA 10-bit DAC A24 NA cam_hs 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS gpio_94 4 IO safe_mode 7 cam_vs 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS gpio_95 4 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS A23 C25 C27 C23 20 NA NA NA NA NA safe_mode 7 cam_ xclka 0 O gpio_96 4 IO safe_mode 7 cam_pclk 0 I gpio_97 4 IO safe_mode 7 cam_fld 0 IO cam_global_reset 2 IO TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 AG17 AH17 B24 C24 D24 A25 K28 L28 K27 L27 B25 C26 B26 B23 D25 AG19 AH19 AG18 BALL TOP [2] NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] IO L L 7 VDDS Yes 4 PD LVDS/ CMOS L L 7 VDDS Yes 4 PD LVDS/ CMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS NA 4 PD LVDS/ CMOS L L 7 VDDS NA 4 PD LVDS/ CMOS L L 7 VDDS NA 4 PD LVDS/ CMOS L L 7 VDDS NA 4 PD LVDS/ CMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS I L L 7 VDDS Yes 4 PD LVDS/ CMOS I L L 7 VDDS Yes 4 PD LVDS/ CMOS I L L 7 VDDS Yes 4 PD LVDS/ CMOS gpio_98 4 safe_mode 7 cam_d0 0 I gpio_99 4 I safe_mode 7 cam_d1 0 I gpio_100 4 I safe_mode 7 cam_d2 0 I gpio_101 4 IO safe_mode 7 cam_d3 0 I gpio_102 4 IO safe_mode 7 cam_d4 0 I gpio_103 4 IO safe_mode 7 cam_d5 0 I gpio_104 4 IO safe_mode 7 cam_d6 0 I gpio_105 4 IO safe_mode 7 cam_d7 0 I gpio_106 4 IO safe_mode 7 cam_d8 0 I gpio_107 4 IO safe_mode 7 cam_d9 0 I gpio_108 4 IO safe_mode 7 cam_d10 0 I gpio_109 4 IO safe_mode 7 cam_d11 0 I gpio_110 4 IO safe_mode 7 cam_ xclkb 0 O gpio_111 4 IO safe_mode 7 cam_wen 0 I cam_ shutter 2 O IO gpio_167 4 safe_mode 7 cam_ strobe 0 O gpio_126 4 IO safe_mode 7 gpio_112 4 safe_mode 7 gpio_113 4 safe_mode 7 gpio_114 4 safe_mode 7 Submit Documentation Feedback TERMINAL DESCRIPTION 21 PRODUCT PREVIEW Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] AH18 NA P21 N21 R21 PRODUCT PREVIEW M21 N28 M27 N27 N26 N25 P28 P27 P26 R27 R25 AE2 AG5 (2) 22 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] I L L 7 VDDS Yes 4 PD LVDS/ CMOS PGM L 7 VDDS Yes 4 (2) PU/ PD LVCMOS PGM L 7 VDDS Yes 4 (2) PU/ PD LVCMOS PGM L 7 VDDS Yes 4 (2) PU/ PD LVCMOS PGM L 7 VDDS Yes 4 (2) PU/ PD LVCMOS L L 7 MMC1_ VDDS Yes 8 PU/ PD LVCMOS L L 7 MMC1_ VDDS Yes 8 PU/ PD LVCMOS L L 7 MMC1_ VDDS Yes 8 PU/ PD LVCMOS L L 7 MMC1_ VDDS Yes 8 PU/ PD LVCMOS L L 7 MMC1_ VDDS Yes 8 PU/ PD LVCMOS L L 7 MMC1_ VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS_MMC1a No 8 PD LVCMOS L L 7 VDDS_MMC1a No 8 PD LVCMOS L L 7 VDDS_MMC1a No 8 PD LVCMOS L L 7 VDDS_MMC1a No 8 PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS gpio_115 4 safe_mode 7 mcbsp2_fsx 0 IO gpio_116 4 IO safe_mode 7 mcbsp2_ clkx 0 IO gpio_117 4 IO safe_mode 7 mcbsp2_dr 0 I gpio_118 4 IO safe_mode 7 mcbsp2_dx 0 IO gpio_119 4 IO safe_mode 7 mmc1_clk 0 O gpio_120 4 IO safe_mode 7 mmc1_cmd 0 IO gpio_121 4 IO safe_mode 7 mmc1_dat0 0 IO gpio_122 4 IO safe_mode 7 mmc1_dat1 0 IO gpio_123 4 IO safe_mode 7 mmc1_dat2 0 IO gpio_124 4 IO safe_mode 7 mmc1_dat3 0 IO gpio_125 4 IO safe_mode 7 mmc1_dat4 0 IO gpio_126 4 IO safe_mode 7 mmc1_dat5 0 IO gpio_127 4 IO safe_mode 7 mmc1_dat6 0 IO gpio_128 4 IO safe_mode 7 mmc1_dat7 0 IO gpio_129 4 IO safe_mode 7 mmc2_clk 0 O mcspi3_clk 1 IO IO gpio_130 4 safe_mode 7 mmc2_ cmd 0 IO mcspi3_ simo 1 IO gpio_131 4 IO safe_mode 7 The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in the above table. TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL TOP [2] AH5 NA AH4 AG4 AF4 AE4 AH3 AF3 AE3 AF6 AE6 NA NA NA NA NA NA NA NA NA PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS mmc2_ dat0 0 IO mcspi3_ somi 1 IO IO gpio_132 4 safe_mode 7 mmc2_ dat1 0 IO gpio_133 4 IO safe_mode 7 mmc2_ dat2 0 IO mcspi3_cs1 1 O IO gpio_134 4 safe_mode 7 mmc2_ dat3 0 IO mcspi3_cs0 1 IO IO gpio_135 4 safe_mode 7 mmc2_ dat4 0 IO mmc2_dir_dat0 1 O mmc3_dat0 3 IO gpio_136 4 IO safe_mode 7 mmc2_ dat5 0 IO mmc2_dir_dat1 1 O cam_global_reset 2 IO mmc3_dat1 3 IO gpio_137 4 IO hsusb3_tll_stp 5 IO mm3_rxdp 6 IO safe_mode 7 mmc2_ dat6 0 IO mmc2_dir_ cmd 1 O cam_ shutter 2 O mmc3_dat2 3 IO gpio_138 4 IO hsusb3_tll_dir 5 IO safe_mode 7 mmc2_ dat7 0 IO mmc2_ clkin 1 I mmc3_dat3 3 IO gpio_139 4 IO hsusb3_tll_nxt 5 IO mm3_rxdm 6 IO safe_mode 7 mcbsp3_dx 0 IO uart2_cts 1 I gpio_140 4 IO hsusb3_tll_ data4 5 IO safe_mode 7 mcbsp3_dr 0 I uart2_rts 1 O gpio_141 4 IO hsusb3_tll_ data5 5 IO safe_mode 7 Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW BALL BOTTOM [1] 23 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] AF5 NA mcbsp3_ clkx 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS uart2_tx 1 O L L 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS AE5 PRODUCT PREVIEW AB26 AB25 AA25 AD25 AA8 AA9 W8 Y8 AE1 AD1 24 NA NA NA NA NA NA NA NA NA NA NA gpio_142 4 IO hsusb3_tll_ data6 5 IO safe_mode 7 mcbsp3_fsx 0 IO uart2_rx 1 I gpio_143 4 IO hsusb3_tll_ data7 5 IO safe_mode 7 uart2_cts 0 I mcbsp3_dx 1 IO gpt9_pwm_evt 2 IO gpio_144 4 IO safe_mode 7 uart2_rts 0 O mcbsp3_dr 1 I gpt10_pwm_evt 2 IO gpio_145 4 IO safe_mode 7 uart2_tx 0 O mcbsp3_ clkx 1 IO gpt11_pwm _evt 2 IO gpio_146 4 IO safe_mode 7 uart2_rx 0 I mcbsp3_fsx 1 IO gpt8_pwm_evt 2 IO gpio_147 4 IO safe_mode 7 uart1_tx 0 O gpio_148 4 IO safe_mode 7 uart1_rts 0 O gpio_149 4 IO safe_mode 7 uart1_cts 0 I gpio_150 4 IO hsusb3_tll_clk 5 O safe_mode 7 uart1_rx 0 I mcbsp1_ clkr 2 IO mcspi4_clk 3 IO gpio_151 4 IO safe_mode 7 mcbsp4_ clkx 0 IO gpio_152 4 IO hsusb3_tll_ data1 5 IO mm3_txse0 6 IO safe_mode 7 mcbsp4_dr 0 I gpio_153 4 IO hsusb3_tll_ data0 5 IO mm3_rxrcv 6 IO TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL TOP [2] PIN NAME [3] MODE [4] safe_mode 7 AD2 NA mcbsp4_dx gpio_154 AC1 Y21 AA21 V21 U21 T21 K26 W21 H18 H19 H20 H21 NA NA NA NA NA NA NA NA NA NA NA NA TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS 4 IO hsusb3_tll_ data2 5 IO mm3_txdat 6 IO safe_mode 7 mcbsp4_fsx 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS gpio_155 4 IO hsusb3_tll_ data3 5 IO mm3_txen_n 6 IO safe_mode 7 mcbsp1_ clkr 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS mcspi4_clk 1 IO IO L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS gpio_156 4 safe_mode 7 mcbsp1_fsr 0 IO cam_global_reset 2 IO IO gpio_157 4 safe_mode 7 mcbsp1_dx 0 IO mcspi4_ simo 1 IO mcbsp3_dx 2 IO gpio_158 4 IO safe_mode 7 mcbsp1_dr 0 I mcspi4_ somi 1 IO mcbsp3_dr 2 O gpio_159 4 IO safe_mode 7 mcbsp_clks 0 I cam_ shutter 2 O gpio_160 4 IO uart1_cts 5 I safe_mode 7 mcbsp1_fsx 0 IO mcspi4_cs0 1 IO mcbsp3_fsx 2 IO gpio_161 4 IO safe_mode 7 mcbsp1_ clkx 0 IO mcbsp3_ clkx 2 IO IO gpio_162 4 safe_mode 7 uart3_cts_ rctx 0 IO gpio_163 4 IO safe_mode 7 uart3_rts_ sd 0 O gpio_164 4 IO safe_mode 7 uart3_rx_ irrx 0 I gpio_165 4 IO safe_mode 7 uart3_tx_ irtx 0 O gpio_166 4 IO Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW BALL BOTTOM [1] 25 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] PIN NAME [3] MODE [4] safe_mode 7 T28 NA hsusb0_clk gpio_120 T25 NA R28 NA PRODUCT PREVIEW T26 NA T27 NA U28 NA U27 NA U26 NA U25 NA V28 NA V27 NA V26 NA BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] 0 I L L 7 VDDS Yes 4 PU/ PD LVCMOS 4 IO H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS safe_mode 7 hsusb0_stp 0 O gpio_121 4 IO safe_mode 7 hsusb0_dir 0 I gpio_122 4 IO safe_mode 7 hsusb0_nxt 0 I gpio_124 4 IO safe_mode 7 hsusb0_ data0 0 IO uart3_tx_ irtx 2 O IO gpio_125 4 safe_mode 7 hsusb0_ data1 0 IO uart3_rx_ irrx 2 I IO gpio_130 4 safe_mode 7 hsusb0_ data2 0 IO uart3_rts_ sd 2 O IO gpio_131 4 safe_mode 7 hsusb0_ data3 0 IO uart3_cts_ rctx 2 IO IO gpio_169 4 safe_mode 7 hsusb0_ data4 0 IO gpio_188 4 IO safe_mode 7 hsusb0_ data5 0 IO gpio_189 4 IO safe_mode 7 hsusb0_ data6 0 IO gpio_190 4 IO safe_mode 7 hsusb0_ data7 0 IO gpio_191 4 IO safe_mode 7 K21 NA i2c1_scl 0 IOD H H 0 VDDS Yes 4 PU/ PD Open Drain J21 NA i2c1_sda 0 IOD H H 0 VDDS Yes 4 PU/ PD Open Drain AF15 NA i2c2_scl 0 IOD H H 7 VDDS Yes 4 PU/ PD Open Drain gpio_168 4 IO safe_mode 7 i2c2_sda 0 IOD H H 7 VDDS Yes 4 PU/ PD Open Drain gpio_183 4 IO safe_mode 7 i2c3_scl 0 IOD H H 7 VDDS Yes 4 PU/ PD Open Drain gpio_184 4 IO safe_mode 7 i2c3_sda 0 IOD H H 7 VDDS Yes 4 PU/ PD Open Drain gpio_185 4 IO AE15 NA AF14 NA AG14 26 TYPE [5] NA TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL TOP [2] AD26 NA AE26 J25 AB3 AB4 AA4 AC2 AC3 AB1 AB2 AA3 Y2 NA NA NA NA NA NA NA NA NA NA NA PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] safe_mode 7 i2c4_scl sys_ nvmode1 0 IOD H H 0 VDDS Yes 4 PU/ PD Open Drain 1 O safe_mode 7 i2c4_sda 0 IOD sys_ nvmode2 1 O H H 0 VDDS Yes 4 PU/ PD Open Drain safe_mode 7 hdq_sio 0 IOD sys_altclk 1 I H H 7 VDDS Yes 4 PU/ PD LVCMOS i2c2_sccbe 2 O i2c3_sccbe 3 O gpio_170 4 IO safe_mode 7 mcspi1_clk 0 IO PGM L 7 VDDS Yes 4 (2) mmc2_dat4 1 IO PU/ PD LVCMOS IO PGM L 7 VDDS Yes 4 (2) PU/ PD LVCMOS PGM L 7 VDDS Yes 4 (2) PU/ PD LVCMOS PGM H 7 VDDS Yes 4 (2) PU/ PD LVCMOS PGM H 7 VDDS Yes 4 (2) PU/ PD LVCMOS PGM H 7 VDDS Yes 4 (2) PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS gpio_171 4 safe_mode 7 mcspi1_ simo 0 IO mmc2_dat5 1 IO IO gpio_172 4 safe_mode 7 mcspi1_ somi 0 IO mmc2_dat6 1 IO IO gpio_173 4 safe_mode 7 mcspi1_cs0 0 IO mmc2_dat7 1 IO IO gpio_174 4 safe_mode 7 mcspi1_cs1 0 O mmc3_cmd 3 IO IO gpio_175 4 safe_mode 7 mcspi1_cs2 0 O mmc3_clk 3 O IO gpio_176 4 safe_mode 7 mcspi1_cs3 0 O hsusb2_tll_ data2 2 IO hsusb2_ data2 3 IO gpio_177 4 IO mm2_txdat 5 IO safe_mode 7 mcspi2_clk 0 IO hsusb2_tll_ data7 2 IO hsusb2_ data7 3 O gpio_178 4 IO safe_mode 7 mcspi2_ simo 0 IO gpt9_pwm_evt 1 IO hsusb2_tll_ data4 2 IO hsusb2_ data4 3 I gpio_179 4 IO safe_mode 7 Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW BALL BOTTOM [1] 27 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] Y3 NA Y4 NA PRODUCT PREVIEW V3 NA MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] L L 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS NA mcspi2_ somi 0 IO gpt10_pwm_evt 1 IO hsusb2_tll_ data5 2 IO hsusb2_ data5 3 O gpio_180 4 IO safe_mode 7 mcspi2_cs0 0 IO gpt11_pwm_evt 1 IO hsusb2_tll_ data6 2 IO hsusb2_ data6 3 O gpio_181 4 IO safe_mode 7 mcspi2_cs1 0 O gpt8_pwm_evt 1 IO hsusb2_tll_ data3 2 IO hsusb2_ data3 3 IO gpio_182 4 IO mm2_txen_n 5 IO safe_mode 7 AE25 NA sys_32k 0 I Z I NA VDDS Yes NA LVCMOS AE17 NA sys_xtalin 0 I Z I NA VDDS Yes NA LVCMOS AF17 NA sys_xtalout 0 O Z O NA VDDS Yes NA LVCMOS AF25 NA sys_clkreq 0 IO 0 1 0 VDDS Yes 4 PU/ PD LVCMOS gpio_1 4 IO safe_mode 7 sys_nirq 0 I H H 7 VDDS Yes 4 PU/ PD LVCMOS gpio_0 4 IO AF26 NA safe_mode 7 AH25 NA sys_ nrespwron 0 I Z I NA VDDS Yes NA NA LVCMOS AF24 NA sys_ nreswarm 0 IOD 0 1 (PU) 0 VDDS Yes 4 PU/ PD LVCMOS gpio_30 4 IO safe_mode 7 sys_boot0 0 I Z Z 0 VDDS Yes 4 PU/ PD LVCMOS gpio_2 4 IO safe_mode 7 sys_boot1 0 I Z Z 0 VDDS Yes 4 PU/ PD LVCMOS gpio_3 4 IO safe_mode 7 sys_boot2 0 I Z Z 0 VDDS Yes 4 PU/ PD LVCMOS gpio_4 4 IO safe_mode 7 sys_boot3 0 I Z Z 0 VDDS Yes 4 PU/ PD LVCMOS gpio_5 4 IO safe_mode 7 sys_boot4 0 I Z Z 0 VDDS Yes 4 PU/ PD LVCMOS mmc2_dir_dat2 1 O IO Z Z 0 VDDS Yes 4 PU/ PD LVCMOS Z Z 0 VDDS Yes 4 PU/ PD LVCMOS AH26 NA AG26 AE14 AF18 AF19 AE21 AF21 28 PIN NAME [3] NA NA NA NA NA NA gpio_6 4 safe_mode 7 sys_boot5 0 I mmc2_dir_dat3 1 O IO gpio_7 4 safe_mode 7 sys_boot6 0 I gpio_8 4 IO TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL TOP [2] PIN NAME [3] MODE [4] safe_mode 7 AF22 NA sys_off_ mode gpio_9 AG25 AE22 NA NA TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] 0 O 0 L 7 VDDS Yes 4 PU/ PD LVCMOS 4 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS safe_mode 7 sys_clkout1 0 O gpio_10 4 IO safe_mode 7 sys_clkout2 0 O gpio_186 4 IO safe_mode 7 B1 NA sys_ ipmcsws 0 AI Z AI NA VDDS NA NA NA Analog A1 NA sys_ opmcsws 0 AO 0 AO NA VDDS No NA NA LVCMOS AA17 NA jtag_ntrst 0 I L L 0 VDDS Yes NA PU/ PD LVCMOS AA13 NA jtag_tck 0 I L L 0 VDDS Yes NA PU/ PD LVCMOS AA12 NA jtag_rtck 0 O L 0 0 VDDS Yes 4 PU/ PD LVCMOS AA18 NA jtag_tms_tmsc 0 IO H H 0 VDDS Yes 4 PU/ PD LVCMOS AA20 NA jtag_tdi 0 I H H 0 VDDS Yes NA PU/ PD LVCMOS AA19 NA jtag_tdo 0 O L Z 0 VDDS Yes 4 PU/ PD LVCMOS AA11 NA jtag_emu0 0 IO H H 0 VDDS Yes 4 PU/ PD LVCMOS gpio_11 4 IO safe_mode 7 jtag_emu1 0 IO H H 0 VDDS Yes 4 PU/ PD LVCMOS gpio_31 4 IO safe_mode 7 etk_clk 0 O H H 4 VDDS Yes 4 PU/ PD LVCMOS mcbsp5_ clkx 1 IO O H H 4 VDDS Yes 4 PU/ PD LVCMOS H H 4 VDDS Yes 4 PU/ PD LVCMOS H H 4 VDDS Yes 4 PU/ PD LVCMOS AA10 AF10 AE10 AF11 AG12 NA NA NA NA NA mmc3_clk 2 hsusb1_stp 3 O gpio_12 4 IO IO mm1_rxdp 5 hsusb1_tll_stp 6 I etk_ctl 0 O mmc3_cmd 2 IO hsusb1_clk 3 O gpio_13 4 IO hsusb1_tll_clk 6 O etk_d0 0 O mcspi3_ simo 1 IO mmc3_dat4 2 IO hsusb1_ data0 3 IO gpio_14 4 IO mm1_rxrcv 5 IO hsusb1_tll_ data0 6 IO etk_d1 0 O mcspi3_ somi 1 IO hsusb1_ data1 3 IO gpio_15 4 IO mm1_txse0 5 IO hsusb1_tll_ data1 6 IO Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW BALL BOTTOM [1] 29 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] AH12 NA AE13 PRODUCT PREVIEW AE11 AH9 AF13 AH14 AF9 AG9 30 NA NA NA NA NA NA NA PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] H H 4 VDDS Yes 4 PU/ PD LVCMOS H H 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS etk_d2 0 O mcspi3_cs0 1 IO hsusb1_ data2 3 IO gpio_16 4 IO mm1_txdat 5 IO hsusb1_tll_data2 6 IO etk_d3 0 O mcspi3_clk 1 IO mmc3_dat3 2 IO hsusb1_ data7 3 IO gpio_17 4 IO hsusb1_tll_ data7 6 IO etk_d4 0 O mcbsp5_dr 1 I mmc3_dat0 2 IO hsusb1_ data4 3 IO gpio_18 4 IO hsusb1_tll_ data4 6 IO etk_d5 0 O mcbsp5_fsx 1 IO mmc3_dat1 2 IO hsusb1_ data5 3 IO gpio_19 4 IO hsusb1_tll_ data5 6 IO etk_d6 0 O mcbsp5_dx 1 IO mmc3_dat2 2 IO hsusb1_ data6 3 IO gpio_20 4 IO hsusb1_tll_ data6 6 IO etk_d7 0 O mcspi3_cs1 1 O mmc3_dat7 2 IO hsusb1_ data3 3 IO gpio_21 4 IO mm1_txen_n 5 IO hsusb1_tll_ data3 6 IO etk_d8 0 O sys_drm_ msecure 1 O mmc3_dat6 2 IO hsusb1_dir 3 I gpio_22 4 IO hsusb1_tll_dir 6 O etk_d9 0 O sys_secure_indic ator 1 O mmc3_dat5 2 IO hsusb1_nxt 3 I gpio_23 4 IO mm1_rxdm 5 IO hsusb1_tll_nxt 6 O TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL TOP [2] AE7 NA AF7 AG7 AH7 AG8 AH8 NA NA NA NA NA PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS etk_d10 0 O uart1_rx 2 I hsusb2_clk 3 O gpio_24 4 IO hsusb2_tll_clk 6 O etk_d11 0 O hsusb2_stp 3 O gpio_25 4 IO mm2_rxdp 5 IO hsusb2_tll_stp 6 I etk_d12 0 O hsusb2_dir 3 I gpio_26 4 IO hsusb2_tll_dir 6 O etk_d13 0 O hsusb2_nxt 3 I gpio_27 4 IO mm2_rxdm 5 IO hsusb2_tll_nxt 6 O etk_d14 0 O hsusb2_ data0 3 IO gpio_28 4 IO mm2_rxrcv 5 IO hsusb2_tll_ data0 6 IO etk_d15 0 O hsusb2_ data1 3 IO gpio_29 4 IO mm2_txse0 5 IO hsusb2_tll_ data1 6 IO Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW BALL BOTTOM [1] 31 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.) BALL BOTTOM [1] BALL TOP [2] AE16 - AE15 AD17 PRODUCT PREVIEW AE18 AD16 AE17 32 - - - - MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] L L 7 - Yes 4 PU100/ PD100 LVDS/ CMOS L L 7 - Yes 4 PU100/ PD100 LVDS/ CMOS L L 7 - Yes 4 PU100/ PD100 LVDS/ CMOS L L 7 - Yes 4 PU100/ PD100 LVDS/ CMOS L L 7 - Yes 4 PU100/ PD100 LVDS/ CMOS L L 7 Yes 4 PU100/ PD100 LVDS/ CMOS cam_d0 0 I - 2 IDS gpio_99 4 I safe_mode 7 - cam_d1 0 I - 2 IDS gpio_100 4 I safe_mode 7 - - 0 IDS gpio_112 4 I safe_mode 7 - - 0 IDS gpio_114 4 I safe_mode 7 - - 0 IDS gpio_113 4 I safe_mode 7 - - 0 IDS gpio_115 4 I safe_mode 7 - - G20 sdrc_a0 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - K20 sdrc_a1 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - J20 sdrc_a2 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - J21 sdrc_a3 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - U21 sdrc_a4 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS (1) NA LVDS/ CMOS - R20 sdrc_a5 0 O 0 0 0 vdds_io No 4 - M21 sdrc_a6 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - M20 sdrc_a7 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - N20 sdrc_a8 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - K21 sdrc_a9 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - Y16 sdrc_a10 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - N21 sdrc_a11 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - R21 sdrc_a12 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - AA15 sdrc_a13 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - Y12 sdrc_a14 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - AA18 sdrc_ba0 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - V20 sdrc_ba1 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - Y15 sdrc_cke0 0 O H 1 7 vdds_io Yes 4 (1) safe_mode 7 PU100/ PD100 LVDS/ CMOS sdrc_cke1 0 O H 1 7 vdds_io Yes 4 (1) safe_mode 7 PU100/ PD100 LVDS/ CMOS - (1) - PIN NAME [4] Y13 The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the selected mode. TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 BALL TOP [2] - A12 - PIN NAME [4] MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] sdrc_clk 0 IO L 0 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS D1 sdrc_d0 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - G1 sdrc_d1 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - G2 sdrc_d2 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - E1 sdrc_d3 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - D2 sdrc_d4 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - E2 sdrc_d5 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - B3 sdrc_d6 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - B4 sdrc_d7 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - A10 sdrc_d8 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - B11 sdrc_d9 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - A11 sdrc_d10 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - B12 sdrc_d11 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - A16 sdrc_d12 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - A17 sdrc_d13 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - B17 sdrc_d14 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - B18 sdrc_d15 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - B7 sdrc_d16 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - A5 sdrc_d17 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - B6 sdrc_d18 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS (1) PU100/ PD100 LVDS/ CMOS - A6 sdrc_d19 0 IO L Z 0 vdds_io Yes 4 - A8 sdrc_d20 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - B9 sdrc_d21 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - A9 sdrc_d22 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - B10 sdrc_d23 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - C21 sdrc_d24 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - D20 sdrc_d25 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - B19 sdrc_d26 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - C20 sdrc_d27 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - D21 sdrc_d28 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - E20 sdrc_d29 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - E21 sdrc_d30 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS Submit Documentation Feedback TERMINAL DESCRIPTION 33 PRODUCT PREVIEW Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] - G21 - PRODUCT PREVIEW MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] sdrc_d31 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS H1 sdrc_dm0 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - A14 sdrc_dm1 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - A4 sdrc_dm2 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - A18 sdrc_dm3 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - C2 sdrc_dqs0 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - B15 sdrc_dqs1 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - B8 sdrc_dqs2 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - A19 sdrc_dqs3 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PD100 LVDS/ CMOS - U20 sdrc_ncas 0 O 1 1 0 vdds_io No 4 (1) NA LVDS/ CMOS - B13 sdrc_nclk 0 O 1 1 0 vdds_io No 4 (1) NA LVDS/ CMOS - T21 sdrc_ncs0 0 O 1 1 0 vdds_io No 4 (1) NA LVDS/ CMOS - T20 sdrc_ncs1 0 O 1 1 0 vdds_io No 4 (1) NA LVDS/ CMOS - V21 sdrc_nras 0 O 1 1 0 vdds_io No 4 (1) NA LVDS/ CMOS - Y18 sdrc_nwe 0 O 1 1 0 vdds_io No 4 (1) NA LVDS/ CMOS AE21 - dss_data0 0 IO L L 7 - No 4 - 1 ODS PU100/ PD100 LVDS/ CMOS uart1_cts 2 I gpio_70 4 IO safe_mode 7 - dss_data1 0 IO L L 7 - No 4 - 1 ODS PU100/ PD100 LVDS/ CMOS uart1_rts 2 O gpio_71 4 IO safe_mode 7 - dss_data2 0 IO L L 7 - No 4 - 1 ODS PU100/ PD100 LVDS/ CMOS gpio_72 4 IO safe_mode 7 - dss_data3 0 IO L L 7 - No 4 - 1 ODS PU100/ PD100 LVDS/ CMOS gpio_73 4 IO safe_mode 7 - dss_data4 0 IO L L 7 - No 4 - 1 ODS PU100/ PD100 LVDS/ CMOS uart3_rx_irrx 2 I gpio_74 4 IO safe_mode 7 - dss_data5 0 IO L L 7 - No 4 - 1 ODS PU100/ PD100 LVDS/ CMOS uart3_tx_irtx 2 O gpio_75 4 IO safe_mode 7 - AE22 AE23 AE24 AD23 AD24 34 - - - - - PIN NAME [4] TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 BALL TOP [2] AC26 - AD26 AA25 Y25 AA26 AB26 F25 AC25 AB25 G25 J2 H1 H2 - - - - - - - - - - - - PIN NAME [4] MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] L L 7 - NA 4 PU100/ PD100 LVDS/ CMOS L L 7 - NA 4 PU100/ PD100 LVDS/ CMOS L L 7 - NA 4 PU100/ PD100 LVDS/ CMOS L L 7 - NA 4 PU100/ PD100 LVDS/ CMOS L L 7 - NA 4 PU100/ PD100 LVDS/ CMOS L L 7 - NA 4 PU100/ PD100 LVDS/ CMOS H H 7 vdds_io Yes 4 PU100/ PD100 LVCMOS L L 7 - NA 4 PU100/ PD100 LVDS/ CMOS L L 7 - NA 4 PU100/ PD100 LVDS/ CMOS H H 7 vdds_io Yes 4 PU100/ PD100 LVCMOS L L 7 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS L L 7 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS L L 7 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS dss_data10 0 IO - 1 ODS gpio_80 4 IO safe_mode 7 - dss_data11 0 IO - 1 ODS gpio_81 4 IO safe_mode 7 - dss_data12 0 IO - 1 ODS gpio_82 4 IO safe_mode 7 - dss_data13 0 IO - 1 ODS gpio_83 4 IO safe_mode 7 - dss_data14 0 IO - 1 ODS gpio_84 4 IO safe_mode 7 - dss_data15 0 IO - 1 ODS gpio_85 4 IO safe_mode 7 - dss_data20 0 O - 1 O mcspi3_somi 2 IO dss_data2 3 IO gpio_90 4 IO safe_mode 7 - dss_data22 0 O - 1 ODS mcspi3_cs1 2 O dss_data4 3 IO gpio_92 4 IO safe_mode 7 - dss_data23 0 O - 1 ODS dss_data5 3 IO gpio_93 4 IO safe_mode 7 - dss_pclk 0 O gpio_66 4 IO hw_dbg12 5 O safe_mode 7 - gpmc_a1 0 O gpio_34 4 IO safe_mode 7 - gpmc_a2 0 O gpio_35 4 IO safe_mode 7 - gpmc_a3 0 O gpio_36 4 IO Submit Documentation Feedback TERMINAL DESCRIPTION 35 PRODUCT PREVIEW Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] G2 - F1 F2 PRODUCT PREVIEW E1 E2 D1 D2 N1 - - - - - L1 MODE [5] TYPE [6] safe_mode 7 - gpmc_a4 0 O gpio_37 4 IO safe_mode 7 - gpmc_a5 0 O gpio_38 4 IO safe_mode 7 - gpmc_a6 0 O gpio_39 4 IO safe_mode 7 - gpmc_a7 0 O gpio_40 4 IO safe_mode 7 - gpmc_a8 0 O gpio_41 4 IO safe_mode 7 - gpmc_a9 0 O sys_ndmareq2 1 I gpio_42 4 IO safe_mode 7 - gpmc_a10 0 O sys_ndmareq3 1 I gpio_43 4 IO safe_mode 7 - gpmc_clk 0 O gpio_59 4 IO BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] L L 7 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS L L 7 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS H H 7 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS H H 7 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS H H 7 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS H H 7 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS H H 7 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS L 0 0 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS safe_mode 7 - AA2 U2 gpmc_d0 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS AA1 U1 gpmc_d1 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS AC2 V2 gpmc_d2 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS AC1 V1 gpmc_d3 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS AE5 AA3 gpmc_d4 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS AD6 AA4 gpmc_d5 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS AD5 Y3 gpmc_d6 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS AC5 Y4 gpmc_d7 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS (1) PU100/ PD100 LVCMOS V1 Y1 T1 U2 36 - PIN NAME [4] R1 T1 N1 P2 gpmc_d8 0 IO gpio_44 4 IO safe_mode 7 - gpmc_d9 0 IO gpio_45 4 IO safe_mode 7 - gpmc_d10 0 IO gpio_46 4 IO safe_mode 7 - gpmc_d11 0 IO gpio_47 4 IO safe_mode 7 - TERMINAL DESCRIPTION H H 0 vdds_io Yes 4 H H 0 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS H H 0 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS H H 0 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 BALL TOP [2] U1 P1 P1 L2 M2 M1 J2 K2 PIN NAME [4] MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] gpmc_d12 0 IO H H 0 vdds_io Yes 4 (1) 4 IO PU100/ PD100 LVCMOS gpio_48 safe_mode 7 - gpmc_d13 0 IO H H 0 vdds_io Yes 4 (1) 4 IO PU100/ PD100 LVCMOS gpio_49 safe_mode 7 - gpmc_d14 0 IO H H 0 vdds_io Yes 4 (1) 4 IO PU100/ PD100 LVCMOS gpio_50 safe_mode 7 - gpmc_d15 0 IO H H 0 vdds_io Yes 4 (1) 4 IO PU100/ PD100 LVCMOS gpio_51 safe_mode 7 - AD10 AA9 gpmc_nadv_ale 0 O 0 0 0 vdds_io No 4 (1) NA LVCMOS K2 - gpmc_nbe0_cle 0 O L 0 0 vdds_io Yes 4 (1) LVCMOS gpio_60 4 IO PU100/ PD100 safe_mode 7 - gpmc_nbe1 0 O L L 7 vdds_io Yes 4 (1) 4 IO PU100/ PD100 LVCMOS gpio_61 J1 - safe_mode 7 - AD8 AA8 gpmc_ncs0 0 O 1 1 0 vdds_io No 4 (1) NA LVCMOS AD1 W1 gpmc_ncs1 0 O H 1 0 vdds_io Yes 4 (1) LVCMOS gpio_52 4 IO PU100/ PD100 safe_mode 7 - gpmc_ncs2 0 O H H 7 vdds_io Yes 4 (1) 4 IO PU100/ PD100 LVCMOS gpio_53 safe_mode 7 - gpmc_ncs3 0 O H H 7 vdds_io Yes 4 (1) 1 I PU100/ PD100 LVCMOS sys_ndmareq0 gpio_54 4 IO safe_mode 7 - gpmc_ncs4 0 O H H 7 vdds_io Yes 4 (1) 1 I PU100/ PD100 LVCMOS sys_ndmareq1 mcbsp4_clkx 2 IO gpt9_pwm_evt 3 IO gpio_55 4 IO safe_mode 7 - gpmc_ncs5 0 O H H 7 vdds_io Yes 4 (1) 1 I PU100/ PD100 LVCMOS sys_ndmareq2 mcbsp4_dr 2 I gpt10_pwm_evt 3 IO gpio_56 4 IO safe_mode 7 - gpmc_ncs6 0 O H H 7 vdds_io Yes 4 (1) 1 I PU100/ PD100 LVCMOS sys_ndmareq3 mcbsp4_dx 2 IO gpt11_pwm_evt 3 IO gpio_57 4 IO safe_mode 7 - gpmc_ncs7 0 O H H 7 vdds_io Yes 4 (1) 1 O PU100/ PD100 LVCMOS gpmc_io_dir mcbsp4_fsx 2 IO gpt8_pwm_evt 3 IO gpio_58 4 IO A3 B6 B4 C4 B5 C5 - - - - - - Submit Documentation Feedback TERMINAL DESCRIPTION 37 PRODUCT PREVIEW Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] safe_mode 7 - N2 L2 gpmc_noe 0 M1 K1 gpmc_nwe AC6 Y5 TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] O 1 1 0 vdds_io No 4 (1) NA LVCMOS 0 O 1 1 0 vdds_io No 4 (1) NA LVCMOS gpmc_nwp 0 O L 0 0 vdds_io Yes 4 (1) LVCMOS gpio_62 4 IO PU100/ PD100 PRODUCT PREVIEW safe_mode 7 - Y10 gpmc_wait0 0 I H H 0 vdds_io Yes 4 (1) PU100/ PD100 LVCMOS AC8 Y8 gpmc_wait1 0 I H H 7 vdds_io Yes 4 (1) 4 IO PU100/ PD100 LVCMOS gpio_63 safe_mode 7 - gpmc_wait2 0 I H H 7 vdds_io Yes 4 (1) 4 IO PU100/ PD100 LVCMOS gpio_64 safe_mode 7 - gpmc_wait3 0 I H H 7 vdds_io Yes 4 (1) 1 I PU100/ PD100 LVCMOS sys_ndmareq1 gpio_65 4 IO safe_mode 7 - hsusb0_clk 0 I L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PD100 LVCMOS gpio_120 safe_mode 7 - hsusb0_data0 0 IO L L 7 vdds_io Yes 4 (2) 2 O PU100/ PD100 LVCMOS uart3_tx_irtx gpio_125 4 IO safe_mode 7 - hsusb0_data1 0 IO L L 7 vdds_io Yes 4 (2) 2 I PU100/ PD100 LVCMOS uart3_rx_irrx gpio_130 4 IO safe_mode 7 - hsusb0_data2 0 IO L L 7 vdds_io Yes 4 (2) 2 O PU100/ PD100 LVCMOS uart3_rts_sd gpio_131 4 IO safe_mode 7 - hsusb0_data3 0 IO L L 7 vdds_io Yes 4 (2) 2 IO PU100/ PD100 LVCMOS uart3_cts_rctx gpio_169 4 IO safe_mode 7 - hsusb0_data4 0 IO L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PD100 LVCMOS gpio_188 safe_mode 7 - hsusb0_data5 0 IO L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PD100 LVCMOS gpio_189 safe_mode 7 - hsusb0_data6 0 IO L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PD100 LVCMOS gpio_190 safe_mode 7 - hsusb0_data7 0 IO L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PD100 LVCMOS gpio_191 safe_mode 7 - hsusb0_dir 0 I L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PD100 LVCMOS gpio_122 safe_mode 7 - C6 W19 V20 Y20 V18 W20 W17 Y18 Y19 Y17 V19 38 MODE [5] AC11 B3 (2) PIN NAME [4] - - - - - - - - - - - - The capacity load range is [2 pf to 6 pF]. TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 BALL TOP [2] W18 - U20 MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] hsusb0_nxt 0 I L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PD100 LVCMOS gpio_124 safe_mode 7 - hsusb0_stp 0 O H H 7 vdds_io Yes 4 (2) 4 IO PU100/ PD100 LVCMOS gpio_121 safe_mode 7 - U15 - jtag_ntrst 0 I L L 0 vdds_io Yes NA PU100/ PD100 LVCMOS W13 - jtag_rtck 0 O L 0 0 vdds_io Yes 4 PU100/ PD100 LVCMOS V14 - jtag_tck 0 I L L 0 vdds_io Yes NA PU100/ PD100 LVCMOS U16 - jtag_tdi 0 I H H 0 vdds_io Yes NA PU100/ PD100 LVCMOS Y13 - jtag_tdo 0 O L Z 0 vdds_io Yes 4 PU100/ PD100 LVCMOS V15 - jtag_tms_tmsc 0 IO H H 0 vdds_io Yes 4 PU100/ PD100 LVCMOS N19 - mmc1_clk 0 O L L 7 vdds_mmc1 Yes 8 1 O PU100/ PD100 LVCMOS gpio_120 4 IO safe_mode 7 - mmc1_cmd 0 IO L L 7 vdds_mmc1 Yes 8 1 O PU100/ PD100 LVCMOS gpio_121 4 IO safe_mode 7 - mmc1_dat0 0 IO L L 7 vdds_mmc1 Yes 8 1 IO PU100/ PD100 LVCMOS gpio_122 4 IO safe_mode 7 - mmc1_dat1 0 IO L L 7 vdds_mmc1 Yes 8 1 IO PU100/ PD100 LVCMOS gpio_123 4 IO safe_mode 7 - mmc1_dat2 0 IO L L 7 vdds_mmc1 Yes 8 1 IO PU100/ PD100 LVCMOS gpio_124 4 IO safe_mode 7 - mmc1_dat3 0 IO L L 7 vdds_mmc1 Yes 8 1 IO PU100/ PD100 LVCMOS gpio_125 4 IO safe_mode 7 - mmc1_dat4 0 IO L L 7 vdds_mmc1a No 8 PU/PD (3) LVCMOS - 2 IO gpio_126 4 IO safe_mode 7 - mmc1_dat5 0 IO L L 7 vdds_mmc1a No 8 PU/PD (3) LVCMOS - 2 O gpio_127 4 IO safe_mode 7 - mmc1_dat6 0 IO L L 7 vdds_mmc1a No 8 PU/PD (3) LVCMOS - 2 O gpio_128 4 IO safe_mode 7 - L18 M19 M18 K18 N20 M20 P17 P18 (3) - PIN NAME [4] - - - - - - - - The PU nominal drive strength of this IO cell is equal to 25 µA @ 1.8 V and 41.6 µA @ 3.0 V. The PD nominal drive strength of this IO cell is equal to 1 mA @ 1.8 V and 1.66 mA @ 3.0 V. Submit Documentation Feedback TERMINAL DESCRIPTION 39 PRODUCT PREVIEW Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] P19 - TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] mmc1_dat7 0 IO L L 7 vdds_mmc1a No 8 PU/PD (3) LVCMOS - 2 O gpio_129 4 IO safe_mode 7 - PRODUCT PREVIEW - i2c1_scl 0 IOD H H 0 vdds_io Yes 3 PU100/ PD100 Open Drain J24 - i2c1_sda 0 IOD H H 0 vdds_io Yes 3 PU100/ PD100 Open Drain C2 - i2c2_scl 0 IOD H H 7 vdds_io Yes 3 gpio_168 4 IO PU100/ PD100 LVCMOS Open Drain safe_mode 7 - i2c2_sda 0 IOD gpio_183 4 IO PU100/ PD100 LVCMOS Open Drain safe_mode 7 - i2c3_scl 0 IOD gpio_184 4 IO PU100/ PD100 LVCMOS Open Drain safe_mode 7 - i2c3_sda 0 IOD gpio_185 4 IO PU100/ PD100 LVCMOS Open Drain safe_mode 7 - mcbsp1_clkr 0 IO mcspi4_clk 1 IO - 2 I gpio_156 4 IO safe_mode 7 - mcbsp1_clkx 0 IO mcbsp3_clkx 2 IO gpio_162 4 IO safe_mode 7 - mcbsp1_dr 0 I mcspi4_somi 1 IO mcbsp3_dr 2 I gpio_159 4 IO safe_mode 7 - mcbsp1_dx 0 IO mcspi4_simo 1 IO mcbsp3_dx 2 IO gpio_158 4 IO safe_mode 7 - mcbsp1_fsr 0 IO - 1 I cam_global_reset 2 IO gpio_157 4 IO safe_mode 7 - mcbsp1_fsx 0 IO mcspi4_cs0 1 IO mcbsp3_fsx 2 IO gpio_161 4 IO safe_mode 7 - mcbsp2_clkx 0 IO gpio_117 4 IO safe_mode 7 - AB4 AC4 U19 T17 T20 U17 V17 P20 R18 40 MODE [5] J25 C1 (4) PIN NAME [4] - - - - - - - - - - 4 4 H H 7 vdds_io Yes 3 4 4 H H 7 vdds_io Yes 3 4 4 H H 7 vdds_io Yes 3 4 4 L L 7 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS L L 7 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS L L 7 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS L L 7 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS L L 7 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS L L 7 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS L L 7 vdds_io Yes 4 (4) PU100/ PD100 LVCMOS The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in the above table. TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 BALL TOP [2] T18 - R19 U18 P9 R7 R9 P8 P7 W7 V8 W8 U8 - - - - - - - - - - - PIN NAME [4] MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] mcbsp2_dr 0 I L L 7 vdds_io Yes 4 (4) 4 IO PU100/ PD100 LVCMOS gpio_118 safe_mode 7 - mcbsp2_dx 0 IO L L 7 vdds_io Yes 4 (4) 4 IO PU100/ PD100 LVCMOS gpio_119 safe_mode 7 - mcbsp2_fsx 0 IO L L 7 vdds_io Yes 4 (4) 4 IO PU100/ PD100 LVCMOS gpio_116 safe_mode 7 - mcspi1_clk 0 IO L L 7 vdds_io Yes 4 (4) 1 IO PU100/ PD100 LVCMOS mmc2_dat4 gpio_171 4 IO safe_mode 7 - mcspi1_cs0 0 IO H H 7 vdds_io Yes 4 (4) 1 IO PU100/ PD100 LVCMOS mmc2_dat7 gpio_174 4 IO safe_mode 7 - mcspi1_cs2 0 O H H 7 vdds_io Yes 4 (4) 3 O PU100/ PD100 LVCMOS mmc3_clk gpio_176 4 IO safe_mode 7 - mcspi1_simo 0 IO L L 7 vdds_io Yes 4 (4) 1 IO PU100/ PD100 LVCMOS mmc2_dat5 gpio_172 4 IO safe_mode 7 - mcspi1_somi 0 IO L L 7 vdds_io Yes 4 (4) 1 IO PU100/ PD100 LVCMOS mmc2_dat6 gpio_173 4 IO safe_mode 7 - mcspi2_clk 0 IO L L 7 vdds_io Yes 4 (2) 2 IO PU100/ PD100 LVCMOS hsusb2_tll_data7 hsusb2_data7 3 O gpio_178 4 IO safe_mode 7 - mcspi2_cs0 0 IO H H 7 vdds_io Yes 4 (2) 1 IO PU100/ PD100 LVCMOS gpt11_pwm_evt hsusb2_tll_data6 2 IO hsusb2_data6 3 O gpio_181 4 IO safe_mode 7 - mcspi2_simo 0 IO L L 7 vdds_io Yes 4 (2) 1 IO PU100/ PD100 LVCMOS gpt9_pwm_evt hsusb2_tll_data4 2 IO hsusb2_data4 3 I gpio_179 4 IO safe_mode 7 - mcspi2_somi 0 IO L L 7 vdds_io Yes 4 (2) 1 IO PU100/ PD100 LVCMOS gpt10_pwm_evt hsusb2_tll_data5 2 IO hsusb2_data5 3 O gpio_180 4 IO safe_mode 7 - Submit Documentation Feedback TERMINAL DESCRIPTION 41 PRODUCT PREVIEW Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] W10 - R10 T10 PRODUCT PREVIEW T9 U10 U9 V10 R2 H3 L4 Y24 AA24 AD21 42 - - - - - - - - - - - - PIN NAME [4] MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] mmc2_clk 0 O L L 7 vdds_io Yes 4 (2) 1 IO PU100/ PD100 LVCMOS mcspi3_clk gpio_130 4 IO safe_mode 7 - mmc2_cmd 0 IO H H 7 vdds_io Yes 4 (2) 1 IO PU100/ PD100 LVCMOS mcspi3_simo gpio_131 4 IO safe_mode 7 - mmc2_dat0 0 IO H H 7 vdds_io Yes 4 (2) 1 IO PU100/ PD100 LVCMOS mcspi3_somi gpio_132 4 IO safe_mode 7 - mmc2_dat1 0 IO H H 7 vdds_io Yes 4 (2) 4 IO PU100/ PD100 LVCMOS gpio_133 safe_mode 7 - mmc2_dat2 0 IO H H 7 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS mcspi3_cs1 gpio_134 4 IO safe_mode 7 - mmc2_dat3 0 IO H H 7 vdds_io Yes 4 (2) 1 IO PU100/ PD100 LVCMOS mcspi3_cs0 gpio_135 4 IO safe_mode 7 - mmc2_dat4 0 IO L L 7 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS mmc2_dir_dat0 mmc3_dat0 3 IO gpio_136 4 IO safe_mode 7 - uart1_rts 0 O L L 7 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS gpio_149 4 IO safe_mode 7 - uart1_rx 0 I L L 7 vdds_io Yes 4 (2) 2 IO PU100/ PD100 LVCMOS mcbsp1_clkr mcspi4_clk 3 IO gpio_151 4 IO safe_mode 7 - uart1_tx 0 O L L 7 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS gpio_148 4 IO safe_mode 7 - uart2_cts 0 I H H 7 vdds_io Yes 4 1 IO PU100/ PD100 LVCMOS mcbsp3_dx gpt9_pwm_evt 2 IO gpio_144 4 IO safe_mode 7 - uart2_rts 0 O H H 7 vdds_io Yes 4 1 I PU100/ PD100 LVCMOS mcbsp3_dr gpt10_pwm_evt 2 IO gpio_145 4 IO safe_mode 7 - uart2_rx 0 I H H 7 vdds_io Yes 4 1 IO PU100/ PD100 LVCMOS mcbsp3_fsx TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 AD22 F23 F24 H24 G24 J23 AD15 W16 BALL TOP [2] - - - - - - - - PIN NAME [4] MODE [5] TYPE [6] gpt8_pwm_evt 2 IO gpio_147 4 IO safe_mode 7 - uart2_tx 0 O mcbsp3_clkx 1 IO gpt11_pwm_evt 2 IO gpio_146 4 IO safe_mode 7 - uart3_cts_rctx 0 IO gpio_163 4 IO safe_mode 7 - uart3_rts_sd 0 O gpio_164 4 IO safe_mode 7 - uart3_rx_irrx 0 I gpio_165 4 IO safe_mode 7 - uart3_tx_irtx 0 O gpio_166 4 IO safe_mode 7 - hdq_sio 0 IOD sys_altclk 1 I i2c2_sccbe 2 O i2c3_sccbe 3 O gpio_170 4 IO safe_mode 7 - i2c4_scl 0 IOD sys_nvmode1 1 O safe_mode 7 - i2c4_sda 0 IOD sys_nvmode2 1 O BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] H H 7 vdds_io Yes 4 PU100/ PD100 LVCMOS H H 7 vdds_io Yes 4 PU100/ PD100 LVCMOS H H 7 vdds_io Yes 4 PU100/ PD100 LVCMOS H H 7 vdds_io Yes 4 PU100/ PD100 LVCMOS H H 7 vdds_io Yes 4 PU100/ PD100 LVCMOS H H 7 vdds_io Yes 4 PU100/ PD100 LVCMOS Open Drain H H 0 vdds_io Yes 3 PU100/ PD100 LVCMOS Open Drain PU100/ PD100 LVCMOS Open Drain 4 4 H H 0 vdds_io Yes 3 4 safe_mode 7 - K4 - sad2d_clk26mi 0 O L 0 (PD) 0 vdds_io Yes 4 PU100/ PD100 LVCMOS F3 - sys_boot0 0 I Z Z 0 vdds_io Yes 4 4 IO PU100/ PD100 LVCMOS gpio_2 safe_mode 7 - sys_boot1 0 I Z Z 0 vdds_io Yes 4 4 IO PU100/ PD100 LVCMOS gpio_3 safe_mode 7 - sys_boot2 0 I Z Z 0 vdds_io Yes 4 4 IO PU100/ PD100 LVCMOS gpio_4 safe_mode 7 - sys_boot3 0 I Z Z 0 vdds_io Yes 4 4 IO PU100/ PD100 LVCMOS gpio_5 safe_mode 7 - sys_boot4 0 I Z Z 0 vdds_io Yes 4 1 O PU100/ PD100 LVCMOS mmc2_dir_dat2 gpio_6 4 IO safe_mode 7 - sys_boot5 0 I Z Z 0 vdds_io Yes 4 1 O PU100/ PD100 LVCMOS mmc2_dir_dat3 gpio_7 4 IO D3 C3 E3 E4 G3 - - - - - Submit Documentation Feedback 4 TERMINAL DESCRIPTION 43 PRODUCT PREVIEW Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] D4 - AE14 W11 PRODUCT PREVIEW W15 V16 - - - MODE [5] TYPE [6] safe_mode 7 - sys_boot6 0 I gpio_8 4 IO safe_mode 7 - sys_clkout1 0 O gpio_10 4 IO safe_mode 7 - sys_clkout2 0 O gpio_186 4 IO safe_mode 7 - sys_clkreq 0 IO gpio_1 4 IO safe_mode 7 - sys_nirq 0 I gpio_0 4 IO - BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] Z Z 0 vdds_io Yes 4 PU100/ PD100 LVCMOS L L 7 vdds_io Yes 4 PU100/ PD100 LVCMOS L L 7 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS 0 1 0 vdds_io Yes 4 PU100/ PD100 LVCMOS H H 7 vdds_io Yes 4 PU100/ PD100 LVCMOS safe_mode 7 V13 - sys_nrespwron 0 I Z I NA vdds_io Yes NA NA LVCMOS AD7 AA5 sys_nreswarm 0 IOD 0 1 (PU) 0 vdds_io Yes 4 gpio_30 4 IO PU100/ PD100 LVCMOS Open Drain safe_mode 7 - sys_off_mode 0 O 0 L 7 vdds_io Yes 4 4 IO PU100/ PD100 LVCMOS gpio_9 - V12 - safe_mode 7 AF19 - sys_xtalin 0 I Z I NA vdds_io Yes NA NA LVCMOS AF20 - sys_xtalout 0 O Z O NA vdds_io Yes NA NA LVCMOS B1 - sys_ipmcsws 0 AI Z NA NA vdds_io No NA NA Analog A2 - sys_opmcsws 0 AO 0 NA NA vdds_io No NA NA Analog W26 - tv_out1 0 AO Z 0 0 vdda_dac No 8 NA 10-bit DAC V26 - tv_out2 0 AO Z 0 0 vdda_dac No 8 NA 10-bit DAC W25 - tv_vfb1 0 O Z NA 0 vdda_dac No 2 NA 10-bit DAC U24 - tv_vfb2 0 O Z NA 0 vdda_dac No 2 NA 10-bit DAC V23 - tv_vref 0 I Z NA 0 vdda_dac No NA NA 10-bit DAC AE20 - sys_32k 0 I Z I NA vdds_io Yes NA NA LVCMOS A24 - cam_d2 0 I L L 7 vdds_io Yes 4 (2) LVCMOS - 1 I PU100/ PD100 gpio_101 4 IO hw_dbg4 5 O safe_mode 7 - cam_d3 0 I L L 7 vdds_io Yes 4 (2) 1 I PU100/ PD100 LVCMOS gpio_102 4 IO hw_dbg5 5 O safe_mode 7 - cam_d4 0 I L L 7 vdds_io Yes 4 (2) 1 I PU100/ PD100 LVCMOS gpio_103 4 IO hw_dbg6 5 O safe_mode 7 - cam_d5 0 I L L 7 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS gpio_104 4 IO hw_dbg7 5 O safe_mode 7 - B24 D24 C24 44 - PIN NAME [4] - - - TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 BALL TOP [2] D25 - E26 B23 C23 C26 D26 C25 E25 P25 P26 N25 N26 D23 - - - - - - - - - - - - PIN NAME [4] MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] cam_d10 0 I L L 7 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS gpio_109 4 IO hw_dbg8 5 O safe_mode 7 - cam_d11 0 I L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PD100 LVCMOS gpio_110 hw_dbg9 5 O safe_mode 7 - cam_fld 0 IO L L 7 vdds_io Yes 4 (2) 2 IO PU100/ PD100 LVCMOS cam_global_reset gpio_98 4 IO hw_dbg3 5 O safe_mode 7 - cam_hs 0 IO L L 7 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS gpio_94 4 IO hw_dbg0 5 O safe_mode 7 - cam_pclk 0 I L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PD100 LVCMOS gpio_97 hw_dbg2 5 O safe_mode 7 - cam_strobe 0 O L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PD100 LVCMOS gpio_126 hw_dbg11 5 O safe_mode 7 - cam_xclka 0 O L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PD100 LVCMOS gpio_96 safe_mode 7 - cam_xclkb 0 O L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PD100 LVCMOS gpio_111 safe_mode 7 - cam_d6 0 I L L 7 vdds_csib NA 4 4 IO PU100/ PD100 SubLVDS gpio_105 safe_mode 7 - cam_d7 0 I L L 7 vdds_csib NA 4 4 IO PU100/ PD100 SubLVDS gpio_106 safe_mode 7 - cam_d8 0 I L L 7 vdds_csib NA 4 4 IO PU100/ PD100 SubLVDS gpio_107 safe_mode 7 - cam_d9 0 I L L 7 vdds_csib NA 4 4 IO PU100/ PD100 SubLVDS gpio_108 safe_mode 7 - cam_vs 0 IO L L 7 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS gpio_95 4 IO hw_dbg1 5 O safe_mode 7 - Submit Documentation Feedback TERMINAL DESCRIPTION 45 PRODUCT PREVIEW Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] A23 - F26 G26 PRODUCT PREVIEW H25 H26 J26 L25 L26 M24 M26 N24 46 - - - - - - - - - - PIN NAME [4] MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] cam_wen 0 I L L 7 vdds_io Yes 4 (2) 2 O PU100/ PD100 LVCMOS cam_shutter gpio_167 4 IO hw_dbg10 5 O safe_mode 7 - dss_acbias 0 O L L 7 vdds_io Yes 8 4 IO PU100/ PD100 LVCMOS gpio_69 safe_mode 7 - dss_data6 0 IO L L 7 vdds_io Yes 8 2 O PU100/ PD100 LVCMOS uart1_tx gpio_76 4 IO hw_dbg14 5 O safe_mode 7 - dss_data7 0 IO L L 7 vdds_io Yes 8 2 I PU100/ PD100 LVCMOS uart1_rx gpio_77 4 IO hw_dbg15 5 O safe_mode 7 - dss_data8 0 IO L L 7 vdds_io Yes 8 4 IO PU100/ PD100 LVCMOS gpio_78 hw_dbg16 5 O safe_mode 7 - dss_data9 0 IO L L 7 vdds_io Yes 8 4 IO PU100/ PD100 LVCMOS gpio_79 hw_dbg17 5 O safe_mode 7 - dss_data16 0 IO L L 7 vdds_io Yes 8 4 IO PU100/ PD100 LVCMOS gpio_86 safe_mode 7 - dss_data17 0 IO L L 7 vdds_io Yes 8 4 IO PU100/ PD100 LVCMOS gpio_87 safe_mode 7 - dss_data18 0 IO L L 7 vdds_io Yes 8 1 O PU100/ PD100 LVCMOS mcspi3_clk 2 IO dss_data0 3 IO gpio_88 4 IO safe_mode 7 - dss_data19 0 IO L L 7 vdds_io Yes 8 1 O PU100/ PD100 LVCMOS mcspi3_simo 2 IO dss_data1 3 IO gpio_89 4 IO safe_mode 7 - dss_data21 0 O L L 7 vdds_io Yes 8 1 O PU100/ PD100 LVCMOS mcspi3_cs0 2 IO dss_data3 3 IO gpio_91 4 IO safe_mode 7 - TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 BALL TOP [2] K24 - M25 R8 T8 V9 T19 AB2 AB3 AC3 - - - - - - - - PIN NAME [4] MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] H H 7 vdds_io Yes 4 PU100/ PD100 LVCMOS H H 7 vdds_io Yes 4 PU100/ PD100 LVCMOS H H 7 vdds_io Yes 4 (4) PU100/ PD100 LVCMOS H H 7 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS L L 7 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS L L 7 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS H H 4 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS H H 4 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS H H 4 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS dss_hsync 0 O gpio_67 4 IO hw_dbg13 5 O safe_mode 7 - dss_vsync 0 O gpio_68 4 IO safe_mode 7 - mcspi1_cs1 0 O - 1 I mmc3_cmd 3 IO gpio_175 4 IO safe_mode 7 - mcspi1_cs3 0 O hsusb2_tll_data2 2 IO hsusb2_data2 3 IO gpio_177 4 IO mm2_txdat 5 IO safe_mode 7 - mcspi2_cs1 0 O gpt8_pwm_evt 1 IO hsusb2_tll_data3 2 IO hsusb2_data3 3 IO gpio_182 4 IO mm2_txen_n 5 IO safe_mode 7 - mcbsp_clks 0 I cam_shutter 2 O gpio_160 4 IO uart1_cts 5 I safe_mode 7 - etk_clk 0 O mcbsp5_clkx 1 IO mmc3_clk 2 O hsusb1_stp 3 O gpio_12 4 IO mm1_rxdp 5 IO hsusb1_tll_stp 6 I hw_dbg0 7 O etk_ctl 0 O mmc3_cmd 2 IO hsusb1_clk 3 O gpio_13 4 IO hsusb1_tll_clk 6 O hw_dbg1 7 O etk_d0 0 O mcspi3_simo 1 IO mmc3_dat4 2 IO hsusb1_data0 3 IO gpio_14 4 IO mm1_rxrcv 5 IO hsusb1_tll_data0 6 IO hw_dbg2 7 O Submit Documentation Feedback TERMINAL DESCRIPTION 47 PRODUCT PREVIEW Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] AD4 - AD3 PRODUCT PREVIEW AA3 Y3 AB1 AE3 AD2 AA4 48 - - - - - - - PIN NAME [4] MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] etk_d1 0 O H H 4 vdds_io Yes 4 (2) 1 IO PU100/ PD100 LVCMOS mcspi3_somi hsusb1_data1 3 IO gpio_15 4 IO mm1_txse0 5 IO hsusb1_tll_data1 6 IO hw_dbg3 7 O etk_d2 0 O H H 4 vdds_io Yes 4 (2) 1 IO PU100/ PD100 LVCMOS mcspi3_cs0 hsusb1_data2 3 IO gpio_16 4 IO mm1_txdat 5 IO hsusb1_tll_data2 6 IO hw_dbg4 7 O etk_d3 0 O H H 4 vdds_io Yes 4 (2) 1 IO PU100/ PD100 LVCMOS mcspi3_clk mmc3_dat3 2 IO hsusb1_data7 3 IO gpio_17 4 IO hsusb1_tll_data7 6 IO hw_dbg5 7 O etk_d4 0 O L L 4 vdds_io Yes 4 (2) 1 I PU100/ PD100 LVCMOS mcbsp5_dr mmc3_dat0 2 IO hsusb1_data4 3 IO gpio_18 4 IO hsusb1_tll_data4 6 IO hw_dbg6 7 O etk_d5 0 O L L 4 vdds_io Yes 4 (2) 1 IO PU100/ PD100 LVCMOS mcbsp5_fsx mmc3_dat1 2 IO hsusb1_data5 3 IO gpio_19 4 IO hsusb1_tll_data5 6 IO hw_dbg7 7 O etk_d6 0 O L L 4 vdds_io Yes 4 (2) 1 IO PU100/ PD100 LVCMOS mcbsp5_dx mmc3_dat2 2 IO hsusb1_data6 3 IO gpio_20 4 IO hsusb1_tll_data6 6 IO hw_dbg8 7 O etk_d7 0 O L L 4 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS mcspi3_cs1 mmc3_dat7 2 IO hsusb1_data3 3 IO gpio_21 4 IO mm1_txen_n 5 IO hsusb1_tll_data3 6 IO hw_dbg9 7 O etk_d8 0 O L L 4 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS sys_drm_msecure mmc3_dat6 2 IO TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 V2 AE4 AF6 AE6 AF7 AF9 AE9 Y15 Y14 BALL TOP [2] - - - - - - - - - PIN NAME [4] MODE [5] TYPE [6] hsusb1_dir 3 I gpio_22 4 IO hsusb1_tll_dir 6 O hw_dbg10 7 O etk_d9 0 O sys_secure_indicator 1 O mmc3_dat5 2 IO hsusb1_nxt 3 I gpio_23 4 IO mm1_rxdm 5 IO hsusb1_tll_nxt 6 O hw_dbg11 7 O etk_d10 0 O uart1_rx 2 I hsusb2_clk 3 O gpio_24 4 IO hsusb2_tll_clk 6 O hw_dbg12 7 O etk_d11 0 O hsusb2_stp 3 O gpio_25 4 IO mm2_rxdp 5 IO hsusb2_tll_stp 6 I hw_dbg13 7 O etk_d12 0 O hsusb2_dir 3 I gpio_26 4 IO hsusb2_tll_dir 6 O hw_dbg14 7 O etk_d13 0 O hsusb2_nxt 3 I gpio_27 4 IO mm2_rxdm 5 IO hsusb2_tll_nxt 6 O hw_dbg15 7 O etk_d14 0 O hsusb2_data0 3 IO gpio_28 4 IO mm2_rxrcv 5 IO hsusb2_tll_data0 6 IO hw_dbg16 7 O etk_d15 0 O hsusb2_data1 3 IO gpio_29 4 IO mm2_txse0 5 IO hsusb2_tll_data1 6 IO hw_dbg17 7 O jtag_emu0 0 IO gpio_11 4 IO safe_mode 7 - jtag_emu1 0 IO gpio_31 4 IO safe_mode 7 - Submit Documentation Feedback BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] L L 4 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS L L 4 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS L L 4 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS L L 4 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS L L 4 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS L L 4 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS L L 4 vdds_io Yes 4 (2) PU100/ PD100 LVCMOS H H 0 vdds_io Yes 4 PU100/ PD100 LVCMOS H H 0 vdds_io Yes 4 PU100/ PD100 LVCMOS TERMINAL DESCRIPTION 49 PRODUCT PREVIEW Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] U3 - N3 PRODUCT PREVIEW P3 W3 V3 U4 R3 T3 M3 - - - - - - - - PIN NAME [4] MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] mcbsp3_clkx (5) 0 IO L L 7 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS uart2_tx gpio_142 4 IO hsusb3_tll_data6 5 IO safe_mode 7 - mcbsp3_dr (5) 0 I L L 7 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS uart2_rts gpio_141 4 IO hsusb3_tll_data5 5 IO safe_mode 7 - mcbsp3_dx (5) 0 IO L L 7 vdds_io Yes 4 (2) 1 I PU100/ PD100 LVCMOS uart2_cts gpio_140 4 IO hsusb3_tll_data4 5 IO safe_mode 7 - mcbsp3_fsx (5) 0 IO L L 7 vdds_io Yes 4 (2) 1 I PU100/ PD100 LVCMOS uart2_rx gpio_143 4 IO hsusb3_tll_data7 5 IO safe_mode 7 - mcbsp4_clkx (5) 0 IO L L 7 vdds_io Yes 4 (2) 1 I PU100/ PD100 LVCMOS gpio_152 4 IO hsusb3_tll_data1 5 IO mm3_txse0 6 IO safe_mode 7 - mcbsp4_dr (5) 0 I L L 7 vdds_io Yes 4 (2) 1 I PU100/ PD100 LVCMOS gpio_153 4 IO hsusb3_tll_data0 5 IO mm3_rxrcv 6 IO safe_mode 7 - mcbsp4_dx (5) 0 IO L L 7 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS gpio_154 4 IO hsusb3_tll_data2 5 IO mm3_txdat 6 IO safe_mode 7 - mcbsp4_fsx (5) 0 IO L L 7 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS gpio_155 4 IO hsusb3_tll_data3 5 IO mm3_txen_n 6 IO safe_mode 7 - mmc2_dat5 (5) 0 IO L L 7 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS mmc2_dir_dat1 cam_global_reset 2 IO mmc3_dat1 3 IO gpio_137 4 IO hsusb3_tll_stp 5 I mm3_rxdp 6 IO safe_mode 7 - (5) This functionality is not supported. 50 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 BALL TOP [2] L3 - K3 W2 - - PIN NAME [4] MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] mmc2_dat6 (5) 0 IO L L 7 vdds_io Yes 4 (2) 1 O PU100/ PD100 LVCMOS mmc2_dir_cmd cam_shutter 2 O mmc3_dat2 3 IO gpio_138 4 IO hsusb3_tll_dir 5 O safe_mode 7 - mmc2_dat7 (5) 0 IO L L 7 vdds_io Yes 4 (2) 1 I PU100/ PD100 LVCMOS mmc2_clkin mmc3_dat3 3 IO gpio_139 4 IO hsusb3_tll_nxt 5 IO mm3_rxdm 6 IO safe_mode 7 - uart1_cts (5) 0 I L L 7 vdds_io Yes 4 (2) 1 I PU100/ PD100 LVCMOS gpio_150 4 IO hsusb3_tll_clk 5 O safe_mode 7 - Submit Documentation Feedback TERMINAL DESCRIPTION 51 PRODUCT PREVIEW Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-3. Ball Characteristics (CUS Pkg.) (1) PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] D7 sdrc_d0 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C5 sdrc_d1 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C6 sdrc_d2 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B5 sdrc_d3 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D9 sdrc_d4 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D10 sdrc_d5 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C7 sdrc_d6 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B7 sdrc_d7 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B11 sdrc_d8 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C12 sdrc_d9 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B12 sdrc_d10 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D13 sdrc_d11 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C13 sdrc_d12 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B14 sdrc_d13 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A14 sdrc_d14 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B15 sdrc_d15 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C9 sdrc_d16 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS E12 sdrc_d17 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B8 sdrc_d18 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B9 sdrc_d19 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C10 sdrc_d20 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B10 sdrc_d21 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D12 sdrc_d22 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS E13 sdrc_d23 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS E15 sdrc_d24 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D15 sdrc_d25 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C15 sdrc_d26 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B16 sdrc_d27 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C16 sdrc_d28 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D16 sdrc_d29 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B17 sdrc_d30 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B18 sdrc_d31 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C18 sdrc_ba0 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D18 sdrc_ba1 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS A4 sdrc_a0 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS B4 sdrc_a1 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D6 sdrc_a2 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS B3 sdrc_a3 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS B2 sdrc_a4 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C3 sdrc_a5 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS E3 sdrc_a6 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS F6 sdrc_a7 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS E10 sdrc_a8 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS E9 sdrc_a9 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS E7 sdrc_a10 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS G6 sdrc_a11 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS G7 sdrc_a12 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS F7 sdrc_a13 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS F9 sdrc_a14 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS A19 sdrc_ncs0 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS B19 sdrc_ncs1 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS A10 sdrc_clk 0 IO L 0 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A11 sdrc_nclk 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS PRODUCT PREVIEW BALL BOTTOM [1] (1) 52 NA in this table stands for Not Applicable. TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 B20 C20 PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] O H 1 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS O H 1 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS sdrc_cke0 0 safe_mode 7 sdrc_cke1 0 safe_mode 7 D19 sdrc_nras 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS C19 sdrc_ncas 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS A20 sdrc_nwe 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS B6 sdrc_dm0 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS B13 sdrc_dm1 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS A7 sdrc_dm2 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS A16 sdrc_dm3 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS A5 sdrc_dqs0 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A13 sdrc_dqs1 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A8 sdrc_dqs2 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A17 sdrc_dqs3 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS K4 gpmc_a1 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_34 4 IO safe_mode 7 gpmc_a2 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_35 4 IO safe_mode 7 gpmc_a3 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_36 4 IO safe_mode 7 gpmc_a4 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_37 4 IO safe_mode 7 gpmc_a5 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_38 4 IO safe_mode 7 gpmc_a6 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_39 4 IO safe_mode 7 gpmc_a7 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_40 4 IO safe_mode 7 gpmc_a8 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_41 4 IO safe_mode 7 gpmc_a9 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS sys_ ndmareq2 1 I IO H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS K3 K2 J4 J3 J2 J1 H1 H2 G2 gpio_42 4 safe_mode 7 gpmc_a10 0 O sys_ ndmareq3 1 I IO gpio_43 4 safe_mode 7 L2 gpmc_d0 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS M1 gpmc_d1 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS M2 gpmc_d2 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS N2 gpmc_d3 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS M3 gpmc_d4 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS P1 gpmc_d5 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS P2 gpmc_d6 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW Table 2-3. Ball Characteristics (CUS Pkg.) (continued) BALL BOTTOM [1] 53 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-3. Ball Characteristics (CUS Pkg.) (continued) BALL BOTTOM [1] PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] R1 gpmc_d7 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS R2 gpmc_d8 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_44 4 IO safe_mode 7 gpmc_d9 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_45 4 IO safe_mode 7 gpmc_d10 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_46 4 IO safe_mode 7 gpmc_d11 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_47 4 IO safe_mode 7 gpmc_d12 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_48 4 IO safe_mode 7 gpmc_d13 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_49 4 IO safe_mode 7 gpmc_d14 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_50 4 IO safe_mode 7 gpmc_d15 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_51 4 IO T2 U1 PRODUCT PREVIEW R3 T3 U2 V1 V2 safe_mode 7 E2 gpmc_ncs0 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS D2 gpmc_ncs3 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS sys_ ndmareq0 1 I IO H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS F4 G5 F3 G4 54 gpio_54 4 safe_mode 7 gpmc_ncs4 0 O sys_ ndmareq1 1 I mcbsp4_ clkx 2 IO gpt9_pwm_evt 3 IO gpio_55 4 IO safe_mode 7 gpmc_ncs5 0 O sys_ ndmareq2 1 I mcbsp4_dr 2 I gpt10_pwm_evt 3 IO IO gpio_56 4 safe_mode 7 gpmc_ncs6 0 O sys_ ndmareq3 1 I mcbsp4_dx 2 IO gpt11_pwm_evt 3 IO gpio_57 4 IO safe_mode 7 gpmc_ncs7 0 O gpmc_io_dir 1 O mcbsp4_fsx 2 IO gpt8_pwm_evt 3 IO gpio_58 4 IO safe_mode 7 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] W2 gpmc_clk gpio_59 0 O L 0 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS 4 IO safe_mode 7 F1 gpmc_nadv_ale 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS F2 gpmc_noe 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS G3 gpmc_nwe 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS K5 gpmc_nbe0_cle 0 O L 0 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_60 4 IO L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS L 0 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS L1 safe_mode 7 gpmc_nbe1 0 O gpio_61 4 IO safe_mode E1 PRODUCT PREVIEW Table 2-3. Ball Characteristics (CUS Pkg.) (continued) BALL BOTTOM [1] 7 gpmc_nwp 0 O gpio_62 4 IO safe_mode 7 C1 gpmc_wait0 0 I H H 0 VDDS_ MEM Yes NA PU/ PD LVCMOS C2 gpmc_wait3 0 I H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS sys_ ndmareq1 1 I IO H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS No 4 PU/ PD LVDS/ CMOS L L 7 VDDS No 4 PU/ PD LVDS/ CMOS L L 7 VDDS No 4 PU/ PD LVDS/ CMOS L L 7 VDDS No 4 PU/ PD LVDS/ CMOS L L 7 VDDS No 4 PU/ PD LVDS/ CMOS L L 7 VDDS No 4 PU/ PD LVDS/ CMOS G22 E22 F22 J21 AC19 AB19 AD20 AC20 AD21 AC21 gpio_65 4 safe_mode 7 dss_pclk 0 O gpio_66 4 IO safe_mode 7 dss_hsync 0 O gpio_67 4 IO safe_mode 7 dss_vsync 0 O gpio_68 4 IO safe_mode 7 dss_acbias 0 O gpio_69 4 IO safe_mode 7 dss_data0 0 IO uart1_cts 2 I IO gpio_70 4 safe_mode 7 dss_data1 0 IO uart1_rts 2 O IO gpio_71 4 safe_mode 7 dss_data2 0 IO gpio_72 4 IO safe_mode 7 dss_data3 0 IO gpio_73 4 IO safe_mode 7 dss_data4 0 IO uart3_rx_ irrx 2 I IO gpio_74 4 safe_mode 7 dss_data5 0 IO uart3_tx_ irtx 2 O gpio_75 4 IO safe_mode 7 Submit Documentation Feedback TERMINAL DESCRIPTION 55 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-3. Ball Characteristics (CUS Pkg.) (continued) BALL BOTTOM [1] PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] D24 dss_data6 0 IO L L 7 VDDS Yes 8 PU/ PD LVCMOS uart1_tx 2 O IO L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS E23 E24 PRODUCT PREVIEW F23 AC22 AC23 AB22 Y22 W22 V22 J22 G23 G24 H23 D23 K22 56 gpio_76 4 safe_mode 7 dss_data7 0 IO uart1_rx 2 I IO gpio_77 4 safe_mode 7 dss_data8 0 IO gpio_78 4 IO safe_mode 7 dss_data9 0 IO gpio_79 4 IO safe_mode 7 dss_data10 0 IO gpio_80 4 IO safe_mode 7 dss_data11 0 IO gpio_81 4 IO safe_mode 7 dss_data12 0 IO gpio_82 4 IO safe_mode 7 dss_data13 0 IO gpio_83 4 IO safe_mode 7 dss_data14 0 IO gpio_84 4 IO safe_mode 7 dss_data15 0 IO gpio_85 4 IO safe_mode 7 dss_data16 0 IO gpio_86 4 IO safe_mode 7 dss_data17 0 IO gpio_87 4 IO safe_mode 7 dss_data18 0 IO mcspi3_clk 2 IO dss_data0 3 IO gpio_88 4 IO safe_mode 7 dss_data19 0 IO mcspi3_ simo 2 IO dss_data1 3 IO gpio_89 4 IO safe_mode 7 dss_data20 0 O mcspi3_ somi 2 IO dss_data2 3 IO gpio_90 4 IO safe_mode 7 dss_data21 0 TERMINAL DESCRIPTION O Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-3. Ball Characteristics (CUS Pkg.) (continued) V21 W21 PIN NAME [3] MODE [4] TYPE [5] mcspi3_cs0 2 IO dss_data3 3 IO gpio_91 4 IO safe_mode 7 dss_data22 0 O mcspi3_cs1 2 O dss_data4 3 IO gpio_92 4 IO safe_mode 7 dss_data23 0 O dss_data5 3 IO IO BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS L L 7 VDDS NA 4 PU/ PD LVDS/ CMOS PRODUCT PREVIEW BALL BOTTOM [1] gpio_93 4 safe_mode 7 AA23 tv_out2 0 O Z 0 0 VDDADAC 8 NA 10-bit DAC AB24 tv_out1 0 O Z 0 0 VDDADAC 8 NA 10-bit DAC AB23 tv_vfb1 0 O Z NA 0 VDDADAC NA 10-bit DAC Y23 tv_vfb2 0 O Z NA 0 VDDADAC NA 10-bit DAC Y24 tv_vref 0 I Z NA 0 VDDADAC NA 10-bit DAC A22 cam_hs 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS gpio_94 4 IO safe_mode 7 cam_vs 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS gpio_95 4 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PD LVDS/ CMOS L L 7 VDDS Yes 4 PD LVDS/ CMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS NA 4 PD LVDS/ CMOS E18 B22 J19 H24 AB18 AC18 G19 F19 G20 B21 L24 safe_mode 7 cam_ xclka 0 O gpio_96 4 IO safe_mode 7 cam_pclk 0 I gpio_97 4 IO safe_mode 7 cam_fld 0 IO cam_global_reset 2 IO IO gpio_98 4 safe_mode 7 cam_d0 0 I gpio_99 4 I safe_mode 7 cam_d1 0 I gpio_100 4 I safe_mode 7 cam_d2 0 I gpio_101 4 IO safe_mode 7 cam_d3 0 I gpio_102 4 IO safe_mode 7 cam_d4 0 I gpio_103 4 IO safe_mode 7 cam_d5 0 I gpio_104 4 IO safe_mode 7 cam_d6 0 I gpio_105 4 IO Submit Documentation Feedback TERMINAL DESCRIPTION 57 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-3. Ball Characteristics (CUS Pkg.) (continued) BALL BOTTOM [1] K24 J23 K23 PRODUCT PREVIEW F21 G21 C22 F18 J20 V20 T21 V19 R20 M23 L23 M22 M21 M20 (2) 58 PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] safe_mode 7 cam_d7 gpio_106 0 I L L 7 VDDS NA 4 PD LVDS/ CMOS 4 IO safe_mode 7 cam_d8 0 I gpio_107 4 IO L L 7 VDDS NA 4 PD LVDS/ CMOS safe_mode 7 cam_d9 0 I gpio_108 4 IO L L 7 VDDS NA 4 PD LVDS/ CMOS safe_mode 7 cam_d10 0 I gpio_109 4 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS safe_mode 7 cam_d11 0 I gpio_110 4 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS PGM L 7 VDDS Yes 4 (2) PU/ PD LVCMOS PGM L 7 VDDS Yes 4 (2) PU/ PD LVCMOS PGM L 7 VDDS Yes 4 (2) PU/ PD LVCMOS PGM L 7 VDDS Yes 4 (2) PU/ PD LVCMOS L L 7 MMC1_ VDDS Yes 8 PU/ PD LVCMOS L L 7 MMC1_ VDDS Yes 8 PU/ PD LVCMOS L L 7 MMC1_ VDDS Yes 8 PU/ PD LVCMOS L L 7 MMC1_ VDDS Yes 8 PU/ PD LVCMOS L L 7 MMC1_ VDDS Yes 8 PU/ PD LVCMOS safe_mode 7 cam_ xclkb 0 O gpio_111 4 IO safe_mode 7 cam_wen 0 I cam_ shutter 2 O IO gpio_167 4 safe_mode 7 cam_ strobe 0 O gpio_126 4 IO safe_mode 7 mcbsp2_fsx 0 IO gpio_116 4 IO safe_mode 7 mcbsp2_ clkx 0 IO gpio_117 4 IO safe_mode 7 mcbsp2_dr 0 I gpio_118 4 IO safe_mode 7 mcbsp2_dx 0 IO gpio_119 4 IO safe_mode 7 mmc1_clk 0 O gpio_120 4 IO safe_mode 7 mmc1_cmd 0 IO gpio_121 4 IO safe_mode 7 mmc1_dat0 0 IO gpio_122 4 IO safe_mode 7 mmc1_dat1 0 IO gpio_123 4 IO safe_mode 7 mmc1_dat2 0 IO gpio_124 4 IO The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in the above table. TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 PIN NAME [3] MODE [4] safe_mode 7 N23 mmc1_dat3 gpio_125 N22 N21 N20 P24 Y1 AB5 AB3 Y3 W3 V3 AB2 AA2 Y2 TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] 0 IO L L 7 MMC1_ VDDS Yes 8 PU/ PD LVCMOS 4 IO L L 7 VDDS_MMC1a No 8 PD LVCMOS L L 7 VDDS_MMC1a No 8 PD LVCMOS L L 7 VDDS_MMC1a No 8 PD LVCMOS L L 7 VDDS_MMC1a No 8 PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS safe_mode 7 mmc1_dat4 0 IO gpio_126 4 IO safe_mode 7 mmc1_dat5 0 IO gpio_127 4 IO safe_mode 7 mmc1_dat6 0 IO gpio_128 4 IO safe_mode 7 mmc1_dat7 0 IO gpio_129 4 IO safe_mode 7 mmc2_clk 0 O mcspi3_clk 1 IO IO gpio_130 4 safe_mode 7 mmc2_ cmd 0 IO mcspi3_ simo 1 IO IO gpio_131 4 safe_mode 7 mmc2_ dat0 0 IO mcspi3_ somi 1 IO IO gpio_132 4 safe_mode 7 mmc2_ dat1 0 IO gpio_133 4 IO safe_mode 7 mmc2_ dat2 0 IO mcspi3_cs1 1 O IO gpio_134 4 safe_mode 7 mmc2_ dat3 0 IO mcspi3_cs0 1 IO IO gpio_135 4 safe_mode 7 mmc2_ dat4 0 IO mmc2_dir_dat0 1 O mmc3_dat0 3 IO gpio_136 4 IO safe_mode 7 mmc2_ dat5 0 IO mmc2_dir_dat1 1 O cam_global_reset 2 IO mmc3_dat1 3 IO gpio_137 4 IO safe_mode 7 mmc2_ dat6 0 IO mmc2_dir_ cmd 1 O cam_ shutter 2 O mmc3_dat2 3 IO Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW Table 2-3. Ball Characteristics (CUS Pkg.) (continued) BALL BOTTOM [1] 59 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-3. Ball Characteristics (CUS Pkg.) (continued) BALL BOTTOM [1] AA1 V6 PRODUCT PREVIEW V5 W4 V4 W7 W6 AC2 V7 W19 AB20 W18 Y18 60 PIN NAME [3] MODE [4] TYPE [5] IO gpio_138 4 safe_mode 7 mmc2_ dat7 0 IO mmc2_ clkin 1 I mmc3_dat3 3 IO gpio_139 4 IO safe_mode 7 mcbsp3_dx 0 IO uart2_cts 1 I IO gpio_140 4 safe_mode 7 mcbsp3_dr 0 I uart2_rts 1 O IO gpio_141 4 safe_mode 7 mcbsp3_ clkx 0 IO uart2_tx 1 O IO gpio_142 4 safe_mode 7 mcbsp3_fsx 0 IO uart2_rx 1 I IO gpio_143 4 safe_mode 7 uart1_tx 0 O gpio_148 4 IO safe_mode 7 uart1_rts 0 O gpio_149 4 IO safe_mode 7 uart1_cts 0 I gpio_150 4 IO safe_mode 7 uart1_rx 0 I mcbsp1_ clkr 2 IO mcspi4_clk 3 IO gpio_151 4 IO safe_mode 7 mcbsp1_ clkr 0 IO mcspi4_clk 1 IO IO gpio_156 4 safe_mode 7 mcbsp1_fsr 0 IO cam_global_reset 2 IO IO gpio_157 4 safe_mode 7 mcbsp1_dx 0 IO mcspi4_ simo 1 IO mcbsp3_dx 2 IO gpio_158 4 IO safe_mode 7 mcbsp1_dr 0 I mcspi4_ somi 1 IO mcbsp3_dr 2 O gpio_159 4 IO TERMINAL DESCRIPTION BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 PIN NAME [3] MODE [4] safe_mode 7 AA18 mcbsp_clks cam_ shutter AA19 V18 A23 B23 B24 C23 R21 R23 P23 R22 T24 T23 U24 U23 TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] 0 I L L 7 VDDS Yes 4 PU/ PD LVCMOS 2 O gpio_160 4 IO uart1_cts 5 I safe_mode 7 mcbsp1_fsx 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS mcspi4_cs0 1 IO mcbsp3_fsx 2 IO gpio_161 4 IO safe_mode 7 mcbsp1_ clkx 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS mcbsp3_ clkx 2 IO IO H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS gpio_162 4 safe_mode 7 uart3_cts_ rctx 0 IO gpio_163 4 IO safe_mode 7 uart3_rts_ sd 0 O gpio_164 4 IO safe_mode 7 uart3_rx_ irrx 0 I gpio_165 4 IO safe_mode 7 uart3_tx_ irtx 0 O gpio_166 4 IO safe_mode 7 hsusb0_clk 0 I gpio_120 4 IO safe_mode 7 hsusb0_stp 0 O gpio_121 4 IO safe_mode 7 hsusb0_dir 0 I gpio_122 4 IO safe_mode 7 hsusb0_nxt 0 I gpio_124 4 IO safe_mode 7 hsusb0_ data0 0 IO uart3_tx_ irtx 2 O IO gpio_125 4 safe_mode 7 hsusb0_ data1 0 IO uart3_rx_ irrx 2 I IO gpio_130 4 safe_mode 7 hsusb0_ data2 0 IO uart3_rts_ sd 2 O IO gpio_131 4 safe_mode 7 hsusb0_ data3 0 IO uart3_cts_ rctx 2 IO gpio_169 4 IO Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW Table 2-3. Ball Characteristics (CUS Pkg.) (continued) BALL BOTTOM [1] 61 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-3. Ball Characteristics (CUS Pkg.) (continued) BALL BOTTOM [1] PIN NAME [3] MODE [4] safe_mode 7 W24 hsusb0_ data4 gpio_188 V23 W23 PRODUCT PREVIEW T22 BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS 4 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS safe_mode 7 hsusb0_ data5 0 IO gpio_189 4 IO safe_mode 7 hsusb0_ data6 0 IO gpio_190 4 IO safe_mode 7 hsusb0_ data7 0 IO gpio_191 4 IO safe_mode 7 K20 i2c1_scl 0 IOD H H 0 VDDS Yes 4 PU/ PD Open Drain K21 i2c1_sda 0 IOD H H 0 VDDS Yes 4 PU/ PD Open Drain AC15 i2c2_scl 0 IOD H H 7 VDDS Yes 4 PU/ PD Open Drain gpio_168 4 IO safe_mode 7 i2c2_sda 0 IOD H H 7 VDDS Yes 4 PU/ PD Open Drain gpio_183 4 IO safe_mode 7 i2c3_scl 0 IOD H H 7 VDDS Yes 4 PU/ PD Open Drain gpio_184 4 IO safe_mode 7 i2c3_sda 0 IOD H H 7 VDDS Yes 4 PU/ PD Open Drain gpio_185 4 IO safe_mode 7 i2c4_scl 0 IOD H H 0 VDDS Yes 4 PU/ PD Open Drain sys_ nvmode1 1 O safe_mode 7 i2c4_sda 0 IOD H H 0 VDDS Yes 4 PU/ PD Open Drain sys_ nvmode2 1 O safe_mode 7 hdq_sio 0 IOD H H 7 VDDS Yes 4 PU/ PD LVCMOS sys_altclk 1 I i2c2_sccbe 2 O i2c3_sccbe 3 O gpio_170 4 IO safe_mode 7 mcspi1_clk 0 IO PGM L 7 VDDS Yes 4 (2) PU/ PD LVCMOS mmc2_dat4 1 IO IO PGM L 7 VDDS Yes 4 (2) PU/ PD LVCMOS PGM L 7 VDDS Yes 4 (2) PU/ PD LVCMOS PGM H 7 VDDS Yes 4 (2) PU/ PD LVCMOS AC14 AC13 AC12 Y16 Y15 A24 T5 R4 T4 T6 62 TYPE [5] gpio_171 4 safe_mode 7 mcspi1_ simo 0 IO mmc2_dat5 1 IO IO gpio_172 4 safe_mode 7 mcspi1_ somi 0 IO mmc2_dat6 1 IO IO gpio_173 4 safe_mode 7 mcspi1_cs0 0 IO mmc2_dat7 1 IO gpio_174 4 IO TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 PIN NAME [3] MODE [4] safe_mode 7 R5 mcspi1_cs3 hsusb2_tll_ data2 N5 N4 N3 M5 M4 TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] 0 O H H 7 VDDS Yes 4 PU/ PD LVCMOS 2 IO hsusb2_ data2 3 IO gpio_177 4 IO mm2_txdat 5 IO safe_mode 7 L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS NA mcspi2_clk 0 IO hsusb2_tll_ data7 2 IO hsusb2_ data7 3 O gpio_178 4 IO safe_mode 7 mcspi2_ simo 0 IO gpt9_pwm_evt 1 IO hsusb2_tll_ data4 2 IO hsusb2_ data4 3 I gpio_179 4 IO safe_mode 7 mcspi2_ somi 0 IO gpt10_pwm_evt 1 IO hsusb2_tll_ data5 2 IO hsusb2_ data5 3 O gpio_180 4 IO safe_mode 7 mcspi2_cs0 0 IO gpt11_pwm_evt 1 IO hsusb2_tll_ data6 2 IO hsusb2_ data6 3 O gpio_181 4 IO safe_mode 7 mcspi2_cs1 0 O gpt8_pwm_evt 1 IO hsusb2_tll_ data3 2 IO hsusb2_ data3 3 IO gpio_182 4 IO mm2_txen_n 5 IO safe_mode 7 AA16 sys_32k 0 I Z I NA VDDS Yes NA LVCMOS AD15 sys_xtalin 0 I Z I NA VDDS Yes NA LVCMOS AD14 sys_xtalout 0 O Z O NA VDDS Yes NA LVCMOS Y13 sys_clkreq 0 IO 0 1 0 VDDS Yes 4 PU/ PD LVCMOS gpio_1 4 IO safe_mode 7 sys_nirq 0 I H H 7 VDDS Yes 4 PU/ PD LVCMOS gpio_0 4 IO W16 safe_mode 7 AA10 sys_ nrespwron 0 I Z I NA VDDS Yes NA NA LVCMOS Y10 sys_ nreswarm 0 IOD 0 1 (PU) 0 VDDS Yes 4 PU/ PD LVCMOS gpio_30 4 IO safe_mode 7 sys_boot0 0 I Z Z 0 VDDS Yes 4 PU/ PD LVCMOS gpio_2 4 IO safe_mode 7 AB12 Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW Table 2-3. Ball Characteristics (CUS Pkg.) (continued) BALL BOTTOM [1] 63 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-3. Ball Characteristics (CUS Pkg.) (continued) BALL BOTTOM [1] PIN NAME [3] MODE [4] AC16 sys_boot1 gpio_3 safe_mode 7 sys_boot2 0 I gpio_4 4 IO safe_mode 7 sys_boot3 0 I gpio_5 4 IO safe_mode 7 sys_boot4 0 I mmc2_dir_dat2 1 O IO AD17 AD18 AC17 PRODUCT PREVIEW AB16 AA15 AD23 Y7 AA6 BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] 0 I Z Z 0 VDDS Yes 4 PU/ PD LVCMOS 4 IO Z Z 0 VDDS Yes 4 PU/ PD LVCMOS Z Z 0 VDDS Yes 4 PU/ PD LVCMOS Z Z 0 VDDS Yes 4 PU/ PD LVCMOS Z Z 0 VDDS Yes 4 PU/ PD LVCMOS Z Z 0 VDDS Yes 4 PU/ PD LVCMOS 0 L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS gpio_6 4 safe_mode 7 sys_boot5 0 I mmc2_dir_dat3 1 O IO gpio_7 4 safe_mode 7 sys_boot6 0 I gpio_8 4 IO safe_mode 7 sys_off_ mode 0 O gpio_9 4 IO safe_mode 7 sys_clkout1 0 O gpio_10 4 IO safe_mode 7 sys_clkout2 0 O gpio_186 4 IO safe_mode 7 A1 sys_ ipmcsws 0 AI Z AI NA VDDS NA NA NA Analog A2 sys_ opmcsws 0 AO 0 AO NA VDDS No NA NA LVCMOS AB7 jtag_ntrst 0 I L L 0 VDDS Yes NA PU/ PD LVCMOS AB6 jtag_tck 0 I L L 0 VDDS Yes NA PU/ PD LVCMOS AA7 jtag_rtck 0 O L 0 0 VDDS Yes 4 PU/ PD LVCMOS AA9 jtag_tms_tmsc 0 IO H H 0 VDDS Yes 4 PU/ PD LVCMOS AB10 jtag_tdi 0 I H H 0 VDDS Yes NA PU/ PD LVCMOS AB9 jtag_tdo 0 O L Z 0 VDDS Yes 4 PU/ PD LVCMOS AC24 jtag_emu0 0 IO H H 0 VDDS Yes 4 PU/ PD LVCMOS gpio_11 4 IO safe_mode 7 jtag_emu1 0 IO H H 0 VDDS Yes 4 PU/ PD LVCMOS gpio_31 4 IO safe_mode 7 etk_clk 0 O H H 4 VDDS Yes 4 PU/ PD LVCMOS mcbsp5_ clkx 1 IO O H H 4 VDDS Yes 4 PU/ PD LVCMOS AD24 AC1 AD3 64 TYPE [5] mmc3_clk 2 hsusb1_stp 3 O gpio_12 4 IO IO mm1_rxdp 5 hsusb1_tll_stp 6 I etk_ctl 0 O mmc3_cmd 2 IO hsusb1_clk 3 O gpio_13 4 IO TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 AD6 AC6 AC7 AD8 AC5 AD2 AC8 AD9 PIN NAME [3] MODE [4] TYPE [5] hsusb1_tll_clk 6 O etk_d0 0 O mcspi3_ simo 1 IO mmc3_dat4 2 IO hsusb1_ data0 3 IO gpio_14 4 IO mm1_rxrcv 5 IO hsusb1_tll_ data0 6 IO etk_d1 0 O mcspi3_ somi 1 IO hsusb1_ data1 3 IO gpio_15 4 IO mm1_txse0 5 IO hsusb1_tll_ data1 6 IO etk_d2 0 O mcspi3_cs0 1 IO hsusb1_ data2 3 IO gpio_16 4 IO mm1_txdat 5 IO hsusb1_tll_data2 6 IO etk_d3 0 O mcspi3_clk 1 IO mmc3_dat3 2 IO hsusb1_ data7 3 IO gpio_17 4 IO hsusb1_tll_ data7 6 IO etk_d4 0 O mcbsp5_dr 1 I mmc3_dat0 2 IO hsusb1_ data4 3 IO gpio_18 4 IO hsusb1_tll_ data4 6 IO etk_d5 0 O mcbsp5_fsx 1 IO mmc3_dat1 2 IO hsusb1_ data5 3 IO gpio_19 4 IO hsusb1_tll_ data5 6 IO etk_d6 0 O mcbsp5_dx 1 IO mmc3_dat2 2 IO hsusb1_ data6 3 IO gpio_20 4 IO hsusb1_tll_ data6 6 IO etk_d7 0 O mcspi3_cs1 1 O mmc3_dat7 2 IO hsusb1_ data3 3 IO gpio_21 4 IO mm1_txen_n 5 IO hsusb1_tll_ data3 6 IO Submit Documentation Feedback BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] H H 4 VDDS Yes 4 PU/ PD LVCMOS H H 4 VDDS Yes 4 PU/ PD LVCMOS H H 4 VDDS Yes 4 PU/ PD LVCMOS H H 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS TERMINAL DESCRIPTION PRODUCT PREVIEW Table 2-3. Ball Characteristics (CUS Pkg.) (continued) BALL BOTTOM [1] 65 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-3. Ball Characteristics (CUS Pkg.) (continued) BALL BOTTOM [1] AC4 AD5 PRODUCT PREVIEW AC3 AC9 AC10 AD11 AC11 AD12 66 PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS etk_d8 0 O sys_drm_ msecure 1 O mmc3_dat6 2 IO hsusb1_dir 3 I gpio_22 4 IO hsusb1_tll_dir 6 O etk_d9 0 O sys_secure_indic ator 1 O mmc3_dat5 2 IO hsusb1_nxt 3 I gpio_23 4 IO mm1_rxdm 5 IO hsusb1_tll_nxt 6 O etk_d10 0 O uart1_rx 2 I hsusb2_clk 3 O gpio_24 4 IO hsusb2_tll_clk 6 O etk_d11 0 O hsusb2_stp 3 O gpio_25 4 IO mm2_rxdp 5 IO hsusb2_tll_stp 6 I etk_d12 0 O hsusb2_dir 3 I gpio_26 4 IO hsusb2_tll_dir 6 O etk_d13 0 O hsusb2_nxt 3 I gpio_27 4 IO mm2_rxdm 5 IO hsusb2_tll_nxt 6 O etk_d14 0 O hsusb2_ data0 3 IO gpio_28 4 IO mm2_rxrcv 5 IO hsusb2_tll_ data0 6 IO etk_d15 0 O hsusb2_ data1 3 IO gpio_29 4 IO mm2_txse0 5 IO hsusb2_tll_ data1 6 IO TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 2.3 Multiplexing Characteristics Table 2-4 through Table 2-6 provide a description of the OMAP3515/03 multiplexing on the CBB, CBC, and CUS packages, respectively. Note: Table 2-4 and Table 2-6 do not take into account subsystem pin multiplexing options. Subsystem pin multiplexing options are described in Section 2.4, Signal Description. Ball Bottom Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 D6 J2 sdrc_d0 - - - - - - - C6 J1 sdrc_d1 - - - - - - - B6 G2 sdrc_d2 - - - - - - - C8 G1 sdrc_d3 - - - - - - - C9 F2 sdrc_d4 - - - - - - - A7 F1 sdrc_d5 - - - - - - - B9 D2 sdrc_d6 - - - - - - - A9 D1 sdrc_d7 - - - - - - - C14 B13 sdrc_d8 - - - - - - - B14 A13 sdrc_d9 - - - - - - - C15 B14 sdrc_d10 - - - - - - - (1) B16 A14 sdrc_d11 - - - - - - - D17 B16 sdrc_d12 - - - - - - - C17 A16 sdrc_d13 - - - - - - - B17 B19 sdrc_d14 - - - - - - - D18 A19 sdrc_d15 - - - - - - - D11 B3 sdrc_d16 - - - - - - - B10 A3 sdrc_d17 - - - - - - - C11 B5 sdrc_d18 - - - - - - - D12 A5 sdrc_d19 - - - - - - - C12 B8 sdrc_d20 - - - - - - - A11 A8 sdrc_d21 - - - - - - - B13 B9 sdrc_d22 - - - - - - - D14 A9 sdrc_d23 - - - - - - - C18 B21 sdrc_d24 - - - - - - - A19 A21 sdrc_d25 - - - - - - - B19 D22 sdrc_d26 - - - - - - - B20 D23 sdrc_d27 - - - - - - - D20 E22 sdrc_d28 - - - - - - - A21 E23 sdrc_d29 - - - - - - - B21 G22 sdrc_d30 - - - - - - - C21 G23 sdrc_d31 - - - - - - - H9 AB21 sdrc_ba0 - - - - - - - H10 AC21 sdrc_ba1 - - - - - - - A4 N22 sdrc_a0 - - - - - - - B4 N 23 sdrc_a1 - - - - - - - B3 P22 sdrc_a2 - - - - - - - C5 P23 sdrc_a3 - - - - - - - C4 R22 sdrc_a4 - - - - - - - PRODUCT PREVIEW Table 2-4. Multiplexing Characteristics (CBB Pkg.) (1) NA in table stands for Not Applicable. Submit Documentation Feedback TERMINAL DESCRIPTION 67 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-4. Multiplexing Characteristics (CBB Pkg.) (continued) Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 D5 R23 sdrc_a5 - - - - - - - C3 T22 sdrc_a6 - - - - - - - C2 T23 sdrc_a7 - - - - - - - C1 U22 sdrc_a8 - - - - - - - D4 U23 sdrc_a9 - - - - - - - D3 V22 sdrc_a10 - - - - - - - D2 V23 sdrc_a11 - - - - - - - D1 W22 sdrc_a12 - - - - - - - E2 W23 sdrc_a13 - - - - - - - E1 Y22 sdrc_a14 - - - - - - - H11 M22 sdrc_ncs0 - - - - - - - H12 M23 sdrc_ncs1 - - - - - - - A13 A11 sdrc_clk - - - - - - - A14 B11 sdrc_nclk - - - - - - - H16 J22 sdrc_cke0 - - - - - - safe_mode H17 J23 sdrc_cke1 - - - - - - safe_mode H14 L23 sdrc_nras - - - - - - - H13 L22 sdrc_ncas - - - - - - - H15 K23 sdrc_nwe - - - - - - - B7 C1 sdrc_dm0 - - - - - - - A16 A17 sdrc_dm1 - - - - - - - PRODUCT PREVIEW Ball Bottom 68 B11 A6 sdrc_dm2 - - - - - - - C20 A20 sdrc_dm3 - - - - - - - A6 C2 sdrc_dqs0 - - - - - - - A17 B17 sdrc_dqs1 - - - - - - - A10 B6 sdrc_dqs2 - - - - - - - A20 B20 sdrc_dqs3 - - - - - - - N4 AC15 gpmc_a1 - - - gpio_34 - - safe_mode M4 AB15 gpmc_a2 - - - gpio_35 - - safe_mode L4 AC16 gpmc_a3 - - - gpio_36 - - safe_mode K4 AB16 gpmc_a4 - - - gpio_37 - - safe_mode T3 AC17 gpmc_a5 - - - gpio_38 - - safe_mode R3 AB17 gpmc_a6 - - - gpio_39 - - safe_mode N3 AC18 gpmc_a7 - - - gpio_40 - - safe_mode M3 AB18 gpmc_a8 - - - gpio_41 - - safe_mode L3 AC19 gpmc_a9 sys_ ndmareq2 - - gpio_42 - - safe_mode K3 AB19 gpmc_a10 sys_ ndmareq3 - - gpio_43 - - safe_mode K1 M2 gpmc_d0 - - - - - - - L1 M1 gpmc_d1 - - - - - - - L2 N2 gpmc_d2 - - - - - - - P2 N1 gpmc_d3 - - - - - - - T1 R2 gpmc_d4 - - - - - - - V1 R1 gpmc_d5 - - - - - - - V2 T2 gpmc_d6 - - - - - - - W2 T1 gpmc_d7 - - - - - - - TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Ball Bottom Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 H2 AB3 gpmc_d8 - - - gpio_44 - - safe_mode K2 AC3 gpmc_d9 - - - gpio_45 - - safe_mode P1 AB4 gpmc_d10 - - - gpio_46 - - safe_mode R1 AC4 gpmc_d11 - - - gpio_47 - - safe_mode R2 AB6 gpmc_d12 - - - gpio_48 - - safe_mode T2 AC6 gpmc_d13 - - - gpio_49 - - safe_mode W1 AB7 gpmc_d14 - - - gpio_50 - - safe_mode Y1 AC7 gpmc_d15 - - - gpio_51 - - safe_mode G4 Y2 gpmc_ncs0 - - - - - - - H3 Y1 gpmc_ncs1 - - - gpio_52 - - safe_mode V8 NA gpmc_ncs2 - - - gpio_53 - - safe_mode U8 NA gpmc_ncs3 sys_ ndmareq0 - - gpio_54 - - safe_mode T8 NA gpmc_ncs4 sys_ ndmareq1 mcbsp4_clkx gpt9_pwm_ evt gpio_55 - - safe_mode R8 NA gpmc_ncs5 sys_ ndmareq2 mcbsp4_dr gpt10_pwm_ evt gpio_56 - - safe_mode P8 NA gpmc_ncs6 sys_ ndmareq3 mcbsp4_dx gpt11_pwm_ evt gpio_57 - - safe_mode N8 NA gpmc_ncs7 gpmc_io_dir mcbsp4_fsx gpt8_pwm_ evt gpio_58 - - safe_mode T4 W2 gpmc_clk - - - gpio_59 - - safe_mode F3 W1 gpmc_nadv_ ale - - - - - - - G2 V2 gpmc_noe - - - - - - - F4 V1 gpmc_nwe - - - - - - - G3 AC12 gpmc_nbe0_ cle - - - gpio_60 - - safe_mode U3 NA gpmc_nbe1 - - - gpio_61 - - safe_mode safe_mode H1 AB10 gpmc_nwp - - - gpio_62 - - M8 AB12 gpmc_wait0 - - - - - - - L8 AC10 gpmc_wait1 - - - gpio_63 - - safe_mode K8 NA gpmc_wait2 - - - gpio_64 - - safe_mode J8 NA gpmc_wait3 sys_ ndmareq1 - - gpio_65 - - safe_mode D28 NA dss_pclk - - - gpio_66 - - safe_mode D26 NA dss_hsync - - - gpio_67 - - safe_mode D27 NA dss_vsync - - - gpio_68 - - safe_mode E27 NA dss_acbias - - - gpio_69 - - safe_mode AG22 NA dss_data0 - uart1_cts - gpio_70 - - safe_mode AH22 NA dss_data1 - uart1_rts - gpio_71 - - safe_mode AG23 NA dss_data2 - - - gpio_72 - - safe_mode AH23 NA dss_data3 - - - gpio_73 - - safe_mode AG24 NA dss_data4 - uart3_rx_irrx - gpio_74 - - safe_mode AH24 NA dss_data5 - uart3_tx_irtx - gpio_75 - - safe_mode E26 NA dss_data6 - uart1_tx - gpio_76 - - safe_mode F28 NA dss_data7 - uart1_rx - gpio_77 - - safe_mode F27 NA dss_data8 - - - gpio_78 - - safe_mode G26 NA dss_data9 - - - gpio_79 - - safe_mode Submit Documentation Feedback TERMINAL DESCRIPTION 69 PRODUCT PREVIEW Table 2-4. Multiplexing Characteristics (CBB Pkg.) (continued) OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-4. Multiplexing Characteristics (CBB Pkg.) (continued) Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 AD28 NA dss_data10 - - - gpio_80 - - safe_mode AD27 NA dss_data11 - - - gpio_81 - - safe_mode AB28 NA dss_data12 - - - gpio_82 - - safe_mode AB27 NA dss_data13 - - - gpio_83 - - safe_mode AA28 NA dss_data14 - - - gpio_84 - - safe_mode AA27 NA dss_data15 - - - gpio_85 - - safe_mode G25 NA dss_data16 - - - gpio_86 - - safe_mode H27 NA dss_data17 - - - gpio_87 - - safe_mode H26 NA dss_data18 - mcspi3_clk dss_data0 gpio_88 - - safe_mode H25 NA dss_data19 - mcspi3_simo dss_data1 gpio_89 - - safe_mode E28 NA dss_data20 - mcspi3_somi dss_data2 gpio_90 - - safe_mode PRODUCT PREVIEW Ball Bottom 70 J26 NA dss_data21 - mcspi3_cs0 dss_data3 gpio_91 - - safe_mode AC27 NA dss_data22 - mcspi3_cs1 dss_data4 gpio_92 - - safe_mode AC28 NA dss_data23 - - dss_data5 gpio_93 - - safe_mode W28 NA tv_out2 - - - - - - - Y28 NA tv_out1 - - - - - - - Y27 NA tv_vfb1 - - - - - - - W27 NA tv_vfb2 - - - - - - - W26 NA tv_vref - - - - - - - A24 NA cam_hs - - - gpio_94 - - safe_mode A23 NA cam_vs - - - gpio_95 - - safe_mode C25 NA cam_xclka - - - gpio_96 - - safe_mode C27 NA cam_pclk - - - gpio_97 - - safe_mode C23 NA cam_fld - cam_global_ reset - gpio_98 - - safe_mode AG17 NA cam_d0 - - - gpio_99 - - safe_mode AH17 NA cam_d1 - - - gpio_100 - - safe_mode B24 NA cam_d2 - - - gpio_101 - - safe_mode C24 NA cam_d3 - - - gpio_102 - - safe_mode D24 NA cam_d4 - - - gpio_103 - - safe_mode A25 NA cam_d5 - - - gpio_104 - - safe_mode K28 NA cam_d6 - - - gpio_105 - - safe_mode L28 NA cam_d7 - - - gpio_106 - - safe_mode K27 NA cam_d8 - - - gpio_107 - - safe_mode L27 NA cam_d9 - - - gpio_108 - - safe_mode B25 NA cam_d10 - - - gpio_109 - - safe_mode C26 NA cam_d11 - - - gpio_110 - - safe_mode B26 NA cam_xclkb - - - gpio_111 - - safe_mode B23 NA cam_wen - cam_shutter - gpio_167 - - safe_mode D25 NA cam_strobe - - - gpio_126 - - safe_mode AG19 NA - - - - gpio_112 - - safe_mode AH19 NA - - - - gpio_113 - - safe_mode AG18 NA - - - - gpio_114 - - safe_mode AH18 NA - - - - gpio_115 - - safe_mode P21 NA mcbsp2_fsx - - - gpio_116 - - safe_mode N21 NA mcbsp2_clkx - - - gpio_117 - - safe_mode R21 NA mcbsp2_dr - - - gpio_118 - - safe_mode TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Ball Bottom Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 M21 NA mcbsp2_dx - - - gpio_119 - - safe_mode N28 NA mmc1_clk - - - gpio_120 - - safe_mode M27 NA mmc1_cmd - - - gpio_121 - - safe_mode N27 NA mmc1_dat0 - - - gpio_122 - - safe_mode N26 NA mmc1_dat1 - - - gpio_123 - - safe_mode N25 NA mmc1_dat2 - - - gpio_124 - - safe_mode P28 NA mmc1_dat3 - - - gpio_125 - - safe_mode P27 NA mmc1_dat4 - - - gpio_126 - - safe_mode P26 NA mmc1_dat5 - - - gpio_127 - - safe_mode R27 NA mmc1_dat6 - - - gpio_128 - - safe_mode R25 NA mmc1_dat7 - - - gpio_129 - - safe_mode AE2 NA mmc2_clk mcspi3_clk - - gpio_130 - - safe_mode AG5 NA mmc2_cmd mcspi3_simo - - gpio_131 - - safe_mode AH5 NA mmc2_dat0 mcspi3_somi - - gpio_132 - - safe_mode AH4 NA mmc2_dat1 - - - gpio_133 - - safe_mode AG4 NA mmc2_dat2 mcspi3_cs1 - - gpio_134 - - safe_mode AF4 NA mmc2_dat3 mcspi3_cs0 - - gpio_135 - - safe_mode AE4 NA mmc2_dat4 mmc2_dir_ dat0 - mmc3_dat0 gpio_136 - - safe_mode AH3 NA mmc2_dat5 mmc2_dir_ dat1 cam_global_ reset mmc3_dat1 gpio_137 hsusb3_tll_ stp mm3_rxdp safe_mode AF3 NA mmc2_dat6 mmc2_dir_ cmd cam_shutter mmc3_dat2 gpio_138 hsusb3_tll_ dir - safe_mode AE3 NA mmc2_dat7 mmc2_clkin - mmc3_dat3 gpio_139 hsusb3_tll_ nxt mm3_rxdm safe_mode AF6 NA mcbsp3_dx uart2_cts - - gpio_140 hsusb3_tll_ data4 - safe_mode AE6 NA mcbsp3_dr uart2_rts - - gpio_141 hsusb3_tll_ data5 - safe_mode AF5 NA mcbsp3_clkx uart2_tx - - gpio_142 hsusb3_tll_ data6 - safe_mode AE5 NA mcbsp3_fsx uart2_rx - - gpio_143 hsusb3_tll_ data7 - safe_mode AB2 NA uart2_cts mcbsp3_dx gpt9_pwm_ evt - gpio_144 - - safe_mode AB25 NA uart2_rts mcbsp3_dr gpt10_pwm_ evt - gpio_145 - - safe_mode AA25 NA uart2_tx mcbsp3_clkx gpt11_pwm_ evt - gpio_146 - - safe_mode AD25 NA uart2_rx mcbsp3_fsx gpt8_pwm_ evt - gpio_147 - - safe_mode AA8 NA uart1_tx - - - gpio_148 - - safe_mode AA9 NA uart1_rts - - - gpio_149 - - safe_mode W8 NA uart1_cts - - - gpio_150 hsusb3_tll_ clk - safe_mode Y8 NA uart1_rx - mcbsp1_clkr mcspi4_clk gpio_151 - - safe_mode AE1 NA mcbsp4_clkx - - - gpio_152 hsusb3_tll_ data1 mm3_txse0 safe_mode AD1 NA mcbsp4_dr - - - gpio_153 hsusb3_tll_ data0 mm3_rxrcv safe_mode Submit Documentation Feedback TERMINAL DESCRIPTION 71 PRODUCT PREVIEW Table 2-4. Multiplexing Characteristics (CBB Pkg.) (continued) OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-4. Multiplexing Characteristics (CBB Pkg.) (continued) Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 AD2 NA mcbsp4_dx - - - gpio_154 hsusb3_tll_ data2 mm3_txdat safe_mode AC1 NA mcbsp4_fsx - - - gpio_155 hsusb3_tll_ data3 mm3_txen_n safe_mode Y21 NA mcbsp1_clkr mcspi4_clk - - gpio_156 - - safe_mode AA21 NA mcbsp1_fsr - cam_global_ reset - gpio_157 - - safe_mode V21 NA mcbsp1_dx mcspi4_simo mcbsp3_dx - gpio_158 - - safe_mode U21 NA mcbsp1_dr mcspi4_somi mcbsp3_dr - gpio_159 - - safe_mode T21 NA mcbsp_clks - cam_shutter - gpio_160 uart1_cts - safe_mode K26 NA mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx - gpio_161 - - safe_mode W21 NA mcbsp1_clkx - mcbsp3_clkx - gpio_162 - - safe_mode H18 NA uart3_cts_rct x - - - gpio_163 - - safe_mode H19 NA uart3_rts_sd - - - gpio_164 - - safe_mode H20 NA uart3_rx_irrx - - - gpio_165 - - safe_mode H21 NA uart3_tx_irtx - - - gpio_166 - - safe_mode T28 NA hsusb0_clk - - - gpio_120 - - safe_mode PRODUCT PREVIEW Ball Bottom 72 T25 NA hsusb0_stp - - - gpio_121 - - safe_mode R28 NA hsusb0_dir - - - gpio_122 - - safe_mode T26 NA hsusb0_nxt - - - gpio_124 - - safe_mode T27 NA hsusb0_ data0 - uart3_tx_irtx - gpio_125 - - safe_mode U28 NA hsusb0_ data1 - uart3_rx_irrx - gpio_130 - - safe_mode U27 NA hsusb0_ data2 - uart3_rts_sd - gpio_131 - - safe_mode U26 NA hsusb0_ data3 - uart3_cts_ rctx - gpio_169 - - safe_mode U25 NA hsusb0_ data4 - - - gpio_188 - - safe_mode V28 NA hsusb0_ data5 - - - gpio_189 - - safe_mode V27 NA hsusb0_ data6 - - - gpio_190 - - safe_mode V26 NA hsusb0_ data7 - - - gpio_191 - - safe_mode K21 NA i2c1_scl - - - - - - - J21 NA i2c1_sda - - - - - - - AF15 NA i2c2_scl - - - gpio_168 - - safe_mode AE15 NA i2c2_sda - - - gpio_183 - - safe_mode AF14 NA i2c3_scl - - - gpio_184 - - safe_mode AG14 NA i2c3_sda - - - gpio_185 - - safe_mode AD26 NA i2c4_scl sys_ nvmode1 - - - - - safe_mode AE26 NA i2c4_sda sys_ nvmode2 - - - - - safe_mode J25 NA hdq_sio sys_altclk i2c2_sccbe i2c3_sccbe gpio_170 - - safe_mode AB3 NA mcspi1_clk mmc2_dat4 - - gpio_171 - - safe_mode AB4 NA mcspi1_simo mmc2_dat5 - - gpio_172 - - safe_mode AA4 NA mcspi1_somi mmc2_dat6 - - gpio_173 - - safe_mode TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Ball Bottom Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 AC2 NA mcspi1_cs0 mmc2_dat7 - - gpio_174 - - safe_mode AC3 NA mcspi1_cs1 - - mmc3_cmd gpio_175 - - safe_mode AB1 NA mcspi1_cs2 - - mmc3_clk gpio_176 - - safe_mode AB2 NA mcspi1_cs3 - hsusb2_tll_ data2 hsusb2_ data2 gpio_177 mm2_txdat - safe_mode AA3 NA mcspi2_clk - hsusb2_tll_ data7 hsusb2_ data7 gpio_178 - - safe_mode Y2 NA mcspi2_simo gpt9_pwm_ evt hsusb2_tll_ data4 hsusb2_ data4 gpio_179 - - safe_mode Y3 NA mcspi2_somi gpt10_pwm_ evt hsusb2_tll_ data5 hsusb2_ data5 gpio_180 - - safe_mode Y4 NA mcspi2_cs0 gpt11_pwm_ evt hsusb2_tll_ data6 hsusb2_ data6 gpio_181 - - safe_mode V3 NA mcspi2_cs1 gpt8_pwm_ evt hsusb2_tll_ data3 hsusb2_ data3 gpio_182 mm2_txen_n - safe_mode AE25 NA sys_32k - - - - - - - AE17 NA sys_xtalin - - - - - - - AF17 NA sys_xtalout - - - - - - - AF25 NA sys_clkreq - - - gpio_1 - - safe_mode AF26 NA sys_nirq - - - gpio_0 - - safe_mode AH25 NA sys_nrespwr on - - - - - - - AF24 NA sys_nreswar m - - - gpio_30 - - safe_mode AH26 NA sys_boot0 - - - gpio_2 - - safe_mode AG26 NA sys_boot1 - - - gpio_3 - - safe_mode AE14 NA sys_boot2 - - - gpio_4 - - safe_mode AF18 NA sys_boot3 - - - gpio_5 - - safe_mode AF19 NA sys_boot4 mmc2_dir_ dat2 - - gpio_6 - - safe_mode AE21 NA sys_boot5 mmc2_dir_ dat3 - - gpio_7 - - safe_mode AF21 NA sys_boot6 - - - gpio_8 - - safe_mode AF22 NA sys_off_ mode - - - gpio_9 - - safe_mode AG25 NA sys_clkout1 - - - gpio_10 - - safe_mode AE22 NA sys_clkout2 - - - gpio_186 - - safe_mode B1 NA sys_ipmcsws - - - - - - - A1 NA sys_ opmcsws - - - - - - - AA17 NA jtag_ntrst - - - - - - - AA13 NA jtag_tck - - - - - - - AA12 NA jtag_rtck - - - - - - - AA18 NA jtag_tms_ tmsc - - - - - - - AA20 NA jtag_tdi - - - - - - - AA19 NA jtag_tdo - - - - - - - AA11 NA jtag_emu0 - - - gpio_11 - - safe_mode AA10 NA jtag_emu1 - - - gpio_31 - - safe_mode AF10 NA etk_clk mcbsp5_clkx mmc3_clk hsusb1_stp gpio_12 mm1_rxdp hsusb1_tll_ stp - Submit Documentation Feedback TERMINAL DESCRIPTION 73 PRODUCT PREVIEW Table 2-4. Multiplexing Characteristics (CBB Pkg.) (continued) OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-4. Multiplexing Characteristics (CBB Pkg.) (continued) Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 AE10 NA etk_ctl - mmc3_cmd hsusb1_clk gpio_13 - hsusb1_tll_ clk - AF11 NA etk_d0 mcspi3_simo mmc3_dat4 hsusb1_ data0 gpio_14 mm1_rxrcv hsusb1_tll_ data0 - AG12 NA etk_d1 mcspi3_somi - hsusb1_ data1 gpio_15 mm1_txse0 hsusb1_tll_ data1 - AH12 NA etk_d2 mcspi3_cs0 - hsusb1_ data2 gpio_16 mm1_txdat hsusb1_tll_ data2 - AE13 NA etk_d3 mcspi3_clk mmc3_dat3 hsusb1_ data7 gpio_17 - hsusb1_tll_ data7 - AE11 NA etk_d4 mcbsp5_dr mmc3_dat0 hsusb1_ data4 gpio_18 - hsusb1_tll_ data4 - AH9 NA etk_d5 mcbsp5_fsx mmc3_dat1 hsusb1_ data5 gpio_19 - hsusb1_tll_ data5 - AF13 NA etk_d6 mcbsp5_dx mmc3_dat2 hsusb1_ data6 gpio_20 - hsusb1_tll_ data6 - AH14 NA etk_d7 mcspi3_cs1 mmc3_dat7 hsusb1_ data3 gpio_21 mm1_txen_n hsusb1_tll_ data3 - AF9 NA etk_d8 sys_drm_ msecure mmc3_dat6 hsusb1_dir gpio_22 - hsusb1_tll_ dir - AG9 NA etk_d9 sys_secure_ indicator mmc3_dat5 hsusb1_nxt gpio_23 mm1_rxdm hsusb1_tll_ nxt - AE7 NA etk_d10 - uart1_rx hsusb2_clk gpio_24 - hsusb2_tll_ clk - AF7 NA etk_d11 - - hsusb2_stp gpio_25 mm2_rxdp hsusb2_tll_ stp - AG7 NA etk_d12 - - hsusb2_dir gpio_26 - hsusb2_tll_ dir - AH7 NA etk_d13 - - hsusb2_nxt gpio_27 mm2_rxdm hsusb2_tll_ nxt - AG8 NA etk_d14 - - hsusb2_ data0 gpio_28 mm2_rxrcv hsusb2_tll_ data0 - AH8 NA etk_d15 - - hsusb2_ data1 gpio_29 mm2_txse0 hsusb2_tll_ data1 - PRODUCT PREVIEW Ball Bottom Table 2-5. Multiplexing Characteristics (CBC Pkg.) Ball Bottom Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 AE16 - cam_d0 - - - - gpio_99 - safe_mode AE15 - cam_d1 - - - - gpio_100 - safe_mode AD17 - - - - - - gpio_112 - safe_mode AE18 - - - - - - gpio_114 - safe_mode AD16 - - - - - - gpio_113 - safe_mode AE17 - - - - - - gpio_115 - safe_mode - G20 sdrc_a0 - - - - - - - - K20 sdrc_a1 - - - - - - - - J20 sdrc_a2 - - - - - - - - J21 sdrc_a3 - - - - - - - - U21 sdrc_a4 - - - - - - - - R20 sdrc_a5 - - - - - - - - M21 sdrc_a6 - - - - - - - - M20 sdrc_a7 - - - - - - - 74 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Ball Bottom Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 - N20 sdrc_a8 - - - - - - - - K21 sdrc_a9 - - - - - - - - Y16 sdrc_a10 - - - - - - - - N21 sdrc_a11 - - - - - - - - R21 sdrc_a12 - - - - - - - - AA15 sdrc_a13 - - - - - - - - Y12 sdrc_a14 - - - - - - - - AA18 sdrc_ba0 - - - - - - - - V20 sdrc_ba1 - - - - - - - - Y15 sdrc_cke0 - - - - - - safe_mode - Y13 sdrc_cke1 - - - - - - safe_mode - A12 sdrc_clk - - - - - - - - D1 sdrc_d0 - - - - - - - - G1 sdrc_d1 - - - - - - - - G2 sdrc_d2 - - - - - - - - E1 sdrc_d3 - - - - - - - - D2 sdrc_d4 - - - - - - - - E2 sdrc_d5 - - - - - - - - B3 sdrc_d6 - - - - - - - - B4 sdrc_d7 - - - - - - - - A10 sdrc_d8 - - - - - - - - B11 sdrc_d9 - - - - - - - - A11 sdrc_d10 - - - - - - - - B12 sdrc_d11 - - - - - - - - A16 sdrc_d12 - - - - - - - - A17 sdrc_d13 - - - - - - - - B17 sdrc_d14 - - - - - - - - B18 sdrc_d15 - - - - - - - - B7 sdrc_d16 - - - - - - - - A5 sdrc_d17 - - - - - - - - B6 sdrc_d18 - - - - - - - - A6 sdrc_d19 - - - - - - - - A8 sdrc_d20 - - - - - - - - B9 sdrc_d21 - - - - - - - - A9 sdrc_d22 - - - - - - - - B10 sdrc_d23 - - - - - - - - C21 sdrc_d24 - - - - - - - - D20 sdrc_d25 - - - - - - - - B19 sdrc_d26 - - - - - - - - C20 sdrc_d27 - - - - - - - - D21 sdrc_d28 - - - - - - - -- E20 sdrc_d29 - - - - - - - - E21 sdrc_d30 - - - - - - - - G21 sdrc_d31 - - - - - - - - H1 sdrc_dm0 - - - - - - - - A14 sdrc_dm1 - - - - - - - Submit Documentation Feedback TERMINAL DESCRIPTION 75 PRODUCT PREVIEW Table 2-5. Multiplexing Characteristics (CBC Pkg.) (continued) OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-5. Multiplexing Characteristics (CBC Pkg.) (continued) PRODUCT PREVIEW Ball Bottom Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 - A4 sdrc_dm2 - - - - - - - A18 sdrc_dm3 - - - - - - - - C2 sdrc_dqs0 - - - - - - - - B15 sdrc_dqs1 - - - - - - - - B8 sdrc_dqs2 - - - - - - - - A19 sdrc_dqs3 - - - - - - - - U20 sdrc_ncas - - - - - - - - B13 sdrc_nclk - - - - - - - - T21 sdrc_ncs0 - - - - - - - - T20 sdrc_ncs1 - - - - - - - - V21 sdrc_nras - - - - - - - - Y18 sdrc_nwe - - - - - - - AE21 - dss_data0 dx0 uart1_cts - gpio_70 - - safe_mode AE22 - dss_data1 dy0 uart1_rts - gpio_71 - - safe_mode AE23 - dss_data2 dx1 - - gpio_72 - - safe_mode AE24 - dss_data3 dy1 - - gpio_73 - - safe_mode AC26 - dss_data10 - - - gpio_80 - - safe_mode AD26 - dss_data11 - - - gpio_81 - - safe_mode AA25 - dss_data12 - - - gpio_82 - - safe_mode Y25 - dss_data13 - - - gpio_83 - - safe_mode AA26 - dss_data14 - - - gpio_84 - - safe_mode AB26 - dss_data15 - - - gpio_85 - - safe_mode F25 - dss_data20 - mcspi3_so mi dss_data2 gpio_90 - - safe_mode AC25 - dss_data22 - mcspi3_cs1 dss_data4 gpio_92 - - safe_mode AB25 - dss_data23 - - dss_data5 gpio_93 - - safe_mode G25 - dss_pclk - - - gpio_66 hw_dbg12 - safe_mode J2 - gpmc_a1 - - - gpio_34 - - safe_mode H1 - gpmc_a2 - - - gpio_35 - - safe_mode H2 - gpmc_a3 - - - gpio_36 - - safe_mode G2 - gpmc_a4 - - - gpio_37 - - safe_mode F1 - gpmc_a5 - - - gpio_38 - - safe_mode F2 - gpmc_a6 - - - gpio_39 - - safe_mode E1 - gpmc_a7 - - - gpio_40 - - safe_mode E2 - gpmc_a8 - - - gpio_41 - - safe_mode D1 - gpmc_a9 sys_ndmare q2 - gpio_42 - - safe_mode D2 - gpmc_a10 sys_ndmare q3 - gpio_43 - - safe_mode N1 - gpmc_clk - - - gpio_59 - - safe_mode AA2 - gpmc_d0 - - - - - - - AA1 - gpmc_d1 - - - - - - - AC2 - gpmc_d2 - - - - - - - AC1 - gpmc_d3 - - - - - - - AE5 - gpmc_d4 - - - - - - - AD6 - gpmc_d5 - - - - - - - AD5 - gpmc_d6 - - - - - - - 76 TERMINAL DESCRIPTION Mode 7 Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Ball Bottom Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 AC5 - gpmc_d7 - - - - - - - V1 - gpmc_d8 - - - gpio_44 - - safe_mode Y1 - gpmc_d9 - - - gpio_45 - - safe_mode T1 - gpmc_d10 - - - gpio_46 - - safe_mode U2 - gpmc_d11 - - - gpio_47 - - safe_mode U1 - gpmc_d12 - - - gpio_48 - - safe_mode P1 - gpmc_d13 - - - gpio_49 - - safe_mode L2 - gpmc_d14 - - - gpio_50 - - safe_mode M2 - gpmc_d15 - - - gpio_51 - - safe_mode AD10 - gpmc_nadv _ale - - - - - - - K2 - gpmc_nbe0 _cle - - - gpio_60 - - safe_mode J1 - gpmc_nbe1 - - - gpio_61 - - safe_mode AD8 - gpmc_ncs0 - - - - - - - AD1 - gpmc_ncs1 - - - gpio_52 - - safe_mode A3 - gpmc_ncs2 - - - gpio_53 - - safe_mode B6 - gpmc_ncs3 sys_ndmare q0 - gpio_54 - - safe_mode B4 - gpmc_ncs4 sys_ndmare mcbsp4_clk q1 x gpt9_pwm_ evt gpio_55 - - safe_mode C4 - gpmc_ncs5 sys_ndmare mcbsp4_dr q2 gpt10_pwm _evt gpio_56 - - safe_mode B5 - gpmc_ncs6 sys_ndmare mcbsp4_dx q3 gpt11_pwm _evt gpio_57 - - safe_mode C5 - gpmc_ncs7 gpmc_io_dir mcbsp4_fsx gpt8_pwm_ evt gpio_58 - - safe_mode N2 - gpmc_noe - - - - - - - M1 - gpmc_nwe - - - - - - - AC6 - gpmc_nwp - - - gpio_62 - - safe_mode AC11 - gpmc_wait0 - - - - - - - AC8 - gpmc_wait1 - - - gpio_63 - - safe_mode B3 - gpmc_wait2 - - - gpio_64 - - safe_mode C6 - gpmc_wait3 sys_ndmare q1 - gpio_65 - - safe_mode W19 - hsusb0_clk - - - gpio_120 - - safe_mode V20 - hsusb0_dat a0 - uart3_tx_irtx - gpio_125 - - safe_mode Y20 - hsusb0_dat a1 - uart3_rx_irr x - gpio_130 - - safe_mode V18 - hsusb0_dat a2 - uart3_rts_s d - gpio_131 - - safe_mode W20 - hsusb0_dat a3 - uart3_cts_rc tx gpio_169 - - safe_mode W17 - hsusb0_dat a4 - - - gpio_188 - - safe_mode Y18 - hsusb0_dat a5 - - - gpio_189 - - safe_mode Y19 - hsusb0_dat a6 - - - gpio_190 - - safe_mode Submit Documentation Feedback TERMINAL DESCRIPTION 77 PRODUCT PREVIEW Table 2-5. Multiplexing Characteristics (CBC Pkg.) (continued) OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-5. Multiplexing Characteristics (CBC Pkg.) (continued) PRODUCT PREVIEW Ball Bottom Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Y17 - hsusb0_dat a7 - - - gpio_191 - - safe_mode V19 - hsusb0_dir - - - gpio_122 - - safe_mode W18 - hsusb0_nxt - - - gpio_124 - - safe_mode U20 - hsusb0_stp - - - gpio_121 - - safe_mode U15 - jtag_ntrst - - - - - - - W13 - jtag_rtck - - - - - - - V14 - jtag_tck - - - - - - - U16 - jtag_tdi - - - - - - - Y13 - jtag_tdo - - - - - - - V15 - jtag_tms_tm sc - - - - - - AE19 - vdd_dsi - - - - - - - K20 - vdd_sram_c ore - - - - - - N9 - vdd_sram_ mpu_iva - - - - - - - K14 - vdd_wkup - - - - - - - - vdd_sram_e mu - - - - - - N19 - mmc1_clk ms_clk - - gpio_120 - - safe_mode L18 - mmc1_cmd ms_bs - - gpio_121 - - safe_mode M19 - mmc1_dat0 ms_dat0 - - gpio_122 - - safe_mode M18 - mmc1_dat1 ms_dat1 - - gpio_123 - - safe_mode K18 - mmc1_dat2 ms_dat2 - - gpio_124 - - safe_mode N20 - mmc1_dat3 ms_dat3 - - gpio_125 - - safe_mode M20 - mmc1_dat4 - - - gpio_126 - - safe_mode P17 - mmc1_dat5 - - - gpio_127 - - safe_mode P18 - mmc1_dat6 - - - gpio_128 - - safe_mode P19 - mmc1_dat7 - - - gpio_129 - - safe_mode J25 - i2c1_scl - - - - - - - J24 - i2c1_sda - - - - - - - C2 - i2c2_scl - - - gpio_168 - - safe_mode C1 - i2c2_sda - - - gpio_183 - - safe_mode AB4 - i2c3_scl - - - gpio_184 - - safe_mode AC4 - i2c3_sda - - - gpio_185 - - safe_mode U19 - mcbsp1_clk r mcspi4_clk - - gpio_156 - - safe_mode T17 - mcbsp1_clk x - mcbsp3_clk x - gpio_162 - - safe_mode T20 - mcbsp1_dr mcspi4_so mi mcbsp3_dr - gpio_159 - - safe_mode U17 - mcbsp1_dx mcspi4_sim o mcbsp3_dx - gpio_158 - - safe_mode V17 - mcbsp1_fsr - cam_global _reset - gpio_157 - - safe_mode P20 - mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx - gpio_161 - - safe_mode R18 - mcbsp2_clk x - - - gpio_117 - - safe_mode T18 - mcbsp2_dr - - - gpio_118 - - safe_mode 78 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Ball Bottom Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 R19 - mcbsp2_dx - - - gpio_119 - - safe_mode U18 - mcbsp2_fsx - - - gpio_116 - - safe_mode P9 - mcspi1_clk mmc2_dat4 - - gpio_171 - - safe_mode R7 - mcspi1_cs0 mmc2_dat7 - - gpio_174 - - safe_mode R9 - mcspi1_cs2 - - mmc3_clk gpio_176 - - safe_mode P8 - mcspi1_sim o mmc2_dat5 - - gpio_172 - - safe_mode P7 - mcspi1_so mi mmc2_dat6 - - gpio_173 - - safe_mode W10 - mmc2_clk mcspi3_clk - - gpio_130 - - safe_mode R10 - mmc2_cmd mcspi3_sim o - - gpio_131 - - safe_mode T10 - mmc2_dat0 mcspi3_so mi - - gpio_132 - - safe_mode T9 - mmc2_dat1 - - - gpio_133 - - safe_mode U10 - mmc2_dat2 mcspi3_cs1 - - gpio_134 - - safe_mode U9 - mmc2_dat3 mcspi3_cs0 - - gpio_135 - - safe_mode V10 - mmc2_dat4 mmc2_dir_d at0 mmc3_dat0 gpio_136 - - safe_mode R2 - uart1_rts - - - gpio_149 - - safe_mode H3 - uart1_rx - mcbsp1_clk r mcspi4_clk gpio_151 - - safe_mode L4 - uart1_tx - - - gpio_148 - - safe_mode Y24 - uart2_cts mcbsp3_dx gpt9_pwm_ evt - gpio_144 - - safe_mode AA24 - uart2_rts mcbsp3_dr gpt10_pwm _evt - gpio_145 - - safe_mode AD21 - uart2_rx mcbsp3_fsx gpt8_pwm_ evt - gpio_147 - - safe_mode AD22 - uart2_tx mcbsp3_clk x gpt11_pwm _evt - gpio_146 - - safe_mode F23 - uart3_cts_rc tx - - gpio_163 - - safe_mode F24 - uart3_rts_s d - - - gpio_164 - - safe_mode H24 - uart3_rx_irr x - - - gpio_165 - - safe_mode G24 - uart3_tx_irtx - - - gpio_166 - - safe_mode J23 - hdq_sio sys_altclk i2c2_sccbe i2c3_sccbe gpio_170 - - safe_mode AD15 - i2c4_scl sys_nvmod e1 - - - - - safe_mode W16 - i2c4_sda sys_nvmod e2 - - - - - safe_mode F3 - sys_boot0 - - - gpio_2 - - safe_mode D3 - sys_boot1 - - - gpio_3 - - safe_mode C3 - sys_boot2 - - - gpio_4 - - safe_mode E3 - sys_boot3 - - - gpio_5 - - safe_mode E4 - sys_boot4 mmc2_dir_d at2 - gpio_6 - - safe_mode G3 - sys_boot5 mmc2_dir_d at3 - gpio_7 - - safe_mode D4 - sys_boot6 - - gpio_8 - - safe_mode Submit Documentation Feedback - TERMINAL DESCRIPTION 79 PRODUCT PREVIEW Table 2-5. Multiplexing Characteristics (CBC Pkg.) (continued) OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-5. Multiplexing Characteristics (CBC Pkg.) (continued) PRODUCT PREVIEW Ball Bottom Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 AE14 - sys_clkout1 - - - gpio_10 - - safe_mode W11 - sys_clkout2 - - - gpio_186 - - safe_mode W15 - sys_clkreq - - - gpio_1 - - safe_mode V16 - sys_nirq - - - gpio_0 - - safe_mode V13 - sys_nrespw ron - - - - - - - AD7 - sys_nreswa rm - - - gpio_30 - - safe_mode V12 - sys_off_mo de - - - gpio_9 - - safe_mode AF19 - sys_xtalin - - - - - - - D6 - bg_testout - - - - - - - N18 - pbias_mmc 1 - - - - - - - K23 - pbias_sim - - - - - - - B1 - sys_ipmcsw s - - - - - - A2 - sys_opmcs ws - - - - - - - W26 - tv_out1 - - - - - - - V26 - tv_out2 - - - - - - - W25 - tv_vfb1 - - - - - - - U24 - tv_vfb2 - - - - - - - V23 - tv_vref - - - - - - - AE20 - sys_32k - - - - - - - A24 - cam_d2 - - - gpio_101 hw_dbg4 - safe_mode B24 - cam_d3 - - - gpio_102 hw_dbg5 - safe_mode D24 - cam_d4 - - - gpio_103 hw_dbg6 - safe_mode C24 - cam_d5 - - - gpio_104 hw_dbg7 - safe_mode D25 - cam_d10 - - - gpio_109 hw_dbg8 - safe_mode E26 - cam_d11 - - - gpio_110 hw_dbg9 - safe_mode B23 - cam_fld - cam_global _reset - gpio_98 hw_dbg3 - safe_mode C23 - cam_hs - - - gpio_94 hw_dbg0 - safe_mode C26 - cam_pclk - - - gpio_97 hw_dbg2 - safe_mode D26 - cam_strobe - - - gpio_126 hw_dbg11 - safe_mode C25 - cam_xclka - - - gpio_96 - - safe_mode E25 - cam_xclkb - - - gpio_111 - - safe_mode P25 - cam_d6 - - - gpio_105 - - safe_mode P26 - cam_d7 - - - gpio_106 - - safe_mode N25 - cam_d8 - - - gpio_107 - - safe_mode N26 - cam_d9 - - - gpio_108 - - safe_mode D23 - cam_vs - - - gpio_95 hw_dbg1 - safe_mode A23 - cam_wen - cam_shutter - gpio_167 hw_dbg10 - safe_mode F26 - dss_acbias - - - gpio_69 - - safe_mode G26 - dss_data6 - uart1_tx - gpio_76 hw_dbg14 - safe_mode H25 - dss_data7 - uart1_rx - gpio_77 hw_dbg15 - safe_mode H26 - dss_data8 - - - gpio_78 hw_dbg16 - safe_mode J26 - dss_data9 - - - gpio_79 hw_dbg17 - safe_mode 80 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Ball Bottom Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 L25 - dss_data16 - - - gpio_86 - - safe_mode L26 - dss_data17 - - - gpio_87 - - safe_mode M24 - dss_data18 - mcspi3_clk dss_data0 gpio_88 - - safe_mode M26 - dss_data19 - mcspi3_sim o dss_data1 gpio_89 - - safe_mode N24 - dss_data21 - mcspi3_cs0 dss_data3 gpio_91 - - safe_mode K24 - dss_hsync - - - gpio_67 hw_dbg13 - safe_mode M25 - dss_vsync - - - gpio_68 - - safe_mode R8 - mcspi1_cs1 - - mmc3_cmd gpio_175 - - safe_mode T8 - mcspi1_cs3 - hsusb2_tll_ data2 hsusb2_dat a2 gpio_177 mm2_txdat - safe_mode V9 - mcspi2_cs1 gpt8_pwm_ evt hsusb2_tll_ data3 hsusb2_dat a3 gpio_182 mm2_txen_ n - safe_mode T19 - mcbsp_clks - cam_shutter - gpio_160 uart1_cts - safe_mode AB2 - etk_clk mcbsp5_clk x mmc3_clk hsusb1_stp gpio_12 mm1_rxdp hsusb1_tll_ stp hw_dbg0 AB3 - etk_ctl - mmc3_cmd hsusb1_clk gpio_13 - hsusb1_tll_ clk hw_dbg1 AC3 - etk_d0 mcspi3_sim o mmc3_dat4 hsusb1_dat a0 gpio_14 mm1_rxrcv hsusb1_tll_ data0 hw_dbg2 AD4 - etk_d1 mcspi3_so mi - hsusb1_dat a1 gpio_15 mm1_txse0 hsusb1_tll_ data1 hw_dbg3 AD3 - etk_d2 mcspi3_cs0 - hsusb1_dat a2 gpio_16 mm1_txdat hsusb1_tll_ data2 hw_dbg4 AA3 - etk_d3 mcspi3_clk mmc3_dat3 hsusb1_dat a7 gpio_17 - hsusb1_tll_ data7 hw_dbg5 Y3 - etk_d4 mcbsp5_dr mmc3_dat0 hsusb1_dat a4 gpio_18 - hsusb1_tll_ data4 hw_dbg6 AB1 - etk_d5 mcbsp5_fsx mmc3_dat1 hsusb1_dat a5 gpio_19 - hsusb1_tll_ data5 hw_dbg7 AE3 - etk_d6 mcbsp5_dx mmc3_dat2 hsusb1_dat a6 gpio_20 - hsusb1_tll_ data6 hw_dbg8 AD2 - etk_d7 mcspi3_cs1 mmc3_dat7 hsusb1_dat a3 gpio_21 mm1_txen_ n hsusb1_tll_ data3 hw_dbg9 AA4 - etk_d8 sys_drm_m secure mmc3_dat6 hsusb1_dir gpio_22 - hsusb1_tll_ dir hw_dbg10 V2 - etk_d9 sys_secure _indicator mmc3_dat5 hsusb1_nxt gpio_23 mm1_rxdm hsusb1_tll_ nxt hw_dbg11 AE4 - etk_d10 - uart1_rx hsusb2_clk gpio_24 - hsusb2_tll_ clk hw_dbg12 AF6 - etk_d11 - - hsusb2_stp gpio_25 mm2_rxdp hsusb2_tll_ stp hw_dbg13 AE6 - etk_d12 - - hsusb2_dir gpio_26 - hsusb2_tll_ dir hw_dbg14 AF7 - etk_d13 - - hsusb2_nxt gpio_27 mm2_rxdm hsusb2_tll_ nxt hw_dbg15 AF9 - etk_d14 - - hsusb2_dat a0 gpio_28 mm2_rxrcv hsusb2_tll_ data0 hw_dbg16 AE9 - etk_d15 - - hsusb2_dat a1 gpio_29 mm2_txse0 hsusb2_tll_ data1 hw_dbg17 Y15 - jtag_emu0 - - - gpio_11 - - safe_mode Y14 - jtag_emu1 - - - gpio_31 - - safe_mode Submit Documentation Feedback TERMINAL DESCRIPTION 81 PRODUCT PREVIEW Table 2-5. Multiplexing Characteristics (CBC Pkg.) (continued) OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-5. Multiplexing Characteristics (CBC Pkg.) (continued) PRODUCT PREVIEW Ball Bottom Ball Top Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 U3 - mcbsp3_clk x uart2_tx - - gpio_142 hsusb3_tll_ data6 - safe_mode N3 - mcbsp3_dr uart2_rts - - gpio_141 hsusb3_tll_ data5 - safe_mode P3 - mcbsp3_dx uart2_cts - - gpio_140 hsusb3_tll_ data4 - safe_mode W3 - mcbsp3_fsx uart2_rx - - gpio_143 hsusb3_tll_ data7 - safe_mode V3 - mcbsp4_clk x - - - gpio_152 hsusb3_tll_ data1 mm3_txse0 safe_mode U4 - mcbsp4_dr - - - gpio_153 hsusb3_tll_ data0 mm3_rxrcv safe_mode R3 - mcbsp4_dx - - - gpio_154 hsusb3_tll_ data2 mm3_txdat safe_mode T3 - mcbsp4_fsx - - - gpio_155 hsusb3_tll_ data3 mm3_txen_ n safe_mode M3 - mmc2_dat5 mmc2_dir_d cam_global at1 _reset mmc3_dat1 gpio_137 hsusb3_tll_ stp mm3_rxdp safe_mode L3 - mmc2_dat6 mmc2_dir_c cam_shutter mmc3_dat2 md gpio_138 hsusb3_tll_ dir - safe_mode K3 - mmc2_dat7 mmc2_clkin - mmc3_dat3 gpio_139 hsusb3_tll_ nxt mm3_rxdm safe_mode W2 - uart1_cts - - - gpio_150 hsusb3_tll_ clk - safe_mode 82 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Ball Bottom Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 D7 sdrc_d0 - - - - - - - C5 sdrc_d1 - - - - - - - C6 sdrc_d2 - - - - - - - B5 sdrc_d3 - - - - - - - (1) D9 sdrc_d4 - - - - - - - D10 sdrc_d5 - - - - - - - C7 sdrc_d6 - - - - - - - B7 sdrc_d7 - - - - - - - B11 sdrc_d8 - - - - - - - C12 sdrc_d9 - - - - - - - B12 sdrc_d10 - - - - - - - D13 sdrc_d11 - - - - - - - C13 sdrc_d12 - - - - - - - B14 sdrc_d13 - - - - - - - A14 sdrc_d14 - - - - - - - B15 sdrc_d15 - - - - - - - C9 sdrc_d16 - - - - - - - E12 sdrc_d17 - - - - - - - B8 sdrc_d18 - - - - - - - B9 sdrc_d19 - - - - - - - C10 sdrc_d20 - - - - - - - B10 sdrc_d21 - - - - - - - D12 sdrc_d22 - - - - - - - E13 sdrc_d23 - - - - - - - E15 sdrc_d24 - - - - - - - D15 sdrc_d25 - - - - - - - C15 sdrc_d26 - - - - - - - B16 sdrc_d27 - - - - - - - C16 sdrc_d28 - - - - - - - D16 sdrc_d29 - - - - - - - B17 sdrc_d30 - - - - - - - B18 sdrc_d31 - - - - - - - C18 sdrc_ba0 - - - - - - - D18 sdrc_ba1 - - - - - - - A4 sdrc_a0 - - - - - - - B4 sdrc_a1 - - - - - - - D6 sdrc_a2 - - - - - - - B3 sdrc_a3 - - - - - - - B2 sdrc_a4 - - - - - - - C3 sdrc_a5 - - - - - - - E3 sdrc_a6 - - - - - - - F6 sdrc_a7 - - - - - - - E10 sdrc_a8 - - - - - - - E9 sdrc_a9 - - - - - - - E7 sdrc_a10 - - - - - - - PRODUCT PREVIEW Table 2-6. Multiplexing Characteristics (CUS Pkg.) (1) NA in table stands for Not Applicable. Submit Documentation Feedback TERMINAL DESCRIPTION 83 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-6. Multiplexing Characteristics (CUS Pkg.) (continued) PRODUCT PREVIEW 84 Ball Bottom Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 G6 sdrc_a11 - - - - - - - G7 sdrc_a12 - - - - - - - F7 sdrc_a13 - - - - - - - F9 sdrc_a14 - - - - - - - A19 sdrc_ncs0 - - - - - - - B19 sdrc_ncs1 - - - - - - - A10 sdrc_clk - - - - - - - A11 sdrc_nclk - - - - - - - B20 sdrc_cke0 - - - - - - safe_mode C20 sdrc_cke1 - - - - - - safe_mode D19 sdrc_nras - - - - - - - C19 sdrc_ncas - - - - - - - A20 sdrc_nwe - - - - - - - B6 sdrc_dm0 - - - - - - - B13 sdrc_dm1 - - - - - - - A7 sdrc_dm2 - - - - - - - A16 sdrc_dm3 - - - - - - - A5 sdrc_dqs0 - - - - - - - A13 sdrc_dqs1 - - - - - - - A8 sdrc_dqs2 - - - - - - - A17 sdrc_dqs3 - - - - - - - K4 gpmc_a1 - - - gpio_34 - - safe_mode K3 gpmc_a2 - - - gpio_35 - - safe_mode K2 gpmc_a3 - - - gpio_36 - - safe_mode J4 gpmc_a4 - - - gpio_37 - - safe_mode J3 gpmc_a5 - - - gpio_38 - - safe_mode J2 gpmc_a6 - - - gpio_39 - - safe_mode J1 gpmc_a7 - - - gpio_40 - - safe_mode H1 gpmc_a8 - - - gpio_41 - - safe_mode H2 gpmc_a9 sys_ ndmareq2 - - gpio_42 - - safe_mode G2 gpmc_a10 sys_ ndmareq3 - - gpio_43 - - safe_mode L2 gpmc_d0 - - - - - - - M1 gpmc_d1 - - - - - - - M2 gpmc_d2 - - - - - - - N2 gpmc_d3 - - - - - - - M3 gpmc_d4 - - - - - - - P1 gpmc_d5 - - - - - - - P2 gpmc_d6 - - - - - - - R1 gpmc_d7 - - - - - - - R2 gpmc_d8 - - - gpio_44 - - safe_mode T2 gpmc_d9 - - - gpio_45 - - safe_mode U1 gpmc_d10 - - - gpio_46 - - safe_mode R3 gpmc_d11 - - - gpio_47 - - safe_mode T3 gpmc_d12 - - - gpio_48 - - safe_mode U2 gpmc_d13 - - - gpio_49 - - safe_mode TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Ball Bottom Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 V1 gpmc_d14 - - - gpio_50 - - safe_mode V2 gpmc_d15 - - - gpio_51 - - safe_mode E2 gpmc_ncs0 - - - - - - - D2 gpmc_ncs3 sys_ ndmareq0 - - gpio_54 - - safe_mode F4 gpmc_ncs4 sys_ ndmareq1 mcbsp4_clkx gpt9_pwm_ evt gpio_55 - - safe_mode G5 gpmc_ncs5 sys_ ndmareq2 mcbsp4_dr gpt10_pwm_ evt gpio_56 - - safe_mode F3 gpmc_ncs6 sys_ ndmareq3 mcbsp4_dx gpt11_pwm_ evt gpio_57 - - safe_mode G4 gpmc_ncs7 gpmc_io_dir mcbsp4_fsx gpt8_pwm_ evt gpio_58 - - safe_mode W2 gpmc_clk - - - gpio_59 - - safe_mode F1 gpmc_nadv_a le - - - - - - - F2 gpmc_noe - - - - - - G3 gpmc_nwe - - - - - - - K5 gpmc_nbe0_c le - - - gpio_60 - - safe_mode L1 gpmc_nbe1 - - - gpio_61 - - safe_mode E1 gpmc_nwp - - - gpio_62 - - safe_mode C1 gpmc_wait0 - - - - - - - C2 gpmc_wait3 sys_ ndmareq1 - - gpio_65 - - safe_mode G22 dss_pclk - - - gpio_66 - - safe_mode E22 dss_hsync - - - gpio_67 - - safe_mode F22 dss_vsync - - - gpio_68 - - safe_mode J21 dss_acbias - - - gpio_69 - - safe_mode AC19 dss_data0 - uart1_cts - gpio_70 - - safe_mode AB19 dss_data1 - uart1_rts - gpio_71 - - safe_mode AD20 dss_data2 - - - gpio_72 - - safe_mode AC20 dss_data3 - - - gpio_73 - - safe_mode AD21 dss_data4 - uart3_rx_irrx - gpio_74 - - safe_mode AC21 dss_data5 - uart3_tx_irtx - gpio_75 - - safe_mode D24 dss_data6 - uart1_tx - gpio_76 - - safe_mode E23 dss_data7 - uart1_rx - gpio_77 - - safe_mode E24 dss_data8 - - - gpio_78 - - safe_mode F23 dss_data9 - - - gpio_79 - - safe_mode AC22 dss_data10 - - - gpio_80 - - safe_mode AC23 dss_data11 - - - gpio_81 - - safe_mode AB22 dss_data12 - - - gpio_82 - - safe_mode Y22 dss_data13 - - - gpio_83 - - safe_mode W22 dss_data14 - - - gpio_84 - - safe_mode V22 dss_data15 - - - gpio_85 - - safe_mode J22 dss_data16 - - - gpio_86 - - safe_mode G23 dss_data17 - - - gpio_87 - - safe_mode G24 dss_data18 - mcspi3_clk dss_data0 gpio_88 - - safe_mode H23 dss_data19 - mcspi3_simo dss_data1 gpio_89 - - safe_mode Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW Table 2-6. Multiplexing Characteristics (CUS Pkg.) (continued) 85 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-6. Multiplexing Characteristics (CUS Pkg.) (continued) PRODUCT PREVIEW 86 Ball Bottom Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 D23 dss_data20 - mcspi3_somi dss_data2 gpio_90 - - safe_mode K22 dss_data21 - mcspi3_cs0 dss_data3 gpio_91 - - safe_mode V21 dss_data22 - mcspi3_cs1 dss_data4 gpio_92 - - safe_mode W21 dss_data23 - - dss_data5 gpio_93 - - safe_mode AA23 tv_out2 - - - - - - - AB24 tv_out1 - - - - - - - AB23 tv_vfb1 - - - - - - - Y23 tv_vfb2 - - - - - - - Y24 tv_vref - - - - - - - A22 cam_hs - - - gpio_94 - - safe_mode E18 cam_vs - - - gpio_95 - - safe_mode B22 cam_xclka - - - gpio_96 - - safe_mode J19 cam_pclk - - - gpio_97 - - safe_mode H24 cam_fld - cam_global_r eset - gpio_98 - - safe_mode AB18 cam_d0 - - - gpio_99 - - safe_mode AC18 cam_d1 - - - gpio_100 - - safe_mode G19 cam_d2 - - - gpio_101 - - safe_mode F19 cam_d3 - - - gpio_102 - - safe_mode G20 cam_d4 - - - gpio_103 - - safe_mode B21 cam_d5 - - - gpio_104 - - safe_mode L24 cam_d6 - - - gpio_105 - - safe_mode K24 cam_d7 - - - gpio_106 - - safe_mode J23 cam_d8 - - - gpio_107 - - safe_mode K23 cam_d9 - - - gpio_108 - - safe_mode F21 cam_d10 - - - gpio_109 - - safe_mode G21 cam_d11 - - - gpio_110 - - safe_mode C22 cam_xclkb - - - gpio_111 - - safe_mode F18 cam_wen - cam_shutter - gpio_167 - - safe_mode J20 cam_strobe - - - gpio_126 - - safe_mode V20 mcbsp2_fsx - - - gpio_116 - - safe_mode T21 mcbsp2_clkx - - - gpio_117 - - safe_mode V19 mcbsp2_dr - - - gpio_118 - - safe_mode R20 mcbsp2_dx - - - gpio_119 - - safe_mode M23 mmc1_clk - - - gpio_120 - - safe_mode L23 mmc1_cmd - - - gpio_121 - - safe_mode M22 mmc1_dat0 - - - gpio_122 - - safe_mode M21 mmc1_dat1 - - - gpio_123 - - safe_mode M20 mmc1_dat2 - - - gpio_124 - - safe_mode N23 mmc1_dat3 - - - gpio_125 - - safe_mode N22 mmc1_dat4 - - - gpio_126 - - safe_mode N21 mmc1_dat5 - - - gpio_127 - - safe_mode N20 mmc1_dat6 - - - gpio_128 - - safe_mode P24 mmc1_dat7 - - - gpio_129 - - safe_mode Y1 mmc2_clk mcspi3_clk - - gpio_130 - - safe_mode AB5 mmc2_cmd mcspi3_simo - - gpio_131 - - safe_mode AB3 mmc2_dat0 mcspi3_somi - - gpio_132 - - safe_mode TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Ball Bottom Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Y3 mmc2_dat1 - - - gpio_133 - - safe_mode W3 mmc2_dat2 mcspi3_cs1 - - gpio_134 - - safe_mode V3 mmc2_dat3 mcspi3_cs0 - - gpio_135 - - safe_mode AB2 mmc2_dat4 mmc2_dir_ dat0 - mmc3_dat0 gpio_136 - - safe_mode AA2 mmc2_dat5 mmc2_dir_ dat1 cam_global_r eset mmc3_dat1 gpio_137 - - safe_mode Y2 mmc2_dat6 mmc2_dir_ cmd cam_shutter mmc3_dat2 gpio_138 - - safe_mode AA1 mmc2_dat7 mmc2_clkin - mmc3_dat3 gpio_139 - - safe_mode V6 mcbsp3_dx uart2_cts - - gpio_140 - - safe_mode V5 mcbsp3_dr uart2_rts - - gpio_141 - - safe_mode W4 mcbsp3_clkx uart2_tx - - gpio_142 - - safe_mode V4 mcbsp3_fsx uart2_rx - - gpio_143 - - safe_mode W7 uart1_tx - - - gpio_148 - - safe_mode W6 uart1_rts - - - gpio_149 - - safe_mode AC2 uart1_cts - - - gpio_150 - - safe_mode V7 uart1_rx - mcbsp1_clkr mcspi4_clk gpio_151 - - safe_mode W19 mcbsp1_clkr mcspi4_clk - - gpio_156 - - safe_mode AB20 mcbsp1_fsr - cam_global_r eset - gpio_157 - - safe_mode W18 mcbsp1_dx mcspi4_simo mcbsp3_dx - gpio_158 - - safe_mode Y18 mcbsp1_dr mcspi4_somi mcbsp3_dr - gpio_159 - - safe_mode AA18 mcbsp_clks - cam_shutter - gpio_160 uart1_cts - safe_mode AA19 mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx - gpio_161 - - safe_mode V18 mcbsp1_clkx - mcbsp3_clkx - gpio_162 - - safe_mode A23 uart3_cts_rctx - - - gpio_163 - - safe_mode B23 uart3_rts_sd - - - gpio_164 - - safe_mode B24 uart3_rx_irrx - - - gpio_165 - - safe_mode C23 uart3_tx_irtx - - - gpio_166 - - safe_mode R21 hsusb0_clk - - - gpio_120 - - safe_mode R23 hsusb0_stp - - - gpio_121 - - safe_mode P23 hsusb0_dir - - - gpio_122 - - safe_mode R22 hsusb0_nxt - - - gpio_124 - - safe_mode T24 hsusb0_ data0 - uart3_tx_irtx - gpio_125 - - safe_mode T23 hsusb0_ data1 - uart3_rx_irrx - gpio_130 - - safe_mode U24 hsusb0_ data2 - uart3_rts_sd - gpio_131 - - safe_mode U23 hsusb0_ data3 - uart3_cts_ rctx - gpio_169 - - safe_mode W24 hsusb0_ data4 - - - gpio_188 - - safe_mode V23 hsusb0_ data5 - - - gpio_189 - - safe_mode W23 hsusb0_ data6 - - - gpio_190 - - safe_mode T22 hsusb0_ data7 - - - gpio_191 - - safe_mode Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW Table 2-6. Multiplexing Characteristics (CUS Pkg.) (continued) 87 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-6. Multiplexing Characteristics (CUS Pkg.) (continued) PRODUCT PREVIEW 88 Ball Bottom Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 K20 i2c1_scl - - - - - - - K21 i2c1_sda - - - - - - - AC15 i2c2_scl - - - gpio_168 - - safe_mode AC14 i2c2_sda - - - gpio_183 - - safe_mode AC13 i2c3_scl - - - gpio_184 - - safe_mode AC12 i2c3_sda - - - gpio_185 - - safe_mode Y16 i2c4_scl sys_ nvmode1 - - - - - safe_mode Y15 i2c4_sda sys_ nvmode2 - - - - - safe_mode A24 hdq_sio sys_altclk i2c2_sccbe i2c3_sccbe gpio_170 - - safe_mode T5 mcspi1_clk mmc2_dat4 - - gpio_171 - - safe_mode R4 mcspi1_simo mmc2_dat5 - - gpio_172 - - safe_mode T4 mcspi1_somi mmc2_dat6 - - gpio_173 - - safe_mode T6 mcspi1_cs0 mmc2_dat7 - - gpio_174 - - safe_mode R5 mcspi1_cs3 - hsusb2_tll_ data2 hsusb2_ data2 gpio_177 mm2_txdat - safe_mode N5 mcspi2_clk - hsusb2_tll_ data7 hsusb2_ data7 gpio_178 - - safe_mode N4 mcspi2_simo gpt9_pwm_ evt hsusb2_tll_ data4 hsusb2_ data4 gpio_179 - - safe_mode N3 mcspi2_somi gpt10_pwm_ evt hsusb2_tll_ data5 hsusb2_ data5 gpio_180 - - safe_mode M5 mcspi2_cs0 gpt11_pwm_ evt hsusb2_tll_ data6 hsusb2_ data6 gpio_181 - - safe_mode M4 mcspi2_cs1 gpt8_pwm_ evt hsusb2_tll_ data3 hsusb2_ data3 gpio_182 mm2_txen_n - safe_mode AA16 sys_32k - - - - - - - AD15 sys_xtalin - - - - - - - AD14 sys_xtalout - - - - - - - Y13 sys_clkreq - - - gpio_1 - - safe_mode W16 sys_nirq - - - gpio_0 - - safe_mode AA10 sys_nrespwro n - - - - - - - Y10 sys_nreswar m - - - gpio_30 - - safe_mode AB12 sys_boot0 - - - gpio_2 - - safe_mode AC16 sys_boot1 - - - gpio_3 - - safe_mode AD17 sys_boot2 - - - gpio_4 - - safe_mode AD18 sys_boot3 - - - gpio_5 - - safe_mode AC17 sys_boot4 mmc2_dir_ dat2 - - gpio_6 - - safe_mode AB16 sys_boot5 mmc2_dir_ dat3 - - gpio_7 - - safe_mode AA15 sys_boot6 - - - gpio_8 - - safe_mode AD23 sys_off_ mode - - - gpio_9 - - safe_mode Y7 sys_clkout1 - - - gpio_10 - - safe_mode AA6 sys_clkout2 - - - gpio_186 - - safe_mode A1 sys_ipmcsws - - - - - - - TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Ball Bottom Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 A2 sys_ opmcsws - - - - - - - AB7 jtag_ntrst - - - - - - - AB6 jtag_tck - - - - - - - AA7 jtag_rtck - - - - - - - AA9 jtag_tms_ tmsc - - - - - - - AB10 jtag_tdi - - - - - - - AB9 jtag_tdo - - - - - - - AC24 jtag_emu0 - - - gpio_11 - - safe_mode AD24 jtag_emu1 - - - gpio_31 - - safe_mode AC1 etk_clk mcbsp5_clkx mmc3_clk hsusb1_stp gpio_12 mm1_rxdp hsusb1_tll_ stp - AD3 etk_ctl - mmc3_cmd hsusb1_clk gpio_13 - hsusb1_tll_ clk - AD6 etk_d0 mcspi3_simo mmc3_dat4 hsusb1_ data0 gpio_14 mm1_rxrcv hsusb1_tll_ data0 - AC6 etk_d1 mcspi3_somi - hsusb1_ data1 gpio_15 mm1_txse0 hsusb1_tll_ data1 - AC7 etk_d2 mcspi3_cs0 - hsusb1_ data2 gpio_16 mm1_txdat hsusb1_tll_ data2 - AD8 etk_d3 mcspi3_clk mmc3_dat3 hsusb1_ data7 gpio_17 - hsusb1_tll_ data7 - AC5 etk_d4 mcbsp5_dr mmc3_dat0 hsusb1_ data4 gpio_18 - hsusb1_tll_ data4 - AD2 etk_d5 mcbsp5_fsx mmc3_dat1 hsusb1_ data5 gpio_19 - hsusb1_tll_ data5 - AC8 etk_d6 mcbsp5_dx mmc3_dat2 hsusb1_ data6 gpio_20 - hsusb1_tll_ data6 - AD9 etk_d7 mcspi3_cs1 mmc3_dat7 hsusb1_ data3 gpio_21 mm1_txen_n hsusb1_tll_ data3 - AC4 etk_d8 sys_drm_ msecure mmc3_dat6 hsusb1_dir gpio_22 - hsusb1_tll_ dir - AD5 etk_d9 sys_secure_ indicator mmc3_dat5 hsusb1_nxt gpio_23 mm1_rxdm hsusb1_tll_ nxt - AC3 etk_d10 - uart1_rx hsusb2_clk gpio_24 - hsusb2_tll_ clk - AC9 etk_d11 - - hsusb2_stp gpio_25 mm2_rxdp hsusb2_tll_ stp - AC10 etk_d12 - - hsusb2_dir gpio_26 - hsusb2_tll_ dir - AD11 etk_d13 - - hsusb2_nxt gpio_27 mm2_rxdm hsusb2_tll_ nxt - AC11 etk_d14 - - hsusb2_ data0 gpio_28 mm2_rxrcv hsusb2_tll_ data0 - AD12 etk_d15 - - hsusb2_ data1 gpio_29 mm2_txse0 hsusb2_tll_ data1 - Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW Table 2-6. Multiplexing Characteristics (CUS Pkg.) (continued) 89 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 2.4 Signal Description PRODUCT PREVIEW Many signals are available on multiple pins according to the software configuration of the pin multiplexing options. 1. SIGNAL NAME: The signal name 2. DESCRIPTION: Description of the signal 3. TYPE: Type = Ball type for this specific function: – I = Input – O = Output – Z = High-impedance – D = Open Drain – DS = Differential – A = Analog 4. BALL BOTTOM: Associated ball(s) bottom 5. BALL TOP: Associated ball(s) top 6. SUBSYSTEM PIN MULTIPLEXING: Contains a list of the pin multiplexing options at the module/subsystem level. The pin function is selected at the module/system level. Note: The Subsystem Multiplexing Signals are not described in Table 2-1 through Table 2-6. 2.4.1 External Memory Interfaces Table 2-7. External Memory Interfaces – GPMC Signals Description SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] BALL BOTTO M (CBB Pkg.) [4] BALL BALL BALL TOP TOP BOTTOM (CBC Pkg.) [5] (CBB (CBC Pkg.) [4] Pkg.) [5] BALL SUBSYSTEM BOTTO PIN M MULTIPLEXIN (CUS G Pkg.) [4] [6] gpmc_a1 General-purpose memory address bit 1 O N4 / K1 AC15 / M2 J2 / AA2 - / U2 K4/ L2 gpmc_a17/ gpmc_d0 gpmc_a2 General-purpose memory address bit 2 O M4 / L1 AB15 / M1 H1 / AA1 - / U1 K3/ M1 gpmc_a18/ gpmc_d1 gpmc_a3 General-purpose memory address bit 3 O L4 / L2 AC16 / N2 H2 / AC2 - / V2 K2/ M2 gpmc_a19/ gpmc_d2 gpmc_a4 General-purpose memory address bit 4 O K4 / P2 AB16 / N1 G2 / AC1 - / V1 J4/ N2 gpmc_a20/ gpmc_d3 gpmc_a5 General-purpose memory address bit 5 O T3 / T1 AC17 / R2 F1 / AE5 - / AA3 J3/ M3 gpmc_a21/ gpmc_d4 gpmc_a6 General-purpose memory address bit 6 O R3 / V1 AB17 / R1 F2 / AD6 - / AA4 J2/ P1 gpmc_a22/ gpmc_d5 gpmc_a7 General-purpose memory address bit 7 O N3 / V2 AC18 / T2 E1 / AD5 - / Y3 J1/ P2 gpmc_a23/ gpmc_d6 gpmc_a8 General-purpose memory address bit 8 O M3 / W2 AB18 / T1 E2 / AC5 - / Y4 H1/ R1 gpmc_a24/ gpmc_d7 gpmc_a9 General-purpose memory address bit 9 O L3 / H2 AC19 / AB3 D1 / V1 - / R1 H2/ R2 gpmc_a25/ gpmc_d8 gpmc_a10 General-purpose memory address bit 10 O K3 / K2 AB19 / AC3 D2 / Y1 - / T1 G2/ T2 gpmc_a26/ gpmc_d9 gpmc_a11 General-purpose memory address bit 11 O P1 AB4 T1 N1 U1 gpmc_d10 gpmc_a12 General-purpose memory address bit 12 O R1 AC4 U2 P2 R3 gpmc_d11 gpmc_a13 General-purpose memory address bit 13 O R2 AB6 U1 P1 T3 gpmc_d12 gpmc_a14 General-purpose memory address bit 14 O T2 AC6 P1 M1 U2 gpmc_d13 90 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-7. External Memory Interfaces – GPMC Signals Description (continued) DESCRIPTION [2] TYPE [3] BALL BOTTO M (CBB Pkg.) [4] BALL BALL BALL TOP TOP BOTTOM (CBC Pkg.) [5] (CBB (CBC Pkg.) [4] Pkg.) [5] BALL SUBSYSTEM BOTTO PIN M MULTIPLEXIN (CUS G Pkg.) [4] [6] gpmc_a15 General-purpose memory address bit 15 O W1 AB7 L2 J2 V1 gpmc_d14 gpmc_a16 General-purpose memory address bit 16 O Y1 AC7 M2 K2 V2 gpmc_d15 gpmc_a17 General-purpose memory address bit 17 O N4 AC15 J2 - K4 gpmc_a1 gpmc_a18 General-purpose memory address bit 18 O M4 AB15 H1 - K3 gpmc_a2 gpmc_a19 General-purpose memory address bit 19 O L4 AC16 H2 - K2 gpmc_a3 gpmc_a20 General-purpose memory address bit 20 O K4 AB16 G2 - J4 gpmc_a4 gpmc_a21 General-purpose memory address bit 21 O T3 AC17 F1 - J3 gpmc_a5 gpmc_a22 General-purpose memory address bit 22 O R3 AB17 F2 - J2 gpmc_a6 gpmc_a23 General-purpose memory address bit 23 O N3 AC18 E1 - J1 gpmc_a7 gpmc_a24 General-purpose memory address bit 24 O M3 AB18 E2 - H1 gpmc_a8 gpmc_a25 General-purpose memory address bit 25 O L3 AC19 D1 - H2 gpmc_a9 gpmc_a26 General-purpose memory address bit 26 O K3 AB19 D2 - G2 gpmc_a10 gpmc_d0 GPMC Data bit 0 IO K1 M2 AA1 U2 L2 gpmc_a1/ gpmc_d0 gpmc_d1 GPMC Data bit 1 IO L1 M1 AA1 U1 M1 gpmc_a2/ gpmc_d1 gpmc_d2 GPMC Data bit 2 IO L2 N2 AC2 V2 M2 gpmc_a3/ gpmc_d2 gpmc_d3 GPMC Data bit 3 IO P2 N1 AC1 V1 N2 gpmc_a4/ gpmc_d3 gpmc_d4 GPMC Data bit 4 IO T1 R2 AE5 AA3 M3 gpmc_a5/ gpmc_d4 gpmc_d5 GPMC Data bit 5 IO V1 R1 AD6 AA4 P1 gpmc_a6/ gpmc_d5 gpmc_d6 GPMC Data bit 6 IO V2 T2 AD5 Y3 P2 gpmc_a7 /gpmc_d6 gpmc_d7 GPMC Data bit 7 IO W2 T1 AC5 Y4 R1 gpmc_a8/ gpmc_d7 gpmc_d8 GPMC Data bit 8 IO H2 AB3 V1 R1 R2 gpmc_a9/ gpmc_d8 gpmc_d9 GPMC Data bit 9 IO K2 AC3 Y1 T1 T2 gpmc_a10/ gpmc_d9 gpmc_d10 GPMC Data bit 10 IO P1 AB4 T1 N1 U1 gpmc_a11/ gpmc_d10 gpmc_d11 GPMC Data bit 11 IO R1 AC4 U2 P2 R3 gpmc_a12/ gpmc_d11 gpmc_d12 GPMC Data bit 12 IO R2 AB6 U1 P1 T3 gpmc_a13/ gpmc_d12 gpmc_d13 GPMC Data bit 13 IO T2 AC6 P1 M1 U2 gpmc_a14/ gpmc_d13 Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW SIGNAL NAME [1] 91 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-7. External Memory Interfaces – GPMC Signals Description (continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] BALL BOTTO M (CBB Pkg.) [4] BALL BALL BALL TOP TOP BOTTOM (CBC Pkg.) [5] (CBB (CBC Pkg.) [4] Pkg.) [5] BALL SUBSYSTEM BOTTO PIN M MULTIPLEXIN (CUS G Pkg.) [4] [6] PRODUCT PREVIEW gpmc_d14 GPMC Data bit 14 IO W1 AB7 L2 J2 V1 gpmc_a15/ gpmc_d14 gpmc_d15 GPMC Data bit 15 IO Y1 AC7 M2 K2 V2 gpmc_a16/ gpmc_d15 gpmc_ncs0 GPMC Chip Select bit 0 O G4 Y2 AD8 AA8 E2 - gpmc_ncs1 GPMC Chip Select bit 1 O H3 Y1 AD1 W1 NA - gpmc_ncs2 GPMC Chip Select bit 2 O V8 NA A3 - NA - gpmc_ncs3 GPMC Chip Select bit 3 O U8 NA B6 - D2 - gpmc_ncs4 GPMC Chip Select bit 4 O T8 NA B4 - F4 - gpmc_ncs5 GPMC Chip Select bit 5 O R8 NA C4 - G5 - gpmc_ncs6 GPMC Chip Select bit 6 O P8 NA B5 - F3 - gpmc_ncs7 GPMC Chip Select bit 7 O N8 NA C5 - G4 - gpmc_io_dir GPMC IO direction control for use with external transceivers O N8 NA C5 - G4 - gpmc_clk GPMC clock O T4 W2 N1 L1 W2 - gpmc_nadv_ ale Address Valid or Address Latch Enable O F3 W1 AD10 AA9 F1 - gpmc_noe Output Enable O G2 V2 N2 L2 F2 - gpmc_nwe Write Enable O F4 V1 M1 K1 G3 - gpmc_nbe0_ cle Lower Byte Enable. Also used for Command Latch Enable O G3 AC12 K2 - K5 - gpmc_nbe1 Upper Byte Enable O U3 NA J1 - L1 - gpmc_nwp Flash Write Protect O H1 AB10 AC6 Y5 E1 - gpmc_wait0 External indication of wait I M8 AB12 AC11 Y10 C1 - gpmc_wait1 External indication of wait I L8 AC10 AC8 Y8 NA - gpmc_wait2 External indication of wait I K8 NA B3 - NA - gpmc_wait3 External indication of wait I J8 NA C6 - C2 - Table 2-8. External Memory Interfaces – SDRC Signals Description SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL TOP (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL TOP (CBC Pkg.) BALL BOTTOM (CUS Pkg.) J2 - D1 D7 sdrc_d0 SDRAM data bit 0 IO D6 sdrc_d1 SDRAM data bit 1 IO C6 J1 - G1 C5 sdrc_d2 SDRAM data bit 2 IO B6 G2 - G2 C6 sdrc_d3 SDRAM data bit 3 IO C8 G1 - E1 B5 sdrc_d4 SDRAM data bit 4 IO C9 F2 - D2 D9 sdrc_d5 SDRAM data bit 5 IO A7 F1 - E2 D10 sdrc_d6 SDRAM data bit 6 IO B9 D2 - B3 C7 sdrc_d7 SDRAM data bit 7 IO A9 D1 - B4 B7 sdrc_d8 SDRAM data bit 8 IO C14 B13 - A10 B11 sdrc_d9 SDRAM data bit 9 IO B14 A13 - B11 C12 sdrc_d10 SDRAM data bit 10 IO C15 B14 - A11 B12 sdrc_d11 SDRAM data bit 11 IO B16 A14 - B12 D13 sdrc_d12 SDRAM data bit 12 IO D17 B16 - A16 C13 (1) 92 Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog). TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-8. External Memory Interfaces – SDRC Signals Description (continued) TYPE (1) BALL BOTTOM (CBB Pkg.) BALL TOP (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL TOP (CBC Pkg.) BALL BOTTOM (CUS Pkg.) sdrc_d13 SDRAM data bit 13 IO C17 A16 - A17 B14 sdrc_d14 SDRAM data bit 14 IO B17 B19 - B17 A14 sdrc_d15 SDRAM data bit 15 IO D18 A19 - B18 B15 sdrc_d16 SDRAM data bit 16 IO D11 B3 - B7 C9 sdrc_d17 SDRAM data bit 17 IO B10 A3 - A5 E12 sdrc_d18 SDRAM data bit 18 IO C11 B5 - B6 B8 sdrc_d19 SDRAM data bit 19 IO D12 A5 - A6 B9 sdrc_d20 SDRAM data bit 20 IO C12 B8 - A8 C10 sdrc_d21 SDRAM data bit 21 IO A11 A8 -- B9 B10 sdrc_d22 SDRAM data bit 22 IO B13 B9 - A9 D12 sdrc_d23 SDRAM data bit 23 IO D14 A9 - B10 E13 sdrc_d24 SDRAM data bit 24 IO C18 B21 - C21 E15 sdrc_d25 SDRAM data bit 25 IO A19 A21 - D20 D15 sdrc_d26 SDRAM data bit 26 IO B19 D22 - B19 C15 sdrc_d27 SDRAM data bit 27 IO B20 D23 - C20 B16 sdrc_d28 SDRAM data bit 28 IO D20 E22 - D21 C16 sdrc_d29 SDRAM data bit 29 IO A21 E23 - E20 D16 sdrc_d30 SDRAM data bit 30 IO B21 G22 - E21 B17 sdrc_d31 SDRAM data bit 31 IO C21 G23 - G21 B18 sdrc_ba0 SDRAM bank select 0 O H9 AB21 - AA18 C18 sdrc_ba1 SDRAM bank select 1 O H10 AC21 - V20 D18 sdrc_a0 SDRAM address bit 0 O A4 N22 - G20 A4 sdrc_a1 SDRAM address bit 1 O B4 N23 - K20 B4 sdrc_a2 SDRAM address bit 2 O B3 P22 - J20 D6 sdrc_a3 SDRAM address bit 3 O C5 P23 - J21 B3 sdrc_a4 SDRAM address bit 4 O C4 R22 - U21 B2 sdrc_a5 SDRAM address bit 5 O D5 R23 - R20 C3 sdrc_a6 SDRAM address bit 6 O C3 T22 - M21 E3 sdrc_a7 SDRAM address bit 7 O C2 T23 - M20 F6 sdrc_a8 SDRAM address bit 8 O C1 U22 - N20 E10 sdrc_a9 SDRAM address bit 9 O D4 U23 - K21 E9 sdrc_a10 SDRAM address bit 10 O D3 V22 - Y16 E7 sdrc_a11 SDRAM address bit 11 O D2 V23 - N21 G6 sdrc_a12 SDRAM address bit 12 O D1 W22 - R21 G7 sdrc_a13 SDRAM address bit 13 O E2 W23 - AA15 F7 Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW DESCRIPTION SIGNAL NAME 93 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-8. External Memory Interfaces – SDRC Signals Description (continued) DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL TOP (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL TOP (CBC Pkg.) BALL BOTTOM (CUS Pkg.) sdrc_a14 SDRAM address bit 14 O E1 Y22 - Y12 F9 sdrc_ncs0 Chip select 0 O H11 M22 - T21 A19 sdrc_ncs1 Chip select 1 O H12 M23 - T20 B19 sdrc_clk Clock IO A13 A11 - A12 A10 sdrc_nclk Clock Invert O A14 B11 - B13 A11 sdrc_cke0 Clock Enable 0 O H16 J22 - Y15 B20 sdrc_cke1 Clock Enable 1 O H17 J23 - Y13 C20 sdrc_nras SDRAM Row Access O H14 L23 - V21 D19 sdrc_ncas SDRAM column address strobe O H13 L22 - U20 C19 sdrc_nwe SDRAM write enable O H15 K23 - Y18 A20 sdrc_dm0 Data Mask 0 O B7 C1 - H1 B6 sdrc_dm1 Data Mask 1 O A16 A17 - A14 B13 sdrc_dm2 Data Mask 2 O B11 A6 - A4 A7 sdrc_dm3 Data Mask 3 O C20 A20 - A18 A16 sdrc_dqs0 Data Strobe 0 IO A6 C2 - C2 A5 sdrc_dqs1 Data Strobe 1 IO A17 B17 - B15 A13 sdrc_dqs2 Data Strobe 2 IO A10 B6 - B8 A8 sdrc_dqs3 Data Strobe 3 IO A20 B20 - A19 A17 SIGNAL NAME PRODUCT PREVIEW 94 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com 2.4.2 SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Video Interfaces SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) A24 C23 A22 E18 cam_hs Camera Horizontal Synchronization IO cam_vs Camera Vertical Synchronization IO A23 D23 cam_xclka Camera Clock Output a O C25 C25 B22 cam_xclkb Camera Clock Output b O B26 E25 C22 cam_d0 Camera digital image data bit 0 I AG17 AE16 AB18 cam_d1 Camera digital image data bit 1 I AH17 AE15 AC18 cam_d2 Camera digital image data bit 2 I B24 A24 G19 cam_d3 Camera digital image data bit 3 I C24 B24 F19 cam_d4 Camera digital image data bit 4 I D24 D24 G20 cam_d5 Camera digital image data bit 5 I A25 C24 B21 cam_d6 Camera digital image data bit 6 I K28 P25 L24 cam_d7 Camera digital image data bit 7 I L28 P26 K24 cam_d8 Camera digital image data bit 8 I K27 N25 J23 cam_d9 Camera digital image data bit 9 I L27 N26 K23 cam_d10 Camera digital image data bit 10 I B25 D25 F21 cam_d11 Camera digital image data bit 11 I C26 E26 G21 cam_fld Camera field identification IO C23 B23 H24 cam_pclk Camera pixel clock I C27 C26 J19 cam_wen Camera Write Enable I B23 A23 F18 cam_strobe Flash strobe control signal O D25 D26 J20 cam_global_res et Global reset is used strobe synchronization IO C23 / AH3 / AA21 V17 / B23 H24/ AA2/ AB20 cam_shutter Mechanical shutter control signal O B23 / AF3 / T21 A23 / T19 F18/ Y2/ AA18 (1) PRODUCT PREVIEW Table 2-9. Video Interfaces – CAM Signals Description Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog). Table 2-10. Video Interfaces – DSS Signals Description SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) dss_pclk LCD Pixel Clock O D28 G25 G22 dss_hsync LCD Horizontal Synchronization O D26 K24 E22 dss_vsync LCD Vertical Synchronization O D27 M25 F22 dss_acbias AC bias control (STN) or pixel data enable (TFT) output O E27 F26 J21 dss_data0 LCD Pixel Data bit 0 IO AG22 / H26 AE21 / M24 AC19 dss_data1 LCD Pixel Data bit 1 IO AH22 / H25 AE22 / M26 AB19 dss_data2 LCD Pixel Data bit 2 IO AG23 / E28 AE23 / F25 AD20 dss_data3 LCD Pixel Data bit 3 IO AH23 / J26 AE24 / N24 AC20 dss_data4 LCD Pixel Data bit 4 IO AG24 / AC27 AD23 / AC25 AD21 dss_data5 LCD Pixel Data bit 5 IO AH24 / AC28 AD24/ AB25 AC21 dss_data6 LCD Pixel Data bit 6 IO E26 G26 D24 dss_data7 LCD Pixel Data bit 7 IO F28 H25 E23 dss_data8 LCD Pixel Data bit 8 IO F27 H26 E24 dss_data9 LCD Pixel Data bit 9 IO G26 J26 F23 (1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog). Submit Documentation Feedback TERMINAL DESCRIPTION 95 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-10. Video Interfaces – DSS Signals Description (continued) SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) PRODUCT PREVIEW dss_data10 LCD Pixel Data bit 10 IO AD28 AC26 AC22 dss_data11 LCD Pixel Data bit 11 IO AD27 AD26 AC23 dss_data12 LCD Pixel Data bit 12 IO AB28 AA25 AB22 dss_data13 LCD Pixel Data bit 13 IO AB27 Y25 Y22 dss_data14 LCD Pixel Data bit 14 IO AA28 AA26 W22 dss_data15 LCD Pixel Data bit 15 IO AA27 AB26 V22 dss_data16 LCD Pixel Data bit 16 IO G25 L25 J22 dss_data17 LCD Pixel Data bit 17 IO H27 L26 G23 dss_data18 LCD Pixel Data bit 18 IO H26 M24 G24 dss_data19 LCD Pixel Data bit 19 IO H25 M26 H23 dss_data20 LCD Pixel Data bit 20 O E28 F25 D23 dss_data21 LCD Pixel Data bit 21 O J26 N24 K22 dss_data22 LCD Pixel Data bit 22 O AC27 AC25 V21 dss_data23 LCD Pixel Data bit 23 O AC28 AB25 W21 Table 2-11. Video Interfaces – RFBI Signals Description SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM BALL BOTTOM BALL BOTTOM (CBB Pkg.) (CBC Pkg.) (CUS Pkg.) SUBSYSTEM PIN MULTIPLEXING (2) rfbi_a0 RFBI command/data control O E27 F26 J21 dss_acbias rfbi_cs0 1st LCD chip select O D26 K24 E22 dss_hsync rfbi_da0 RFBI data bus 0 IO AG22 AE21 AC19 dss_data0 rfbi_da1 RFBI data bus 1 IO AH22 AE22 AB19 dss_data1 rfbi_da2 RFBI data bus 2 IO AG23 AE23 AD20 dss_data2 rfbi_da3 RFBI data bus 3 IO AH23 AE24 AC20 dss_data3 rfbi_da4 RFBI data bus 4 IO AG24 AD23 AD21 dss_data4 rfbi_da5 RFBI data bus 5 IO AH24 AD24 AC21 dss_data5 rfbi_da6 RFBI data bus 6 IO E26 G26 D24 dss_data6 rfbi_da7 RFBI data bus 7 IO F28 H25 E23 dss_data7 rfbi_da8 RFBI data bus 8 IO F27 H26 E24 dss_data8 rfbi_da9 RFBI data bus 9 IO G26 J26 F23 dss_data9 rfbi_da10 RFBI data bus 10 IO AD28 AC26 AC22 dss_data10 rfbi_da11 RFBI data bus 11 IO AD27 AD26 AC23 dss_data11 rfbi_da12 RFBI data bus 12 IO AB28 AA25 AB22 dss_data12 rfbi_da13 RFBI data bus 13 IO AB27 Y25 Y22 dss_data13 rfbi_da14 RFBI data bus 14 IO AA28 AA26 W22 dss_data14 rfbi_da15 RFBI data bus 15 IO AA27 AB26 V22 dss_data15 rfbi_rd Read enable for RFBI O D28 G25 G22 dss_pclk rfbi_wr Write Enable for RFBI O D27 M25 F22 dss_vsync rfbi_te_vsyn tearing effect removal and Vsync c0 input from 1st LCD I G25 L25 J22 dss_data16 rfbi_hsync0 I H27 L26 G23 dss_data17 (1) (2) 96 Hsync for 1st LCD Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog). The subsystem pin multiplexing options are not described in Table 2-1 and Table 2-4 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-12. Video Interfaces – TV Signals Description SIGNAL NAME TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) W26 AB24 tv_out1 TV analog output Composite: tv_out1 O Y28 tv_out2 TV analog output S-VIDEO: tv_out2 O W28 V26 AA23 tv_vfb1 tv_vfb1: Feedback through external resistorto composite O Y27 W25 AB23 tv_vfb2 tv_vfb2: Feedback through external resistorto S-VIDEO O W27 U24 Y23 tv_vref External capacitor I W26 V23 Y24 Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog). PRODUCT PREVIEW (1) DESCRIPTION Submit Documentation Feedback TERMINAL DESCRIPTION 97 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 2.4.3 www.ti.com Serial Communication Interfaces Table 2-13. Serial Communication Interfaces – HDQ/1-Wire Signals Description (1) SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) hdq_sio Bidirectional HDQ 1-Wire control and data Interface. Output is open drain. IOD J25 J23 A24 Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog). Table 2-14. Serial Communication Interfaces – I2C Signals Description SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) INTER-INTEGRATED CIRCUIT INTERFACE (I2C1) PRODUCT PREVIEW i2c1_scl I2C Master Serial clock. Output is open drain. IOD K21 J25 K20 i2c1_sda I2C Serial Bidirectional Data. Output is open drain. IOD J21 J24 K21 INTER-INTEGRATED CIRCUIT INTERFACE (I2C3) i2c3_scl I2C Master Serial clock. Output is open drain. IOD AF14 C2 AC13 i2c3_sda I2C Serial Bidirectional Data. Output is open drain. IOD AG14 C1 AC12 i2c3_sccbe TBD O J25 J23 A24 INTER-INTEGRATED CIRCUIT INTERFACE (I2C2) i2c2_scl I2C Master Serial clock. Output is open drain. IOD AF15 AB4 AC15 i2c2_sda I2C Serial Bidirectional Data. Output is open drain. IOD AE15 AC4 AC14 i2c2_sccbe Serial Camera Control Bus Enable O J25 J23 A24 (1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog). Table 2-15. Serial Communication Interfaces – SmartReflex Signals Description (1) SIGNAL NAME DESCRIPTION TYPE (2) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) INTER-INTEGRATED CIRCUIT INTERFACE (I2C4) i2c4_scl I2C Master Serial clock. Output is open drain. IOD AD26 AD15 Y16 i2c4_sda I2C Serial Bidirectional Data. Output is open drain. IOD AE26 W16 Y15 (1) (2) For more information on SmartReflex voltage control, see the PRCM chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUFA5]. Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog). Table 2-16. Serial Communication Interfaces – McBSP LP Signals Description SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) MULTICHANNEL SERIAL (McBSP LP 1) mcbsp1_dr Received serial data I U21 T20 Y18 mcbsp1_clkr Receive Clock IO Y8 / Y21 U19 / H3 V7 / W19 mcbsp1_fsr Receive frame synchronization IO AA21 V17 AB20 mcbsp1_dx Transmitted serial data IO V21 U17 W18 mcbsp1_clkx Transmit clock IO W21 T17 V18 (1) 98 Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog) TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-16. Serial Communication Interfaces – McBSP LP Signals Description (continued) SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) mcbsp1_fsx Transmit frame synchronization IO K26 P20 AA19 mcbsp_clks External clock input (shared by McBSP1, 2, 3, 4, and 5) I T21 T19 AA18 I R21 T18 V19 R20 MULTICHANNEL SERIAL (McBSP LP 2) mcbsp2_dr Received serial data mcbsp2_dx Transmitted serial data IO M21 R19 mcbsp2_clkx Combined serial clock IO N21 R18 T21 mcbsp2_fsx Combined frame synchronization IO P21 U18 V20 mcbsp3_dr Received serial data I AE6 / AB25 / U21 T20 / AA24 V5 / Y18 mcbsp3_dx Transmitted serial data IO AF6 / AB26 / V21 U17 / Y24 V6 / W18 mcbsp3_clkx Combined serial clock IO AF5 / AA25 / W21 T17 / AD22 W4 / V18 mcbsp3_fsx Combined frame synchronization IO AE5 / AD25 / K26 P20 / AD21 V4 / AA19 I R8 / AD1 C4 G5 F3 PRODUCT PREVIEW MULTICHANNEL SERIAL (McBSP LP 3) MULTICHANNEL SERIAL (McBSP LP 4) mcbsp4_dr Received serial data mcbsp4_dx Transmitted serial data IO P8 / AD2 B5 mcbsp4_clkx Combined serial clock IO T8 / AE1 B4 F4 mcbsp4_fsx Combined frame synchronization IO N8 / AC1 C5 G4 MULTICHANNEL SERIAL (McBSP LP 5) mcbsp5_dr Received serial data I AE11 Y3 AC5 mcbsp5_dx Transmitted serial data IO AF13 AE3 AC8 mcbsp5_clkx Combined serial clock IO AF10 AB2 AC1 mcbsp5_fsx Combined frame synchronization IO AH9 AB1 AD2 Table 2-17. Serial Communication Interfaces – McSPI Signals Description SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) MULTICHANNEL SERIAL PORT INTERFACE (McSPI1) mcspi1_clk SPI Clock IO AB3 P9 T5 mcspi1_simo Slave data in, master data out IO AB4 P8 R4 mcspi1_somi Slave data out, master data in IO AA4 P7 T4 mcspi1_cs0 SPI Enable 0, polarity configured by software IO AC2 R7 T6 mcspi1_cs1 SPI Enable 1, polarity configured by software O AC3 R8 NA mcspi1_cs2 SPI Enable 2, polarity configured by software O AB1 R9 NA mcspi1_cs3 SPI Enable 3, polarity configured by software O AB2 T8 R5 MULTICHANNEL SERIAL PORT INTERFACE (McSPI2) mcspi2_clk SPI Clock IO AA3 W7 N5 mcspi2_simo Slave data in, master data out IO Y2 W8 N4 mcspi2_somi Slave data out, master data in IO Y3 U8 N3 mcspi2_cs0 SPI Enable 0, polarity configured by software IO Y4 V8 M5 mcspi2_cs1 SPI Enable 1, polarity configured by software O V3 V9 M4 MULTICHANNEL SERIAL PORT INTERFACE (McSPI3) (1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog) Submit Documentation Feedback TERMINAL DESCRIPTION 99 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-17. Serial Communication Interfaces – McSPI Signals Description (continued) SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) H26 / AE2 / AE13 W10 / M24 / AA3 G24 / Y1 / AD8 mcspi3_clk SPI Clock IO mcspi3_simo Slave data in, master data out IO H25 / AG5 / AF11 R10 / M26 / AC3 H23 / AB5 / AD6 mcspi3_somi Slave data out, master data in IO E28 / AH5 / AG12 F25 / T10 / AD4 D23 / AB3 / AC6 mcspi3_cs0 SPI Enable 0, polarity configured by software IO J26 / AF4 / AH12 U9 / N24 / AD3 K22 / V3 / AC7 mcspi3_cs1 SPI Enable 1, polarity configured by software O AC27 / AG4 / AH14 AC25 / U10 / AD2 V21 / W3 / AD9 MULTICHANNEL SERIAL PORT INTERFACE (McSPI4) PRODUCT PREVIEW mcspi4_clk SPI Clock IO Y8 / Y21 U19 / H3 V7 / W19 mcspi4_simo Slave data in, master data out IO V21 U17 W18 mcspi4_somi Slave data out, master data in IO U21 T20 Y18 mcspi4_cs0 SPI Enable 0, polarity configured by software IO K26 P20 AA19 Table 2-18. Serial Communication Interfaces – UARTs Signals Description SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) AG22 / W8 / T21 AE21 / T19 AC19 / AC2 / AA18 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART1) uart1_cts UART1 Clear To Send I uart1_rts UART1 Request To Send O AH22 / AA9 AE22 / R2 W6 / AB19 uart1_rx UART1 Receive data I F28 / Y8 / AE7 H3 / H25 / AE4 E23 / V7 / AC3 uart1_tx UART1 Transmit data O E26 / AA8 L4 / G26 D24 / W7 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART2) uart2_cts UART2 Clear To Send I AF6 / AB26 Y24 V6 uart2_rts UART2 Request To Send O AE6 / AB25 AA24 V5 uart2_rx UART2 Receive data I AE5 / AD25 AD21 V4 uart2_tx UART2 Transmit data O AF5 / AA25 AD22 W4 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART3) / IrDA uart3_cts_rct x UART3 Clear To Send (input), Remote TX (output) IO H18 / U26 W20 / F23 A23 / U23 uart3_rts_sd UART3 Request To Send, IR enable O H19 / U27 V18 / F24 B23 / U24 uart3_rx_irrx UART3 Receive data, IR and Remote RX I AG24 / H20 / U28 AD23 / Y20 / H24 AD21 / B24 / T23 uart3_tx_irtx UART3 Transmit data, IR TX O AH24 / H21 / T27 AD24/ V20 / G24 AC21 / C23 / T24 (1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog) Table 2-19. Serial Communication Interfaces – USB Signals Description SIGNAL NAME DESCRIPTION TYPE ( 1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) T28 W19 R21 HIGH-SPEED UNIVERSAL SERIAL BUS INTERFACE (HSUSB0) hsusb0_clk Dedicated for external transceiver 60-MHz clock input from PHY I hsusb0_stp Dedicated for external transceiver Stop signal O T25 U20 R23 hsusb0_dir Dedicated for external transceiver Data direction control from PHY I R28 V19 P23 hsusb0_nxt Dedicated for external transceiver Next signal from PHY I T26 W18 R22 (1) 100 Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog) TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-19. Serial Communication Interfaces – USB Signals Description (continued) DESCRIPTION TYPE ( 1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) hsusb0_data0 Dedicated for external transceiver Bidirectional data bus IO T27 V20 T24 hsusb0_data1 Dedicated for external transceiver Bidirectional data bus IO U28 Y20 T23 hsusb0_data2 Dedicated for external transceiver Bidirectional data bus IO U27 V18 U24 hsusb0_data3 Dedicated for external transceiver Bidirectional data bus IO U26 W20 U23 hsusb0_data4 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO U25 W17 W24 hsusb0_data5 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO V28 Y18 V23 hsusb0_data6 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO V27 Y19 W23 hsusb0_data7 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO V26 Y17 T22 mm3_rxdm Vminus receive data (not used in 3- or 4-pin configurations) IO AE3 AE3 NA mm3_rxdp Vplus receive data (not used in 3- or 4-pin configurations) IO AH3 M3 NA mm3_rxrcv Differential receiver signal input (not used in 3-pin mode) IO AD1 U4 (TBD) NA mm3_txse0 Single-ended zero. Used as VM in 4-pin VP_VM mode. IO AE1 V3 (TBD) NA mm3_txdat USB data. Used as VP in 4-pin VP_VM mode. IO AD2 T3 (TBD) NA mm3_txen_n Transmit enable IO AC1 T3 (TBD) NA mm2_rxdm Vminus receive data (not used in 3- or 4-pin configurations) IO AH7 AF7 AD11 mm2_rxdp Vplus receive data (not used in 3- or 4-pin configurations) IO AF7 AF6 AC9 mm2_rxrcv Differential receiver signal input (not used in 3-pin mode) IO AG8 AF9 AC11 mm2_txse0 Single-ended zero. Used as VM in 4-pin VP_VM mode. IO AH8 AE9 AD12 mm2_txdat USB data. Used as VP in 4-pin VP_VM mode. IO AB2 T8 R5 mm2_txen_n Transmit enable IO V3 V9 M4 mm1_rxdm Vminus receive data (not used in 3- or 4-pin configurations) IO AG9 V2 AD5 mm1_rxdp Vplus receive data (not used in 3- or 4-pin configurations) IO AF10 AB2 AC1 mm1_rxrcv Differential receiver signal input (not used in 3-pin mode) IO AF11 AC3 AD6 mm1_txse0 Single-ended zero. Used as VM in 4-pin VP_VM mode. IO AG12 AD4 AC6 mm1_txdat USB data. Used as VP in 4-pin VP_VM mode. IO AH12 AD3 AC7 mm1_txen_n Transmit enable IO AH14 AD2 AD9 hsusb3_tll_clk Dedicated for external transceiver 60-MHz clock input from PHY O W8 W2 NA hsusb3_tll_stp Dedicated for external transceiver Stop signal I AH3 M3 NA PRODUCT PREVIEW SIGNAL NAME MM_FSUSB3 MM_FSUSB2 MM_FSUSB1 HSUSB3_TLL Submit Documentation Feedback TERMINAL DESCRIPTION 101 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-19. Serial Communication Interfaces – USB Signals Description (continued) SIGNAL NAME DESCRIPTION TYPE ( 1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) PRODUCT PREVIEW hsusb3_tll_dir dedicated for external transceiver Data direction control from PHY O AF3 L3 NA hsusb3_tll_nxt Dedicated for external transceiver Next signal from PHY O AE3 K3 NA hsusb3_tll_data 0 Dedicated for external transceiver Bidirectional data bus IO AD1 U4 NA hsusb3_tll_data 1 Dedicated for external transceiver Bidirectional data bus IO AE1 V3 NA hsusb3_tll_data 2 Dedicated for external transceiver Bidirectional data bus IO AD2 R3 NA hsusb3_tll_data 3 Dedicated for external transceiver Bidirectional data bus IO AC1 T3 NA hsusb3_tll_data 4 Dedicated for external transceiver Bidirectional data bus IO AF6 P3 NA hsusb3_tll_data 5 Dedicated for external transceiver Bidirectional data bus IO AE6 N3 NA hsusb3_tll_data 6 Dedicated for external transceiver Bidirectional data bus IO AF5 U3 NA hsusb3_tll_data 7 Dedicated for external transceiver Bidirectional data bus IO AE5 W3 NA hsusb2_clk Dedicated for external transceiver 60-MHz clock input from PHY O AE7 AE4 AC3 hsusb2_stp Dedicated for external transceiver Stop signal O AF7 AF6 AC9 hsusb2_dir Dedicated for external transceiver Data direction control from PHY I AG7 AE6 AC10 hsusb2_nxt Dedicated for external transceiver Next signal from PHY I AH7 AF7 AD11 hsusb2_data0 Dedicated for external transceiver Bidirectional data bus IO AG8 AF9 AC11 hsusb2_data1 Dedicated for external transceiver Bidirectional data bus IO AH8 AE9 AD12 hsusb2_data2 Dedicated for external transceiver Bidirectional data bus IO AB2 T8 R5 hsusb2_data3 Dedicated for external transceiver Bidirectional data bus IO V3 V9 M4 hsusb2_data4 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO Y2 W8 N4 hsusb2_data5 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO Y3 U8 N3 hsusb2_data6 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO Y4 V8 M5 hsusb2_data7 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO AA3 W7 N5 hsusb2_tll_clk Dedicated for external transceiver 60-MHz clock input from PHY O AE7 AE4 AC3 hsusb2_tll_stp Dedicated for external transceiver Stop signal I AF7 AF6 AC9 hsusb2_tll_dir Dedicated for external transceiver data direction control from PHY O AG7 AE6 AC10 hsusb2_tll_nxt Dedicated for external transceiver Next signal from PHY O AH7 AF7 AD11 hsusb2_tll_data 0 Dedicated for external transceiver Bidirectional data bus IO AG8 AF9 AC11 HSUSB2 HSUSB2_TLL 102 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-19. Serial Communication Interfaces – USB Signals Description (continued) DESCRIPTION TYPE ( 1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) hsusb2_tll_data 1 Dedicated for external transceiver Bidirectional data bus IO AH8 AE9 AD12 hsusb2_tll_data 2 Dedicated for external transceiver Bidirectional data bus IO AB2 T8 R5 hsusb2_tll_data 3 Dedicated for external transceiver Bidirectional data bus IO V3 V9 M4 hsusb2_tll_data 4 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO Y2 W8 N4 hsusb2_tll_data 5 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO Y3 U8 N3 hsusb2_tll_data 6 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO Y4 V8 M5 hsusb2_tll_data 7 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO AA3 W7 N5 hsusb1_clk Dedicated for external transceiver 60-MHz clock input from PHY O AE10 AB3 AD3 hsusb1_stp Dedicated for external transceiver Stop signal O AF10 AB2 AC1 hsusb1_dir Dedicated for external transceiver data direction control from PHY I AF9 AA4 AC4 hsusb1_nxt Dedicated for external transceiver Next signal from PHY I AG9 V2 AD5 hsusb1_data0 Dedicated for external transceiver Bidirectional data bus IO AF11 AC3 AD6 hsusb1_data1 Dedicated for external transceiver Bidirectional data bus IO AG12 AD4 AC6 hsusb1_data2 Dedicated for external transceiver Bidirectional data bus IO AH12 AD3 AC7 hsusb1_data3 Dedicated for external transceiver Bidirectional data bus IO AH14 AD2 AD9 hsusb1_data4 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO AE11 Y3 AC5 hsusb1_data5 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO AH9 AB1 AD2 hsusb1_data6 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO AF13 AE3 AC8 hsusb1_data7 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO AE13 AA7 AD8 hsusb1_tll_clk Dedicated for external transceiver 60-MHz clock input from PHY O AE10 AB3 AD3 hsusb1_tll_stp Dedicated for external transceiver Stop signal I AF10 AB2 AC1 hsusb1_tll_dir Dedicated for external transceiver data direction control from PHY O AF9 AA4 AC4 hsusb1_tll_nxt Dedicated for external transceiver Next signal from PHY O AG9 V2 AD5 hsusb1_tll_data 0 Dedicated for external transceiver Bidirectional data bus IO AF11 AC3 AD6 hsusb1_tll_data 1 Dedicated for external transceiver Bidirectional data bus IO AG12 AD4 AC6 hsusb1_tll_data 2 Dedicated for external transceiver Bidirectional data bus IO AH12 AD3 AC7 hsusb1_tll_data 3 Dedicated for external transceiver Bidirectional data bus IO AH14 AD2 AD9 PRODUCT PREVIEW SIGNAL NAME HSUSB1 HSUSB1_TLL Submit Documentation Feedback TERMINAL DESCRIPTION 103 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-19. Serial Communication Interfaces – USB Signals Description (continued) SIGNAL NAME DESCRIPTION TYPE ( 1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) hsusb1_tll_data 4 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO AE11 Y3 AC5 hsusb1_tll_data 5 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO AH9 AB1 AD2 hsusb1_tll_data 6 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO AF13 AE3 AC8 hsusb1_tll_data 7 Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation IO AE13 AA3 AD8 PRODUCT PREVIEW 104 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com 2.4.4 SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Removable Media Interfaces Table 2-20. Removable Media Interfaces – MMC/SDIO Signals Description SIGNAL NAME DESCRIPTION TYPE ( 1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) M23 mmc1_clk MMC/SD Output Clock O N28 N19 mmc1_cmd MMC/SD command signal IO M27 L18 L23 mmc1_dat0 MMC/SD Card Data bit 0 / SPI Serial Input IO N27 M19 M22 mmc1_dat1 MMC/SD Card Data bit 1 IO N26 M18 M21 mmc1_dat2 MMC/SD Card Data bit 2 IO N25 K18 M20 mmc1_dat3 MMC/SD Card Data bit 3 IO P28 N20 N23 mmc1_dat4 MMC/SD Card Data bit 4 IO P27 M20 N22 mmc1_dat5 MMC/SD Card Data bit 5 IO P26 P17 N21 mmc1_dat6 MMC/SD Card Data bit 6 IO R27 P18 N20 mmc1_dat7 MMC/SD Card Data bit 7 IO R25 P19 P24 PRODUCT PREVIEW MULTIMEDIA MEMORY CARD (MMC1) / SECURE DIGITAL IO (SDIO1) MULTIMEDIA MEMORY CARD (MMC2) / SECURE DIGITAL IO (SDIO2) mmc2_clk MMC/SD Output Clock O AE2 W10 Y1 mmc2_dir_dat0 Direction control for DAT0 signal case an external transceiver used O AE4 V10 AB2 mmc2_dir_dat1 Direction control for DAT1 and DAT3 signals case an external transceiver used O AH3 M3 (TBD) AA2 mmc2_dir_dat2 Direction control for DAT2 signal case an external transceiver used O AF19 E4 AC17 mmc2_dir_dat3 Direction control for DAT4, DAT5, DAT6, and DAT7 signals case an external transceiver used O AE21 G3 AB16 mmc2_clkin MMC/SD input Clock I AE3 K3 (TBD) AA1 mmc2_dat0 MMC/SD Card Data bit 0 IO AH5 T10 AB3 mmc2_dat1 MMC/SD Card Data bit 1 IO AH4 T9 Y3 mmc2_dat2 MMC/SD Card Data bit 2 IO AG4 U10 W3 mmc2_dat3 MMC/SD Card Data bit 3 IO AF4 U9 V3 mmc2_dat4 MMC/SD Card Data bit 4 IO AE4 / AB3 P9 / V10 AB2 / T5 mmc2_dat5 MMC/SD Card Data bit 5 IO AH3 / AB4 P8 AA2 / R4 mmc2_dat6 MMC/SD Card Data bit 6 IO AF3 / AA4 P7 Y2 / T4 mmc2_dat7 MMC/SD Card Data bit 7 IO AE3 / AC2 R7 AA1 / T6 mmc2_dir_cmd Direction control for CMD signal case an external transceiver is used O AF3 L3 (TBD) Y2 mmc2_cmd MMC/SD command signal IO AG5 R10 AB5 MULTIMEDIA MEMORY CARD (MMC3) / SECURE DIGITAL IO (SDIO3) mmc3_clk MMC/SD Output Clock O AB1 / AF10 R9 / AB2 AC1 mmc3_cmd MMC/SD command signal IO AC3 / AE10 R8 / AB3 AD3 mmc3_dat0 MMC/SD Card Data bit 0 / SPI Serial Input IO AE4 / AE11 V10 / Y3 AB2 / AC5 mmc3_dat1 MMC/SD Card Data bit 1 IO AH3 / AH9 AB1 AA2 / AD2 mmc3_dat2 MMC/SD Card Data bit 2 IO AF3 / AF13 AE3 Y2 / AC8 mmc3_dat3 MMC/SD Card Data bit 3 IO AE3 / AE13 AA3 AA1 / AD8 mmc3_dat4 MMC/SD Card Data bit 4 IO AF11 AC3 AD6 mmc3_dat5 MMC/SD Card Data bit 5 IO AG9 V2 AD5 mmc3_dat6 MMC/SD Card Data bit 6 IO AF9 AA4 AC4 mmc3_dat7 MMC/SD Card Data bit 7 IO AH14 AD2 AD9 (1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog) Submit Documentation Feedback TERMINAL DESCRIPTION 105 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 2.4.5 www.ti.com Test Interfaces Table 2-21. Test Interfaces – ETK Signals Description PRODUCT PREVIEW SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) etk_ctl ETK trace ctl O AE10 AB2 AD3 etk_clk ETK trace clock O AF10 AB3 AC1 etk_d0 ETK data 0 O AF11 AC3 AD6 etk_d1 ETK data 1 O AG12 AD4 AC6 etk_d2 ETK data 2 O AH12 AD3 AC7 etk_d3 ETK data 3 O AE13 AA3 AD8 etk_d4 ETK data 4 O AE11 Y3 AC5 etk_d5 ETK data 5 O AH9 AB1 AD2 etk_d6 ETK data 6 O AF13 AE3 AC8 etk_d7 ETK data 7 O AH14 AD2 AD9 etk_d8 ETK data 8 O AF9 AA4 AC4 (1) 106 etk_d9 ETK data 9 O AG9 V2 AD5 etk_d10 ETK data 10 O AE7 AE4 AC3 etk_d11 ETK data 11 O AF7 AF6 AC9 etk_d12 ETK data 12 O AG7 AE6 AC10 etk_d13 ETK data 13 O AH7 AF7 AD11 etk_d14 ETK data 14 O AG8 AF9 AC11 etk_d15 ETK data 15 O AH8 AE9 AD12 Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog) TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-22. Test Interfaces – JTAG Signals Description SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) jtag_ntrst Test Reset I AA17 U15 AB7 jtag_tck Test Clock I AA13 V14 AB6 jtag_rtck ARM Clock Emulation O AA12 W13 AA7 jtag_tms_tmsc Test Mode Select IO AA18 V15 AA9 jtag_tdi Test Data Input I AA20 U16 AB10 jtag_tdo Test Data Output O AA19 Y13 AB9 jtag_emu0 Test emulation 0 IO AA11 Y15 AC24 jtag_emu1 Test emulation 1 IO AA10 Y14 AD24 Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog) Table 2-23. Test Interfaces – SDTI Signals Description TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) SUBSYSTEM SIGNAL MULTIPLEXING (2) Serial clock dual edge O AF7 / AA11 / AG8 AF6 / Y15 / AF9 AC9 / AC24 / AC11 etk_d11 / jtag_emu0 / etk_d14 sdti_txd0 Serial data out (System Trace messages) O AG7 / AA10 / AA11 AE6 / Y14 / Y15 AC10 / AD24 / AC24 etk_d12 / jtag_emu1 / jtag_emu0 sdti_txd1 Serial data out (System Trace messages) O AH7 / AA10 AF7 / Y14 AD11 / AD24 etk_d13 / jtag_emu1 sdti_txd2 Serial data out (System Trace messages) O AG8 AF9 AC11 etk_d14 sdti_txd3 Serial data out (System Trace messages) O AH8 AE9 AD12 etk_d15 SIGNAL NAME sdti_clk (1) (2) DESCRIPTION Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog) The subsystem pin multiplexing options are not described in Table 2-1 and Table 2-4 Table 2-24. Test Interfaces – HWDBG Signals Description (1) SIGNAL NAME DESCRIPTION TYPE (1) hw_dbg0 Debug signal 0 hw_dbg1 Debug signal 1 hw_dbg2 Debug signal 2 hw_dbg3 Debug signal 3 hw_dbg4 BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) O A24 / AF10 C23/AB2 AD3 O A23 / AE10 D23/AB3 AC1 O C27/ AF11 C26/AC3 AD6 O C23 / AG12 B23/AD4 AC6 Debug signal 4 O B24 / AH12 A24/AD3 AC7 hw_dbg5 Debug signal 5 O C24 / AE13 B24/AA3 AD8 hw_dbg6 Debug signal 6 O D24 / AE11 D24/Y3 AC5 hw_dbg7 Debug signal 7 O A25 / AH9 C24/AB1 AD2 hw_dbg8 Debug signal 8 O B25 / AF13 D25/AE3 AC8 hw_dbg9 Debug signal 9 O C26 / AH14 E26/AD2 AD9 hw_dbg10 Debug signal 10 O B23 / AF9 A23/AA4 AC4 hw_dbg11 Debug signal 11 O D25 / AG9 D26/V2 AD5 hw_dbg12 Debug signal 12 O D28 / AE7 G25/AE4 AC3 hw_dbg13 Debug signal 13 O D26 / AF7 K24/AF6 AC9 hw_dbg14 Debug signal 14 O E26 / AG7 G26/AE6 AC10 hw_dbg15 Debug signal 15 O F28 / AH7 H25/AF7 AD11 hw_dbg16 Debug signal 16 O F27 / AG8 H26/AF9 AC11 Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog) Submit Documentation Feedback TERMINAL DESCRIPTION 107 PRODUCT PREVIEW (1) OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-24. Test Interfaces – HWDBG Signals Description (continued) SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) hw_dbg17 Debug signal 17 O G26 / AH8 J26/AE9 AD12 2.4.6 Miscellaneous Table 2-25. Miscellaneous – GP Timer Signals Description PRODUCT PREVIEW SIGNAL NAME DESCRIPTION TYPE (1) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) gpt8_pwm_evt PWM or event for GP timer 8 IO N8 / AD25 / V3 C5 / AD21/ V9 G4/ M4 gpt9_pwm_evt PWM or event for GP timer 9 IO T8 / AB26 / Y2 B4 / W8 / Y24 F4 / N4 gpt10_pwm_evt PWM or event for GP timer 10 IO R8 / AB25 / Y3 C4 / U8 / AA24 G5 / N3 gpt11_pwm_evt PWM or event for GP timer 11 IO P8 / AA25 / Y4 B5 / V8 / AD22 F3 / M5 (1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog) Table 2-26. Miscellaneous - Reserved Pins SIGNAL NAME DESCRIPTION TYPE BALL BOTTOM (CBB Pkg.) BALL TOP (CUS Pkg.) rsv01 Reserved pin. Leave unconnected NA AH20 NA 108 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com 2.4.7 SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 General-Purpose IOs SIGNAL NAME DESCRIPTION TYPE (2) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) gpio_0 General-purpose IO 0 IO AF26 V16 W16 gpio_1 General-purpose IO 1 IO AF25 W15 Y13 gpio_2 General-purpose IO 2 IO AH26 F3 AB12 gpio_3 General-purpose IO 3 IO AG26 D3 AC16 gpio_4 General-purpose IO 4 IO AE14 C3 AD17 gpio_5 General-purpose IO 5 IO AF18 E3 AD18 gpio_6 General-purpose IO 6 IO AF19 E4 AC17 gpio_7 General-purpose IO 7 IO AE21 G3 AB16 gpio_8 General-purpose IO 8 IO AF21 D4 AA15 gpio_9 General-purpose IO 9 IO AF22 V12 AD23 gpio_10 General-purpose IO 10 IO AG25 AE14 Y7 gpio_11 General-purpose IO 11 IO AA11 Y15 AC24 gpio_12 General-purpose IO 12 IO AF10 AB2 AC1 gpio_13 General-purpose IO 13 IO AE10 AB3 AD3 gpio_14 General-purpose IO 14 IO AF11 AC3 AD6 gpio_15 General-purpose IO 15 IO AG12 AD4 AC6 gpio_16 General-purpose IO 16 IO AH12 AD3 AC7 gpio_17 General-purpose IO 17 IO AE13 AA3 AD8 gpio_18 General-purpose IO 18 IO AE11 Y3 AC5 gpio_19 General-purpose IO 19 IO AH9 AB1 AD2 gpio_20 General-purpose IO 20 IO AF13 AE3 AC8 gpio_21 General-purpose IO 21 IO AH14 AA2 AD9 gpio_22 General-purpose IO 22 IO AF9 AA4 AC4 gpio_23 General-purpose IO 23 IO AG9 V2 AD5 gpio_24 General-purpose IO 24 IO AE7 AE4 AC3 gpio_25 General-purpose IO 25 IO AF7 AF6 AC9 gpio_26 General-purpose IO 26 IO AG7 AE6 AC10 gpio_27 General-purpose IO 27 IO AH7 AF7 AD11 gpio_28 General-purpose IO 28 IO AG8 AF9 AC11 gpio_29 General-purpose IO 29 IO AH8 AE9 AD12 gpio_30 General-purpose IO 30 IO AF24 AD7 Y10 gpio_31 General-purpose IO 31 IO AA10 Y14 AD24 gpio_34 General-purpose IO 34 IO N4 J2 K4 gpio_35 General-purpose IO 35 IO M4 H1 K3 gpio_36 General-purpose IO 36 IO L4 H2 K2 gpio_37 General-purpose IO 37 IO K4 G2 J4 gpio_38 General-purpose IO 38 IO T3 F1 J3 gpio_39 General-purpose IO 39 IO R3 F2 J2 gpio_40 General-purpose IO 40 IO N3 E1 J1 gpio_41 General-purpose IO 41 IO M3 E2 H1 gpio_42 General-purpose IO 42 IO L3 D1 H2 gpio_43 General-purpose IO 43 IO K3 D2 G2 gpio_44 General-purpose IO 44 IO H2 V1 R2 (1) (2) PRODUCT PREVIEW Table 2-27. General-Purpose IOs Signals Description (1) NA in table stands for Not Applicable. Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog) Submit Documentation Feedback TERMINAL DESCRIPTION 109 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-27. General-Purpose IOs Signals Description (continued) DESCRIPTION TYPE (2) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) gpio_45 General-purpose IO 45 IO K2 Y1 T2 gpio_46 General-purpose IO 46 IO P1 T1 U1 gpio_47 General-purpose IO 47 IO R1 U2 R3 gpio_48 General-purpose IO 48 IO R2 U1 T3 gpio_49 General-purpose IO 49 IO T2 P1 U2 gpio_50 General-purpose IO 50 IO W1 L2 V1 gpio_51 General-purpose IO 51 IO Y1 M2 V2 gpio_52 General-purpose IO 52 IO H3 AD1 NA gpio_53 General-purpose IO 53 IO V8 A3 NA gpio_54 General-purpose IO 54 IO U8 B6 D2 gpio_55 General-purpose IO 55 IO T8 B4 F4 gpio_56 General-purpose IO 56 IO R8 C4 G5 gpio_57 General-purpose IO 57 IO P8 B5 F3 gpio_58 General-purpose IO 58 IO N8 C5 G4 gpio_59 General-purpose IO 59 IO T4 N1 W2 gpio_60 General-purpose IO 60 IO G3 K2 K5 gpio_61 General-purpose IO 61 IO U3 J1 L1 gpio_62 General-purpose IO 62 IO H1 AC6 E1 gpio_63 General-purpose IO 63 IO L8 AC8 NA gpio_64 General-purpose IO 64 IO K8 B3 NA gpio_65 General-purpose IO 65 IO J8 C6 C2 gpio_66 General-purpose IO 66 IO D28 G25 G22 gpio_67 General-purpose IO 67 IO D26 K24 E22 gpio_68 General-purpose IO 68 IO D27 M25 F22 gpio_69 General-purpose IO 69 IO E27 F26 J21 gpio_70 General-purpose IO 70 IO AG22 AE21 AC19 gpio_71 General-purpose IO 71 IO AH22 AE22 AB19 gpio_72 General-purpose IO 72 IO AG23 AE23 AD20 gpio_73 General-purpose IO 73 IO AH23 AE24 AC20 gpio_74 General-purpose IO 74 IO AG24 AD23 AD21 gpio_75 General-purpose IO 75 IO AH24 AD24 AC21 gpio_76 General-purpose IO 76 IO E26 G26 D24 gpio_77 General-purpose IO 77 IO F28 H25 E23 gpio_78 General-purpose IO 78 IO F27 H26 E24 gpio_79 General-purpose IO 79 IO G26 J26 F23 gpio_80 General-purpose IO 80 IO AD28 AC26 AC22 gpio_81 General-purpose IO 81 IO AD27 AD26 AC23 gpio_82 General-purpose IO 82 IO AB28 AA25 AB22 gpio_83 General-purpose IO 83 IO AB27 Y25 Y22 gpio_84 General-purpose IO 84 IO AA28 AA26 W22 gpio_85 General-purpose IO 85 IO AA27 AB26 V22 gpio_86 General-purpose IO 86 IO G25 L25 J22 gpio_87 General-purpose IO 87 IO H27 L26 G23 gpio_88 General-purpose IO 88 IO H26 M24 G24 gpio_89 General-purpose IO 89 IO H25 M26 H23 gpio_90 General-purpose IO 90 IO E28 F25 D23 PRODUCT PREVIEW SIGNAL NAME 110 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 SIGNAL NAME DESCRIPTION TYPE (2) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) gpio_91 General-purpose IO 91 IO J26 N24 K22 gpio_92 General-purpose IO 92 IO AC27 AC25 V21 gpio_93 General-purpose IO 93 IO AC28 AB25 W21 gpio_94 General-purpose IO 94 IO A24 C23 A22 gpio_95 General-purpose IO 95 IO A23 D23 E18 gpio_96 General-purpose IO 96 IO C25 C25 B22 gpio_97 General-purpose IO 97 IO C27 C26 J19 gpio_98 General-purpose IO 98 IO C23 B23 H24 gpio_99 General-purpose IO 99 I AG17 AE16 AB18 gpio_100 General-purpose IO 100 I AH17 AE15 AC18 gpio_101 General-purpose IO 101 IO B24 A24 G19 gpio_102 General-purpose IO 102 IO C24 B24 F19 gpio_103 General-purpose IO 103 IO D24 D24 G20 gpio_104 General-purpose IO 104 IO A25 C24 B21 gpio_105 General-purpose IO 105 IO K28 P25 L24 gpio_106 General-purpose IO 106 IO L28 P26 K24 gpio_107 General-purpose IO 107 IO K27 N25 J23 gpio_108 General-purpose IO 108 IO L27 N26 K23 gpio_109 General-purpose IO 109 IO B25 D25 F21 gpio_110 General-purpose IO 110 IO C26 E26 G21 gpio_111 General-purpose IO 111 IO B26 E25 C22 gpio_112 General-purpose IO 112 I AG19 AD17 NA gpio_113 General-purpose IO 113 I AH19 AD16 NA gpio_114 General-purpose IO 114 I AG18 AE18 NA gpio_115 General-purpose IO 115 I AH18 AE17 NA gpio_116 General-purpose IO 116 IO P21 U18 V20 gpio_117 General-purpose IO 117 IO N21 R18 T21 gpio_118 General-purpose IO 118 IO R21 T18 V19 gpio_119 General-purpose IO 119 IO M21 R19 R20 gpio_120 General-purpose IO 120 IO N28 / T28 W19 / N19 M23 / R21 gpio_121 General-purpose IO 121 IO M27 / T25 U20 / L18 L23 / R23 gpio_122 General-purpose IO 122 IO N27 / R28 V19 / M19 M22 / P23 gpio_123 General-purpose IO 123 IO N26 M18 M21 gpio_124 General-purpose IO 124 IO N25 / T26 W18 / K18 M20 gpio_125 General-purpose IO 125 IO P28 / T27 V20 / N20 N23 gpio_126 General-purpose IO 126 IO D25 / P27 M20 / D26 J20 / N22 gpio_127 General-purpose IO 127 IO P26 P17 N21 gpio_128 General-purpose IO 128 IO R27 P18 N20 gpio_129 General-purpose IO 129 IO R25 P19 P24 gpio_130 General-purpose IO 130 IO AE2 / U28 Y20 / W10 Y1 / T23 gpio_131 General-purpose IO 131 IO AG5 / U27 V18 / R10 AB5 / U24 gpio_132 General-purpose IO 132 IO AH5 T10 AB3 gpio_133 General-purpose IO 133 IO AH4 T9 Y3 gpio_134 General-purpose IO 134 IO AG4 U10 W3 gpio_135 General-purpose IO 135 IO AF4 U9 V3 gpio_136 General-purpose IO 136 IO AE4 V10 AB2 Submit Documentation Feedback TERMINAL DESCRIPTION PRODUCT PREVIEW Table 2-27. General-Purpose IOs Signals Description (continued) 111 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 2-27. General-Purpose IOs Signals Description (continued) DESCRIPTION TYPE (2) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) gpio_137 General-purpose IO 137 IO AH3 - AA2 gpio_138 General-purpose IO 138 IO AF3 - Y2 gpio_139 General-purpose IO 139 IO AE3 - AA1 gpio_140 General-purpose IO 140 IO AF6 - V6 gpio_141 General-purpose IO 141 IO AE6 - V5 gpio_142 General-purpose IO 142 IO AF5 - W4 gpio_143 General-purpose IO 143 IO AE5 - V4 gpio_144 General-purpose IO 144 IO AB26 Y24 NA gpio_145 General-purpose IO 145 IO AB25 AA24 NA gpio_146 General-purpose IO 146 IO AA25 AD22 NA gpio_147 General-purpose IO 147 IO AD25 AD21 NA gpio_148 General-purpose IO 148 IO AA8 L4 W7 gpio_149 General-purpose IO 149 IO AA9 R2 W6 gpio_150 General-purpose IO 150 IO W8 - AC2 gpio_151 General-purpose IO 151 IO Y8 H3 V7 gpio_152 General-purpose IO 152 IO AE1 - NA gpio_153 General-purpose IO 153 IO AD1 - NA gpio_154 General-purpose IO 154 IO AD2 - NA gpio_155 General-purpose IO 155 IO AC1 - NA gpio_156 General-purpose IO 156 IO Y21 U19 W19 gpio_157 General-purpose IO 157 IO AA21 V17 AB20 gpio_158 General-purpose IO 158 IO V21 U17 W18 gpio_159 General-purpose IO 159 IO U21 T20 Y18 gpio_160 General-purpose IO 160 IO T21 T19 AA18 gpio_161 General-purpose IO 161 IO K26 P20 AA19 gpio_162 General-purpose IO 162 IO W21 T17 V18 gpio_163 General-purpose IO 163 IO H18 F23 A23 gpio_164 General-purpose IO 164 IO H19 F24 B23 gpio_165 General-purpose IO 165 IO H20 H24 B24 gpio_166 General-purpose IO 166 IO H21 G24 C23 gpio_167 General-purpose IO 167 IO B23 A23 F18 gpio_168 General-purpose IO 168 IO AF15 C2 AC15 gpio_169 General-purpose IO 169 IO U26 W20 U23 gpio_170 General-purpose IO 170 IO J25 J23 A24 gpio_171 General-purpose IO 171 IO AB3 P9 T5 gpio_172 General-purpose IO 172 IO AB4 P8 R4 gpio_173 General-purpose IO 173 IO AA4 P7 T4 gpio_174 General-purpose IO 174 IO AC2 R7 T6 gpio_175 General-purpose IO 175 IO AC3 R8 NA gpio_176 General-purpose IO 176 IO AB1 R9 NA gpio_177 General-purpose IO 177 IO AB2 T8 R5 gpio_178 General-purpose IO 178 IO AA3 W7 N5 gpio_179 General-purpose IO 179 IO Y2 W8 N4 gpio_180 General-purpose IO 180 IO Y3 U8 N3 gpio_181 General-purpose IO 181 IO Y4 V8 M5 gpio_182 General-purpose IO 182 IO V3 V9 M4 PRODUCT PREVIEW SIGNAL NAME 112 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-27. General-Purpose IOs Signals Description (continued) DESCRIPTION TYPE (2) BALL BOTTOM (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL BOTTOM (CUS Pkg.) gpio_183 General-purpose IO 183 IO AE15 C1 AC14 gpio_184 General-purpose IO 184 IO AF14 AB4 AC13 gpio_185 General-purpose IO 185 IO AG14 AC4 AC12 gpio_186 General-purpose IO 186 IO AE22 W11 AE6 gpio_188 General-purpose IO 188 IO U25 W17 W24 gpio_189 General-purpose IO 189 IO V28 Y18 V23 gpio_190 General-purpose IO 190 IO V27 Y19 W23 gpio_191 General-purpose IO 191 IO V26 Y17 T22 PRODUCT PREVIEW SIGNAL NAME Submit Documentation Feedback TERMINAL DESCRIPTION 113 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 2.4.8 www.ti.com System and Miscellaneous Terminals Table 2-28. System and Miscellaneous Signals Description SIGNAL NAME DESCRIPTION TYPE ( 1) BALL BOTTOM (CBB Pkg.) BALL TOP (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL TOP (CBC Pkg.) BALL BOTTOM (CUS Pkg.) PRODUCT PREVIEW sys_32k 32-kHz clock input I AE25 NA AE20 - AA16 sys_xtalin Main input clock. Oscillator input or LVCMOS at 19.2, 13, or 12 MHz. I AE17 NA AF19 - AD15 sys_xtalout Output of oscillator O AF17 NA AF20 - AD14 sys_altclk Alternate clock source selectable for GPTIMERs (maximum 54 MHz), USB (48 MHz), or NTSC/PAL (54 MHz) I J25 NA J23 - A24 sys_clkreq Request from OMAP3515/03 device for system clock (open source type) IO AF25 NA W15 - Y13 sys_clkout1 Configurable output clock1 O AG25 NA AE14 - Y7 sys_clkout2 Configurable output clock2 O AE22 NA W11 - AA6 sys_boot0 Boot configuration mode bit 0 I AH26 NA F3 - AB12 sys_boot1 Boot configuration mode bit 1 I AG26 NA D3 - AC16 sys_boot2 Boot configuration mode bit 2 I AE14 NA C3 - AD17 sys_boot3 Boot configuration mode bit 3 I AF18 NA E3 - AD18 sys_boot4 Boot configuration mode bit 4 I AF19 NA E4 - AC17 sys_boot5 Boot configuration mode bit 5 I AE21 NA G3 - AB16 sys_boot6 Boot configuration mode bit 6 I AF21 NA D4 - AA15 I AH25 NA V13 - AA10 IOD AF24 NA AD7 - Y10 sys_nrespwro Power On Reset n sys_nreswar m Warm Boot Reset (open drain output) sys_nirq External FIQ input I AF26 NA V16 - W16 sys_nvmode1 Indicates the voltage mode O AD26 NA AD15 - Y16 sys_nvmode2 Indicates the voltage mode O AE26 NA W16 - Y15 sys_off_mode Indicates the voltage mode O AF22 NA V12 - AD23 sys_ndmareq External DMA request 0 (system 0 expansion). Level (active low) or edge (falling) selectable. I U8 NA B6 - D2 sys_ndmareq External DMA request 1 (system 1 expansion). Level (active low) or edge (falling) selectable. I T8 / J8 NA B4 / C6 - F4 / C2 sys_ndmareq External DMA request 2 (system 2 expansion). Level (active low) or edge (falling) selectable. I L3 / R8 NA D1 / C4 - H2 / G5 sys_ndmareq External DMA request 3 (system 3 expansion). Level (active low) or edge (falling) selectable. I K3 / P8 NA D2 / B5 - G2 / F3 sys_secure_ indicator MSECURE transactions indicator O AG9 NA V2 - AD5 sys_drm_ msecure MSECURE output O AF9 NA AA4 - AC4 sys_ipmcsws Reserved AI B1 NA B1 - A1 sys_opmcsws Reserved AO A1 NA A2 - A2 O AG11 AB9 AF10 Y9 NA pop_int0_ft POP dedicated control signal pop_int1_ft POP dedicated control signal O AH11 AC9 AE2 W2 NA pop_tq_temp _ sense_ft POP dedicated control signal NA AH16 AC14 AF14 AA12 NA (1) 114 Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog) TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-28. System and Miscellaneous Signals Description (continued) SIGNAL NAME POP dedicated control signal TYPE ( 1) BALL BOTTOM (CBB Pkg.) BALL TOP (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL TOP (CBC Pkg.) BALL BOTTOM (CUS Pkg.) NA AG13 AB11 - AA5 NA PRODUCT PREVIEW pop_reset_rp _ft DESCRIPTION Submit Documentation Feedback TERMINAL DESCRIPTION 115 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 2.4.9 www.ti.com Power Supplies Table 2-29. Power Supplies Signals Description (1) SIGNAL NAME DESCRIPTION BALL BOTTOM (CBB Pkg.) BALL TOP (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL TOP (CBC Pkg.) BALL BOTTOM (CUS Pkg.) PRODUCT PREVIEW vdd_mpu ARM power domain Y9 / W9 / T9 / R9 / M9 / L9 / J9 / Y10 / U10 / T10 / R10 / N10 / M10 / L10 / J10 / Y11 / W11 / K11 / J11 / W12 / K13 / Y14 / K14 / J14 / Y15 / W15 / J15 NA H7/ N7/ U7/ V7/ N8/ G9/ L9/ M9/ W9/ Y9/ M10/ P10/ K11/ U11/ V11/ Y11/ G12/ D13/ U13 NA W13/ W12/ V13/ V12/ U13/ U12/ T8/ T7/ R8/ R7/ R6/ N8/ N7/ N6/ M12/ M8/ M7/ M6/ L12/ L11/ J10/ J9/ H10/ H9/ G10/ G9/F10 vdd_core Core power domain AC4 / J4 / H4 / D8 / AE9 / D9 / D15 / Y16 / AE18 / Y18 / W18 / K18 / J18 / AE19 / Y19 / U19 / T19 / N19 / M19 / J19 / Y20 / W20 / V20 / U20 / P20 / N20 / K20 / J20 / D22 / D23 / AE24 / M25 / L25 / E25 NA M7/ T7/ Y8/ G11/ Y12/ D15/ M17/ G18/ H20/ R20/ AC21 NA T20/ T19/ T18/ T17/ R19/ R18/ R17/ M15/ M14/ L15/ L14/ K19/ K18/ K17/ J18/ J17/ H13/ H12/ G13/ G12/ F13/ F12 cap_vdd_wkup Wakeup/EMU/me mory domains, connect capacitor AA15 NA K14 NA Y12 bg_testout Used for band gap test U4 NA D6 NA AD1 vdds_dpll_dll DLL IO power domain (1.8 V): internal connection to PLL_VDDS, power supply for 3PLL (1.8 V) K15 NA K13 NA G18 vpp eFuse programmation G1 NA D5 NA B1 vdda_dac Video DAC power plane V25 NA V25 NA AB13 vssa_dac Video DAC ground plane Y26 NA V24 NA AB15 vdds IO power plane AD3 / AD4 / W4 / AF8 / AE8 / AF16 / AE16 / AF23 / AE23 / F25 / F26 / AG27/ AE27/ AG20/ H28/ AG21/P25 NA G4/ M4/ T4/ Y4/ L7/ AC7/ D9/ AE10/ C11/ J15/ AC15/ A18/ J18/ AC18/ AD20/ E24/ L24/ T24/ W24/ AC24 - Y9 / W10 / W9 / V10 / V9 / U10 / N19 / N18 / N17 / M19 / M18 / M17 / H8 vdds_mem Memory IO power plane U1 / J1 / F1 / J2 / F2 / R4 / B5 / A5 / AH6 / B8 / A8 / B12 / A12 / D16 / C16 / B18 / A18 / B22 / A22 / G28 / C28 AC5 / P1 / H1 / F23 / E1 / C23 / A4 / A7 / A10 / A15 / A18 vdds_dpll_per Peripheral DPLLs power rail AA16 NA U14 NA U17 vdds_wkup_bg For wakeup LDO and VDDA (2 LDOs SRAM and BG) AA14 NA W14 NA AA13 (1) 116 K8 / K7 / K6 / J8 / J7 / J6 / H15 / G16 / G15 / F16 / F15 / E16 NA = Not Applicable. TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 2-29. Power Supplies Signals Description (continued) DESCRIPTION BALL BOTTOM (CBB Pkg.) BALL TOP (CBB Pkg.) BALL BOTTOM (CBC Pkg.) BALL TOP (CBC Pkg.) vss Ground vdds_sram SRAM LDOs W16 NA U12 NA AA12 vdds_mmc1 MMC IO power domain for CMD, CLK, and DAT(0..3) K25 NA N23 NA N24 vdds_mmc1a Power supply for MMC DAT [4..7] P25 NA P23 NA H8 cap_vdd_sram_ SRAM LDO mpu capacitance for VDDRAM1 V4 NA N9 NA U8 cap_vdd_sram_ SRAM LDO core capacitance for VDDRAM2 L21 NA K20 NA H17 pop_ddr_vdd_ft POPed SDRAM power pop_flash_vpp_ POPed flash vpp ft AG2 / U2 / B2 / H2 / B18 / AC20 / G1/ K1/ R1/ W1/ C1/ F1/ H2/ M2/ R2/ AG3 / W3 / P3 / AB5 / AB14 / B2/ H4/ N4/ R4/ Y6/AA7/ Y11/ AA16/ J3 / E3 / A3 / P4 AB20 / P2 / F22 / W4/ AB5/ A6/ D7/ W20/P20/ L21/ H20/ / E4 / AG6 / D7 / E2 / C22 / B4 / Y7/AE7/ A8/ G8/ F20/ B14/A13/ A7 C7 / V9 / U9 / P9 B7 / B10 / B15 D10/ G10/ L10/ / N9 / K9 / W10 / N10/ Y10/ AC10/ V10 / P10 / K10 / C12/ D12/A13/ D14/ D10 / C10 / AF12 AD14/ K15/ Y16/ / AE12 / Y12 / L17/ N17/ R17/ K12 / J12 / Y13 / D18/ D20/G20/ E22/ W13 / J13 / D13 / AB22/ G23/ L23/ C13 / W14 / K16 T23/ W23/ AF23/ / J16 / Y17 / W17 B25/ K25/U25/ / K17 / J17 / W19 AD25 / V19 / R19 / P19 / L19 / K19 / D19 / C19 / AF20 / AE20 / T20 / R20 / M20 / L20 / D21 / C22 / AC25 / Y25 / W25 / AC26 / R26 / L26 / A26 / G27 / B27/ AA26/ M28/ AG16/ AH21 BALL BOTTOM (CUS Pkg.) A15 / J28 / M1 / AF28 / AE28 AA23 / Y23 / K1 / L1/AF13/AF17/AF18 J1/AA11/Y14/AA17/ H23 / A12 /A20/U26/K26 B16/P21/H21 AH13 AC11 pop_flash_vdd_ POPed flash ft power N1 / AA1 / AF1 / AH10 / AH15 AC8 / AC13 / AA1 / U1 / L1 pop_vss_ft B15 / J27 / M2 / M26 / N2 / AA2 / AF2 / AF27 / AG10 / AG15 AB8 / AB13 / AA2 / AA22 / U2 / L2 / K2 / K22 / H22 / B12 POPed devices ground Submit Documentation Feedback AA11 AF13 AF16/AF22/T2/Y2/A AA14/AA19/N2/T2/Y F8/AF5 7/AA6 AF15/AF21/AF24 AA13/Y17/Y19 W15/ V16/ V15/ U16/ U15/ U14/ U11/ U9/T16/ T15/ T14/ T13/ T12/ T11/ T10/ T9/ R15/ R14/ R11/ R10/ P17/ P15/ P14/ P13/P12/ P11/ P10/ P8/ N16/ N15/ N14/ N13/ N12/ N11/ N10/ N9/ M16/ M13/ M11/ M10/ M9/ L17/ L13/ L10/ L8/ K15/ K14/ K11/ K10/ J16/ J15/ J14/ J13/ J12/ J11/H16/ H14/ H11 NA NA NA NA TERMINAL DESCRIPTION 117 PRODUCT PREVIEW SIGNAL NAME OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 3 ELECTRICAL CHARACTERISTICS 3.1 Power Domains The OMAP3515/03 device integrates enhanced features that dynamically adapt energy consumption according to application needs and performance requirements. PRODUCT PREVIEW The OMAP3515/03 device includes an enhanced power-management scheme based on: • Nine independent functional voltage domains on chip partitioning • Multiple voltage domains • Voltage scaling support • Enhanced memory retention support • Optimized device off mode • Centralized management of power, reset, and clock The external power supplies of OMAP3515/03 are: • vdd_mpu for the ARM • vdd_core for macros • vdds for IO macros • vdds_mem for memory macros • vdds_sram for SRAM LDOs • vdds_dpll_dll for DLL IO • vdds_dpll_per for peripheral DPLLs • vdds_wkup_bg for wakeup LDO and VDDA (2 LDOs: SRAM and BandGap) • vdda_dac for video DAC • vdds_mmc1 for MMC IO • vpp for eFuse The supply voltages are detailed in Table 3-3. Figure 3-1 illustrates the power domains: 118 ELECTRICAL CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 vdd_mpu vdds_dpll_dll DLL/DCDL BandGap vdds_wkup_bg LDO3 1.0 V/1.2 V WKUP cap_vdd_wkup EMU BCK MEM VDDS MEM DPLL_MPU cap_vdd_sram_mpu SRAM 1 LDO 0 V/1.0 V/1.2 V vdd_mpu domain PRODUCT PREVIEW vdds SRAM1 ARRAY MPU VDDS vdds_mem LDO in 1.8 V out 1.2 V vdds_sram vpp eFUSE LDO in 1.8 V out 1.2 V vdd_core Core SRAM 2 LDO 0 V/1.0 V/1.2 V SRAM2 ARRAY cap_vdd_sram_core DPLL_CORE vdds_mmc1 MMC1 LDO HSDIVIDER LDO in 1.8 V out 1.2 V Periph1 tv_ref (for capacitor) DPLL4 vdds_dpll_per LDO vdda_dac HSDIVIDER Dual Video DAC LDO in 1.8 V out 1.2 V Periph2 DPLL5 vdd_core domain vss vssa_dac OMAP Device 030-003 Figure 3-1. OMAP3515/03 Power Domains This power domain segmentation switches off (or places in retention state) domains that are unused while keeping others active. This implementation is based on internal switches that independently control each power domain. A power domain regular logic is attached to one of the device VDD supplies through a primary domain switch. When the primary switch is open, most of the logic supply is off, resulting in a low-leakage state of the domain. Embedded switches are implemented for all power domains except the wake-up domain. This allows the domain to be powered off, if not being used, to give maximum power savings. For more information, see the PRCM chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUFA5]. All domain output signals at the interface between power domains are connected through isolation latch cells. These cells ensure a proper electrical isolation between the domains and an appropriate interface state at the domain boundaries. Submit Documentation Feedback ELECTRICAL CHARACTERISTICS 119 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 3.2 Absolute Maximum Ratings The following table specifies the absolute maximum ratings over the operating junction temperature range of OMAP commercial and extended temperature devices. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Notes: • Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions. • The OMAP3515/03 device adheres to EIA/JESD22–A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). Minimum pass level for HBM is ±2 kV. PRODUCT PREVIEW Table 3-1. Absolute Maximum Ratings Over Operating Junction Temperature Range MIN MAX UNIT vdd_mpu vdd_core Supply voltage range for core macros PARAMETER –0.5 1.6 V vdds vdds_mem Second supply voltage range for 1.8-V I/O macros –0.5 2.25 V vdds_mmc1 vdds_mmc1a Second supply voltage range for 1.8-V IOs –0.5 2.45 V vdds_dsi vdds_sdi vdds_csi2 vdds_csib Supply voltage for Supply voltage for Supply voltage for Supply voltage for vdds_dpll_dll vdds_dpll_per Second supply voltage range for 3.0-V IOs –0.5 3.50 –0.5 (1) 2.10 (1) V Supply voltage for DLL DPLL Supply voltage for Per DPLL –0.5 2.10 V vdds_sram vdds_wkup_bg Supply voltage for SRAM LDOs Supply voltage for wakeup LDO and VDDA (2 LDOs SRAM and BG) –0.5 2.25 V VPAD Voltage range at PAD CSIb (Balls K28, L28, K27, L27) CSI2 (Balls AG17, AH17, AG19, AH19, AG18, AH18) DSI (Balls AG22, AH22, AG23, AH23, AG24, AH24) SDI (Balls AD28, AD27, AB28, AB27, AA28, AA27, AC27, AC28) –0.5 (1) 2.10 (1) V MMC1, MS (Balls N28, M27, N27, N26, N25, P28) MMC1, SIM (Balls P27, P26, R27, R25) Supply voltage range for 1.8-V IOs –0.54 (2) 2.34 (2) Supply voltage range for 3.0-V IOs –0.45 (3) 3.45 (3) –0.63 (2) 2.73 (2) DSI SDI CSI2 CSIb I2C1, I2C2, I2C3, I2C4 (Balls K21, J21, AF15, AE15, AF14, AG14, AD26, AE26) Crystal (xtalin/xtalout) (Balls AE17, AF17) –0.5 2.71 Other balls –0.5 vddsx (4) + 0.5 vdda_dac Supply voltage range for analog macros VESD ESD stress voltage (5) 2.43 V HBM (human body model) (6) 2000 V CDM (charged device model) (7) 500 IIOI Current-pulse injection on each I/O pin (8) Iclamp Clamp current for an input or output (1) (2) (3) (4) (5) (6) (7) (8) 120 –0.5 –20 200 mA 20 mA To be confirmed. For a maximum time of 30% time period. For a maximum time of 15% time period. ) Depending on ball, vddsx can be vdds_mem or vdds. Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device. JEDEC JESD22–A114 D with the following exception-no connect pins are not stressed. 2000V Human Body Model (HBM) JEDEC JESD22–C101C with the following exception-split out pin groupings to eliminate cumulative stress effect Each device is tested with I/O pin injection of 200 mA with a stress voltage of 1.5 times maximum vdd at room temperature. ELECTRICAL CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 3-1. Absolute Maximum Ratings Over Operating Junction Temperature Range (continued) PARAMETER Tstg Storage temperature range (9) MIN MAX UNIT –65 150 °C This section includes the maximum power consumption for each power domain (core, etc.). Table 3-2 summarizes the power consumption at the ball level. These temperatures extreme do not simulate actual operating conditions but exaggerate any faults that might exist. PRODUCT PREVIEW (9) Submit Documentation Feedback ELECTRICAL CHARACTERISTICS 121 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 3-2. Estimated Maximum Power Consumption At Ball Level PARAMETER Signal Description vdd_mpu Processors vdd_core Core MAX ( T = 90°C) MAX ( T = 105°C) UNIT OMAP3515/03 (SmartReflex™ Enabled) 686 728 mA OMAP3515/03 (SmartReflex™ Disabled) 850 911 OMAP35 (SmartReflex™ Enabled) mA OMAP35 (SmartReflex™ Disabled) OMAP35 (SmartReflex™ Enabled) OMAP35(SmartReflex™ Disabled) PRODUCT PREVIEW OMAP3515 (SmartReflex™ Enabled) 433 490 OMAP3515 (SmartReflex™ Disabled) 509 599 OMAP3503 (SmartReflex™ Enabled) 328 382 OMAP3503(SmartReflex™ Disabled) 378 485 vdda_dac Video DAC 65 65 mA vdss_dpll_dll DLL + DPLL MPU, and core 25 25 mA vdds_dpll_per DPLL peripheral 1 and peripheral 2 15 15 mA vdds_sram Processors and core LDO (LDO1 and LDO2) 41 41 mA vdds_wkup_bg Bandgap, wakeup + LDO, EMU off 6 6 mA vdds_mem Standard I/Os (SDRC+GPMC) 37 37 mA vdds Standard I/Os (all excluding SDRC and GPMC) 63 63 mA vdds_mmc1 MMC I/O (1) 20 20 mA vdds_mmc1a Power supply for MMC IO [DAT4 – DAT8] 2 2 mA vpp eFuse 50 50 mA (1) 122 MMC card and I/O card are not included. ELECTRICAL CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 3.3 Recommended Operating Conditions All OMAP3515/03 modules are used under the operating conditions contained in Table 3-3. Note: To avoid significant device degradation for industrial temperature OMAP3515A/OMAP3503A devices (-40°C ≤ Tj ≤ 105°C), the following restrictions apply: • OPP5 is not supported.* • The total device POH must be limited to less than 50K.* *If an industrial temperature device is operated such that Tj never exceeds 90C (-40°C ≤Tj ≤ 90°C) then the OPP POH limits for commercial devices indicated above apply. Note: Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions. Table 3-3. Recommended Operating Conditions PARAMETER DESCRIPTION VDD1 (vdd_mpu), SmartReflex Enabled OMAP processor core supply VDD2 (vdd_core) SmartReflex Enabled VDD1 (vdd_mpu), SmartReflex Disabled VDD2 (vdd_core) SmartReflex Disabled OMAP processor core logic supply OMAP processor core supply OMAP processor core logic supply Submit Documentation Feedback MIN NOM MAX UNIT OPP5: Overdrive VDD1NOM (0.04*VDD1NOM) TBD VDD1NOM + (0.04*VDD1NOM) V OPP4: Mid-Overdrive VDD1NOM (0.04*VDD1NOM) TBD VDD1NOM + (0.04*VDD1NOM) V OPP3: Nominal VDD1NOM (0.04*VDD1NOM) TBD VDD1NOM + (0.04*VDD1NOM) V OPP2: Low-Power VDD1NOM (0.04*VDD1NOM) TBD VDD1NOM + (0.04*VDD1NOM) V OPP1: Ultra Low-Power VDD1NOM (0.04*VDD1NOM) TBD VDD1NOM + (0.04*VDD1NOM) V OPP3: Nominal VDD2NOM (0.04*VDD2NOM) TBD VDD2NOM + (0.04*VDD2NOM) V OPP2: Low-Power VDD2NOM (0.04*VDD2NOM) TBD VDD2NOM + (0.04*VDD2NOM) V OPP1: Ultra Low-Power VDD2NOM (0.04*VDD2NOM) TBD VDD2NOM + (0.04*VDD2NOM) V OPP5: Overdrive VDD1NOM (0.04*VDD1NOM) 1.35 VDD1NOM + (0.04*VDD1NOM) V OPP4: Mid-Overdrive VDD1NOM (0.04*VDD1NOM) 1.27 VDD1NOM + (0.04*VDD1NOM) V OPP3: Nominal VDD1NOM (0.04*VDD1NOM) 1.20 VDD1NOM + (0.04*VDD1NOM) V OPP2: Low-Power VDD1NOM (0.04*VDD1NOM) 1.00 VDD1NOM + (0.04*VDD1NOM) V OPP1: Ultra Low-Power VDD1NOM (0.04*VDD1NOM) 0.95 VDD1NOM + (0.04*VDD1NOM) V OPP3: Nominal VDD2NOM (0.04*VDD2NOM) 1.15 VDD2NOM + (0.04*VDD2NOM) V OPP2: Low-Power VDD2NOM (0.04*VDD2NOM) 1.00 VDD2NOM + (0.04*VDD2NOM) V OPP1: Ultra Low-Power VDD2NOM (0.04*VDD2NOM) 0.95 VDD2NOM + (0.04*VDD2NOM) V ELECTRICAL CHARACTERISTICS 123 PRODUCT PREVIEW To avoid significant device degradation for commercial temperature OMAP3515/OMAP3503 devices (0°C ≤ Tj ≤ 90°C), the device power-on hours (POH) must be limited to one of the following: • 100K total POH when operating across all OPPs and keeping the time spent at OPP5 to less than 23K POH. • 50K total POH when operating exclusively at OPP5. • 44K total POH with no restrictions to the proportion of these POH at operating points OPP1 - OPP5. OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 3-3. Recommended Operating Conditions (continued) PRODUCT PREVIEW PARAMETER DESCRIPTION MIN NOM MAX UNIT vdds Supply voltage for I/O macros 1.71 1.8 1.89 V vdds_mem Supply voltage for memory I/O macros 1.71 1.8 1.89 V vdds_mmc1 Supply voltage for MMC1 macro in 1.8-V mode 1.71 1.8 1.89 V Supply voltage for MMC1 macro in 3-V mode 2.7 3 3.3 V vdds_mmc1a Power supply for SIM I/Os 1.71 1.8 1.89 V vdds_wkup_bg Wakeup LDO 1.71 1.8 1.89 V vdda_dac Analog supply voltage for video DAC 1.71 1.8 1.89 V vdds_sram SRAM LDOs 1.71 1.8 1.89 V vdds_dpll_per Peripherals DPLLs power supply 1.71 1.8 1.89 V vdds_dpll_dll Supply voltage for DPLLs I/Os 1.71 1.8 1.89 V vpp (1) eFuse programming vss Ground 0 0 0 vssa_dac Dedicated ground for DAC 0 0 0 V TJ Operating junction temperature range 0 – 90 °C -40 – 105 °C (1) 124 Commercial Temperature Extended Temperature V V It is recommended not to connect this pin. It is just used for eFuse programming on package unit. ELECTRICAL CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 3.4 DC Electrical Characteristics Table 3-4 summarizes the dc electrical characteristics. Table 3-4. DC Electrical Characteristics PARAMETER MIN NOM MAX UNIT LVCMOS Pin Buffers - CBB: N28, M27, N27, N26, N25, P28,P27, P26, R27, R25/ CBC: N19, L18, M19, M18, K18, N20, M20, P17, P18, P19/ CUS: M23, L23, M22, M21, M20, N23 VIL VOH High-level input voltage Low-level input voltage High-level output voltage (2) vdds (1) = 1.8 V 0.65 × vdds (1) vdds + 0.3 vdds (1) = 3.0 V 0.625 × vdds (1) vdds + 0.3 vdds (1) = 1.8 V –0.3 0.35 × vdds vdds (1) = 3.0 V –0.3 0.25 × vdds vdds (1) = 1.8 V vdds (1) – 0.2 vdds VOL tT Low-level output voltage (2) Input transition time (rise time, tR or fall time, tF evaluated between 10% and 90% at PAD) (1) = 3.0 V V V V 0.75 × vdds (1) vdds (1) = 1.8 V 0.2 vdds (1) = 3.0 V 0.125 × vdds (1) Normal Mode 10 High-Speed Mode 3 V ns LVDS/CMOS Pin Buffers - CBB: AG19, AH19, AG18, AH18, AG17, AH17/ CBC: AE16, AE15, AD17, AE18, AD16, AE17/ CUS: AB18, AC18 Low-Power Receiver (LP-RX) VIL Low-level input threshold VIH High-level input threshold 800 mV Input hysteresis 25 mV VHYS 500 mV Ultralow-Power Receiver (ULP-RX) VIL-ULPM VIH Low-level input threshold, ULPM 300 High-level input threshold 880 mV mV High-Speed Receiver (HS-RX) VIDTH Differential input high threshold VIDTL Differential input low threshold –70 mV Maximum differential input voltage 270 mV VIDMAX VILHS Single-ended input low voltage VIHHS Single-ended input high voltage VCMRXDC 70 mV –40 Common-mode voltage mV 70 460 mV 330 mV LVDS/CMOS Pin Buffers - CBB: K28, L28, K27, L27/ CBC: P25, P26, N25, N26 / CUS: L24, K24, J23, K23 VCM Input common mode voltage range 600 Vos Receiver Input dc offset –20 Vid Receiver input differential amplitude 140 Input transition time (rise time, tR or fall time, tF evaluated between 10% and 90% at PAD) 267 tT 900 200 1200 mV 20 mV 400 mV 533 ps LVDS/CMOS Pin Buffers - CBB: AG22, AH22, AG23, AH23, AG24, AH24/ CBC: AE21, AE22, AE23, AE24, AD23, AD24 / CUS: AC19, AB19, AD20, AC20, AD21, AC21 High-Speed Transceiver (HS-TX) VOHHS HS output high voltage |VOD| HS transmit differential voltage 140 VCMTX HS transmit static common mode voltage 150 360 mV 200 270 mV 200 250 mV Low-Power Transceiver (LP-TX) (1) (2) This global value may be overridden on a per interface basis if another value is explicitly defined for that interface (for example, I2C). With 100 µA sink / source current at vddsxmin. Submit Documentation Feedback ELECTRICAL CHARACTERISTICS 125 PRODUCT PREVIEW VIH OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 3-4. DC Electrical Characteristics (continued) PARAMETER MIN VOL Thevenin output low level –50 VOH Thevenin output high level 1.1 VIL Low-level input threshold VIH High-level input threshold NOM 1.2 MAX UNIT 50 mV 1.3 V 550 mV Low-Power Receiver (LP-RX) VHYST Input hysteresis 880 mV 25 mV Ultralow-Power Receiver (ULP-RX) VIL-ULPS VIH Low-level input threshold, ULPM 300 High-level input threshold 880 mV mV PRODUCT PREVIEW subLVDS/CMOS Pin Buffers - CBB: AA27, AA28, AB27, AB28, AD27, AD28, AC28, AC27/ CBC: AC26, AD26, AA25, Y25, AA26, AB26, AC25, AB25/ CUS: V22, W22, Y22, AB22, AC23, AC22, W21, V21 Differential voltage range @ RL = 100 Ω Vod Vocm tT 100 150 Common mode voltage range 0.8 0.9 Input transition time (Vod rise time, tR or Vod fall time, tF evaluated between 20% and 80% at PAD) 200 200 mV 1 V 500 ps Standard LVCMOS Pin Buffers (3) High-level input voltage (Standard LVCMOS) 0.65 × vdds vdds + 0.3 V VIL (3) Low-level input voltage (Standard LVCMOS) - 0.3 0.35 × vdds V VHYS Hysteresis voltage at an input (4) VOH High-level output voltage, driver enabled, pullup or pulldown disabled VIH VOL 0.1 IO = IOH or IO = –2 mA vdds – 0.45 IO = IOH < |–2| mA vdds – 0.40 V Low-level output voltage with , driver enabled, IO = IOL or pullup or pulldown disabled IO = 2 mA 0.45 IO = IOL < 2 mA tT Input transition time (rise time, tR or fall time, tF evaluated between 10% and 90% at PAD) II Input current with VI = VI max Off-state output current for output in high impedance with driver only, driver disabled IOZ IZ V 0.40 10 (1) ns –1 1 µA –20 20 µA 20 µA 0 Off-state output current for output in high impedance with driver/receiver/pullup only, driver disabled, pullup not inhibited –100 Off-state output current for output in high impedance with driver/receiver/pulldown only, driver disabled, pulldown not inhibited 100 Total leakage current through the PAD connection of a driver/receiver combination that may include a pullup or pulldown. The driver output is disabled and the pullup or pulldown is inhibited. V – 20 LVCMOS Open-Drain Pin Buffers Dedicated to I2C IOs - CBB: K21, J21, AF14, AG14, AF15, AE15, AD26, AE26/ CBC: J25, J24, C2, C1, AB4, AC4, AD15, W16, A21, C21/ CUS: K20, K21, AC13, AC12, AC15, AC14, Y16, Y15 (3) (4) 126 VIH High level input voltage 0.7 x vdds vdds + 0.5 V VIL Low level input voltage - 0.5 0.3 x vdds V VOL Low-level output voltage open-drain at 3-mA sink current 0 0.2 x vdds V - 10 10 µA 10 pF II Input current at each I/O pin with an input voltage between 0.1 x vdds to 0.9 x vdds CI Capacitance for each I/O pin VIH/VIL (Standard LVCMOS) parameters are applicable for sys_altclk input clocks. Vhys is the magnitude of the difference between the positive-going threshold voltage VT+ and the negative-going voltage VT-. ELECTRICAL CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 3-4. DC Electrical Characteristics (continued) PARAMETER TOF Output fall time from VIHmin to VILmax with a bus capacitance CB from 10 pF to 400 pF MIN Fast mode 20 + 0.1CB Standard mode NOM MAX UNIT 250 ns 250 Output fall time with a capacitive load from 10 High-speed mode pF to 100 pF at 3-mA sink current 10 40 Output fall time with a capacitive load of 400 pF at 3-mA sink current 20 80 Output fall time with a capacitive load of 40 pF (for CBUS compatibility) 20 VIH High-level input voltage 0.7 x vdds vdds + 0.5 V VIL Low-level input voltage - 0.5 0.3 x vdds V VOH High-level output voltage at 4-mA sink current VOL Low-level output voltage at 4-mA sink current Submit Documentation Feedback vdds - 0.45 PRODUCT PREVIEW LVCMOS Open-Drain Pin Buffers Dedicated in GPIO mode - CBB: AF15, AE15, AF14, AG14, AD26, AE26 / CBC: C2, C1, AB4, AC4, AD15, W16, A21, C21/ CUS: AC15, AC14, AC13, AC12, Y16, Y15 V 0.45 ELECTRICAL CHARACTERISTICS V 127 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 3.5 Core Voltage Decoupling For module performance, decoupling capacitors are required to suppress the switching noise generated by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective when it is close to the device because this minimizes the inductance of the circuit board wiring and interconnects. Table 3-5 summarizes the power supplies decoupling characteristics. Table 3-5. Core Voltage Decoupling Characteristics MIN TYP MAX UNIT Cvdd_mpu (1) PARAMETER 50 100 120 nF Cvdd_core (1) 50 100 120 nF Cvdds_sram 100 nF PRODUCT PREVIEW Ccap_vdd_sram_mpu 0.7 1.0 1.3 µF Ccap_vdd_sram_core 0.7 1.0 1.3 µF Ccap_vdd_wkup 0.7 1.0 1.3 µF Cvdds_wkup_bg 100 nF Cvdds_dpll_dll 100 nF Cvdds_dpll_per 100 nF Cvdda_dac 100 nF Cvdds_mmc1 100 nF Cvdds_mmca 100 nF (1) 128 1 capacitor per 2 to 4 balls ELECTRICAL CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Figure 3-2 illustrates an example of power supply decoupling. OMAP Device vdds_sram vdds_sram Cvdds_sram Cvdda_dac cap_vdd_sram_mpu vdda_dac Video DAC vssa_dac Ccap_vdd_sram_mpu SRAM_LDO1 cap_vdd_sram_core SRAM_LDO2 BG vdds_wkup_bg vdds_mmc1 cap_vdd_wkup MMC IOs Cvdds_mmc1 vdds_wkup_bg Cvdds_wkup_bg WKUP_LDO vdds_mmc1 Ccap_vdd_sram_core PRODUCT PREVIEW vdda_dac Cvdd_wkup DPLL_MPU vdds_dpll_dll vdds_dpll_dll Cvdds_dpll_dll DPLL_CORE vdds_dpll_per DPLL5 vdds_dpll_per Cvdds_dpll_per DPLL4 vdd_mpu Cvdd_mpu Vdd_core Vdd_mpu MPU Core vdd_core Cvdd_core VSS 030-004 (1) Decoupling capacitors must be placed as closed as possible to the power ball. Choose the ground located closest to the power pin for each decoupling capacitor. Place the decoupling capacitor Ci in a group of 1, 2, or 3 balls; the total must be equal to the decoupling requirement. In case you interconnect powers, first insert the decoupling capacitor and then interconnect the powers. (2) The decoupling capacitor value depends on the board characteristics. Figure 3-2. Power Supply Decoupling Submit Documentation Feedback ELECTRICAL CHARACTERISTICS 129 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 3.6 Power-up and Power-down This section provides the timing requirements for the OMAP3515/03 hardware signals. 3.6.1 Power-up Sequence PRODUCT PREVIEW The following steps give an example of power-up sequence supported by the OMAP3515/03 device. 1. vdds and vdds_mem are ramped ensuring a level on the IO domain and sys_nrespwron must be low. At the same time, vdds_sram and vdds_wkup_bg can also be ramped. 2. Once vdds_wkup_bg rail is stabilized, vdd_core can be ramped. 3. Once vdd_core is stabilized, then vdd_mpu can be ramped. 4. vdds_dpll_dll and vdds_dpll_per rails can be ramped at any time during the above sequence. 5. sys_nrespwron can be released as soon as the vdds_pll_dll rail is stabilized, and sys_xtalin and sys_32k clocks are stabilized. 6. During the whole sequence above, sys_nreswarm is held low by OMAP3515/03. sys_nreswarm is released after the eFuse check has been performed; that is, after sys_nrespwron is released. 7. The other power supplies can then be turned on upon software request. Figure 3-3 shows the power-up sequence. Note: If an external square clock is provided, it could be started after sys_nrespwron release provided it is clean: no glitch, stable frequency, and duty cycle. 130 ELECTRICAL CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 1.8 V vdds_wkup_bg 1.8 V vdds_mem,vdds, vdds_sram ldo3 (internal) (2) vdd_core (2) vdd_mpu 1.8 V vdds_dpll_dll 1.8 V PRODUCT PREVIEW vdds_dpll_per sys_32k sys_nrespwron sys_xtalin EFUSE.RSTPWRON(internal) sys_nreswarm vdds_mmc1,vdds_mmc1a, vdda_dac(1), vpp 030-005 Figure 3-3. Power-up Sequence Submit Documentation Feedback ELECTRICAL CHARACTERISTICS 131 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 3.6.2 www.ti.com Power-down Sequence The OMAP3515/03 device proceeds with the power-down sequence shown in Figure 3-4. sys_nrespwron vdds_mmc1, vdda_dac PRODUCT PREVIEW vdds_wkup_bg vdd_mpu vdd_core vdds_mem, vdds, vdds_sram vdds_dpll_dll, vdds_dpll_per sys_32kin sys.clk 030-006 Figure 3-4. Power-down Sequence 132 ELECTRICAL CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 4 CLOCK SPECIFICATIONS The OMAP3515/03 device has three external input clocks, a low frequency (sys_32k), a high frequency (sys_xtalin), and an optional (sys_altclk). The OMAP3515/03 device has two configurable output clocks, sys_clkout1 and sys_clkout2. Figure 4-1 shows the interface to the external clock sources and clock outputs. OMAP sys_32k Power IC sys_clkout1 To Peripherals (From OSC_CLK: 12, 13,16.8, 19.2, 26, or 38.4 MHz) sys_clkout2 To Peripherals (From OSC_CLK: 12,13, 16.8, 19.2, 26, or 38.4 MHz, core_clk [DPLL, up to 332 MHz], DPLL-96 MHz or DPLL-54 MHz outputs with a divider of 1, 2, 4, 8, or 16) sys_xtalout To Quartz (Oscillator output) or Unconnected To Quartz (Oscillator input) or Square Clock sys_xtalin sys_clkreq Clock Request. To Square Clock Source or from Peripherals sys_xtalout sys_xtalout Oscillator is Used Unconnected Oscillator is Bypassed sys_xtalin sys_clkreq PRODUCT PREVIEW Alternate Clock Source Selectable (54, 48 MHz or other [up to 54 MHz]) sys_altclk GPin sys_xtalin sys_clkreq Square Clock Source 030-007 Figure 4-1. Clock Interface The OMAP3515/03 device operation requires the following three input clocks: • The 32-kHz frequency is used for low frequency operation. It supplies the wake-up domain for operation in lowest power mode (off mode). This clock is provided through the sys_32k pin. • The system alternative clock can be used (through the sys_altclk pin) to provide alternative 48 or 54 MHz or other clock source (up to 54 MHz). • The system clock input (12, 13, 16.8, 19.2, 26, or 38.4 MHz) is used to generate the main source clock of the OMAP3515/03 device. It supplies the DPLLs as well as several OMAP modules. The system clock input can be connected to either: – A crystal oscillator clock managed by sys_xtalin and sys_xtalout. In this case, the sys_clkreq is used as an input (GPIN). – A CMOS digital clock through the sys_xtalin pin. In this case, the sys_clkreq is used as an output to request the external system clock. The OMAP3515/03 outputs externally two clocks: • sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) at any time. It can be controlled by software or externally using sys_clkreq control. When the device is in the off state, the sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the device. The off state polarity of sys_clkout1 is programmable. Submit Documentation Feedback CLOCK SPECIFICATIONS 133 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 • www.ti.com sys_clkout2 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz), core_clk (core DPLL output), 96 MHz or 54 MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is programmable. This output is active only when the core power domain is active. For more information on the OMAP3515/03 Applications Processor clocking structure, see the Power, Reset, and Clock management (PRCM) chapter of the OMAP35x Applications Processor TRM (literature number SPRUFA5). 4.1 Input Clock Specifications The clock system accepts three input clock sources: • 32-kHz digital CMOS clock • Crystal oscillator clock or CMOS digital clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) • Alternate clock (48 or 54 MHz, or other up to 54 MHz) PRODUCT PREVIEW 4.1.1 Clock Source Requirements Table 4-1 illustrates the requirements to supply a clock to the OMAP3515/03 device. Table 4-1. Clock Source Requirements PAD sys_32k sys_xtalout sys_xtalin sys_altclk 4.1.2 CLOCK FREQUENCY STABILITY 32.768 kHz ± 200 ppm DUTY CYCLE JITTER TRANSITION < 20 ns Crystal ± 25 ppm na na na 12, 13, 16.8, 19.2, 26, or 38.4 MHz Square ± 50 ppm 45% to 55% < 1% < 2.5 ns ± 50 ppm 40% to 60% < 1% < 5 ns 12, 13, 16.8, or 19.2 MHz 48 or 54 MHz External Crystal Description To supply a 12-, 13-, 16.8-, or 19.2-MHz clock to the OMAP3515/03, an external crystal can be connected to the sys_xtalin and sys_xtalout pins. Figure 4-2 describes the crystal implementation. OMAP Device sys_xtalin sys_xtalout Optional Rbias Optional Rd Cf2 Cf1 Crystal 030-008 Figure 4-2. Crystal Implementation(1)(2)(3)(4) (1) On the PCB, the oscillator components (crystal, foot capacitors, optional Rbias and Rd) must be located close to the package. All these components must be routed first with the lowest possible number of board vias. (2) An optional resistor Rd can be added in series with the crystal to debug or filter the harmonics; a footprint must be reserved on the PCB for use with 10-MHz crystals and feature low-drive levels. 134 CLOCK SPECIFICATIONS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 (3) A 120-kΩ internal bias resistor Rbias is used. The feedback resistor Rbias provides negative feedback to the oscillator to put it in the linear operating region; thus oscillation begins when power is applied. (4) Cf1 and Cf2 represent the total capacitance of the PCB and components excluding the power IC and crystal. Their values in fact depend on the crystal datasheet. In the datasheet of the crystal, the frequency is specified at a specific load capacitor value which is the equivalent capacitor of the two capacitors Cf1 and Cf2 connected to sys_xtalin and sys_xtalout. The frequency of the oscillations depends on the value of the capacitors (10 pF corresponds to a load capacitor of 5 pF for the crystal). The crystal must be in the fundamental mode of operation and parallel resonant. Table 4-2 summarizes the required electrical constraints. Table 4-2. Crystal Electrical Characteristics DESCRIPTION Parallel resonance crystal frequency (1) CL Load capacitance for crystal parallel resonance TYP Crystal ESR (12 and 13 MHz) ESR16.8&19.2 Crystal ESR (16.8 and 19.2 MHz) (1) Co Crystal shunt capacitance Lm Crystal motional inductance for fp = 12 MHz Cm Crystal motional capacitance DL Crystal drive level Rbias Internal bias resistor RpdXI Pulldown resistor on sys_xtalin when oscillator is disabled MAX 12, 13, 16.8, or 19.2 5 (1) ESR12&13 (1) MIN UNIT MHz 20 pF 80 Ω 50 Ω 1 7 pF 35 mH 5 100 fF 0.5 mW 300 kΩ 5 kΩ 30 120 Measured with the load capacitance specified by the crystal manufacturer. This load is defined by the foot capacitances tied in series. If CL = 20 pF, then both foot capacitors will be Cf1 = Cf2 = 40 pF. Parasitic capacitance from package and board must also be taken in account. 2 ESR=Rm 1+ C0 CL When selecting a crystal, the system design must take into account the temperature and aging characteristics of a crystal versus the user environment and expected lifetime of the system. Table 4-3 details the switching characteristics of the oscillator and the input requirements of the 12-, 13-, 16.8-, or 19.2-MHz input clock. Table 4-3. Base Oscillator Switching Characteristics NAME DESCRIPTION fp Oscillation frequency tsX Start-up time (1) (2) (1) (2) MIN TYP 12, 13, 16.8, or 19.2 8 MAX UNIT MHz ms Start-up time defined as time interval between oscillator control signal release and sys_xtalin amplitude at 50% of its final value (vdd and vdds supplies ramped and stable). The start-up time can be performed in function of the crystal characteristics. 8-ms minimum only when using the internal oscillator; it is programmable after reset for wake-up. At power-on reset, the time is adjustable using the pin itself. The reset must be released when the oscillator or clock source is stable. Before the processor boots up and the oscillator is set to bypass mode, there is a start-up time when the internal oscillator is in application mode and receives a square wave. The start-up time in this case is about 100 µs. For fp = 12 or 13 MHz: CL = 13.5 pF and Lm = 35 mH For fp = 16.8 or 19.2 MHz: CL = 9 pF and Lm = 15 mH 4.1.3 Clock Squarer Input Description A 1.8-V CMOS clock squarer is another source that can supply a 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz clock to the OMAP3515/03. An analog clock squarer function converts a low-amplitude sinusoidal clock into a low-jitter digital signal. It can be connected to input pin sys_xtalin (sys_xtalout unconnected). Figure 4-3 illustrates the effective connections. Submit Documentation Feedback CLOCK SPECIFICATIONS 135 PRODUCT PREVIEW NAME fp OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com OMAP Device Oscillator In Bypass Mode sys_clkreq sys_xtalin sys_xtalout Clock Squarer Source PRODUCT PREVIEW 030-010 Figure 4-3. Clock Squarer Source Connection To connect a digital clock source, the oscillator is configured in bypass mode(1). The sys_clkreq(2) pin is an OMAP3515/03 output which can be used to switch the clock source on or off. 1. Pin sys_xtalout is not used in this mode. It must be left unconnected. 2. Once the system is powered up, the clock squarer source or crystal oscillator source can be applied; however, this affects the performance. The input source must be configured after power up to attain the desired system requirements. Table 4-4 summarizes the electrical constraints required by the clock squarer used in the fundamental mode of operation. Table 4-4. Base Oscillator Electrical Characteristics (in Bypass Mode) NAME DESCRIPTION Frequency (1) f MIN TYP MAX 12, 13, 16.8, 19.2, 26, or 38.4 UNIT MHz (2) tsX Start-up time RpdXI Pulldown resistor on sys_xtalin when oscillator is disabled 5 kΩ IDDQ Current consumption on VDDS when sys_xtalin = 0 and in power-down mode 1 µA (1) (2) ms Measured with the load capacitance specified by the manufacturer. Parasitic capacitance from package and board must also be taken in account. Before the processor boots up and the oscillator is set to bypass mode, there is a start-up time when the internal oscillator is in application mode and receives a square wave. The start-up time in this case is about 100 µs. Table 4-5 details the input requirements of the 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz input clock. Table 4-5. 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz Input Clock Squarer Timing Requirements NAME DESCRIPTION MIN TYP MAX OCS0 1 / tc(xtalin) Frequency, sys_xtalin OCS1 tw(xtalin) Pulse duration, sys_xtalin low or high OCS2 tJ(xtalin) Peak-to-peak jitter (1), sys_xtalin OCS3 tR(xtalin) Rise time, sys_xtalin 2.5 OCS4 tF(xtalin) Fall time, sys_xtalin 2.5 ns OCS5 tJ(xtalin) Frequency stability, sys_xtalin ±25 ppm (1) 136 12, 13, 16.8, 19.2, 26, or 38.4 UNIT 0.45 * tc(xtalin) 0.55 * tc(xtalin) –1% 1% MHz ns ns Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300 period samples. The sinusoidal noise is added on top of the vdds supply voltage. CLOCK SPECIFICATIONS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 OCS0 OCS1 OCS1 sys.xtalin 030-011 Figure 4-4. Crystal Oscillator in Bypass Mode 4.1.4 External 32-kHz CMOS Input Clock A 32.768-kHz clock signal (often abbreviated to 32-kHz) can be supplied by an external 1.8-V CMOS signal on pin sys_32k. Table 4-6 summarizes the electrical constraints imposed to the clock source. Table 4-6. 32-kHz Input Clock Source Electrical Characteristics DESCRIPTION Frequency CI Input capacitance RI Input resistance MIN TYP MAX UNIT 32.768 PRODUCT PREVIEW NAME f kHz 0.44 pF 106 0.25 GΩ Table 4-7 details the input requirements of the 32-kHz input clock. Table 4-7. 32-kHz Input Clock Source Timing Requirements (1) NAME DESCRIPTION MIN TYP MAX UNIT CK0 1 / tc(32k) Frequency, sys_32k CK3 tR(32k) Rise time, sys_32k 20 ns CK4 tF(32k) Fall time, sys_32k 20 ns CK5 tJ(32k) Frequency stability, sys_32k ±200 ppm (1) 32.768 kHz See Table 3-4, Electrical Characteristics, Standard LVCMOS IOs part for sys_32k VIH/VIL parameters. CK0 CK1 CK1 sys_32k 030-012 Figure 4-5. 32-kHz CMOS Clock 4.1.5 External sys_altclk CMOS Input Clock A 48- or 54-MHz clock signal can be supplied by an external 1.8-V CMOS signal on pin sys_altclk. Table 4-8 summarizes the electrical constraints imposed by the clock source. Table 4-8. 48- or 54-MHz Input Clock Source Electrical Characteristics NAME DESCRIPTION f Frequency , sys_altclk CI Input capacitance RI Input resistance MIN TYP MAX 48 or 54 MHz 0.74 0.25 UNIT pF 106 GΩ Table 4-9 details the input requirements of the 48- or 54-MHz input clock. Submit Documentation Feedback CLOCK SPECIFICATIONS 137 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 4-9. 48- or 54-MHz Input Clock Source Timing Requirements (1) (2) DESCRIPTION MIN ALT0 NAME 1 / tc(altclk) Frequency, sys_altclk 48 or 54 ALT1 tw(altclk) Pulse duration, sys_altclk low or high 0.40 * tc(altclk) 0.60 * tc(altclk) ALT2 tJ(altclk) Peak-to-peak jitter (1), sys_altclk –1% 1% ALT3 tR(altclk) Rise time, sys_altclk ALT4 tF(altclk) Fall time, sys_altclk ALT5 tJ(altclk) Frequency stability, sys_altclk (1) (2) TYP MAX UNIT MHz 5 ns ns 5 ns ± 50 ppm Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300 period samples. The sinusoidal noise is added on top of the vdds supply voltage. See Table 3-4, Electrical Characteristics, for sys_altclk VIH/VIL parameters. PRODUCT PREVIEW ALT0 ALT1 ALT1 sys_altclk 030-013 Figure 4-6. Alternate CMOS Clock 138 CLOCK SPECIFICATIONS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 4.2 Output Clock Specifications Two output clocks (pin sys_clkout1 and pin sys_clkout2) are available: • sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) at any time. It can be controlled by software or externally using sys_clkreq control. When the device is in the off state, the sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the device. The off state polarity of sys_clkout1 is programmable. • sys_clkout2 can output sys_clk (12, 13, 16.8, 19.2, 26, or 38.4 MHz), CORE_CLK (core DPLL output, 332 MHz maximum), APLL-96 MHz, or APLL-54 MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is programmable. This output is active only when the core domain is active. Table 4-10 summarizes the sys_clkout1 output clock electrical characteristics. NAME f DESCRIPTION MIN Frequency CI Load capacitance (1) (1) TYP MAX UNIT 12, 13, 16.8, 19.2, 26, or 38.4 MHz f(max) = 38.4 MHz 37 pF f(max) = 26 MHz 50 The load capacitance is adapted to a frequency. Table 4-11 details the sys_clkout1 output clock timing characteristics. Table 4-11. sys_clkout1 Output Clock Switching Characteristics NAME DESCRIPTION MIN f 1 / CO0 Frequency CO1 tw(CLKOUT1) Pulse duration, sys_clkout1 low or high TYP MAX UNIT 12, 13, 16.8, 19.2, 26, or 38.4 MHz 0.40 * 0.60 * tc(CLKOUT1) tc(CLKOUT1) ns CO2 tR(CLKOUT1) Rise time, sys_clkout1 (1) 5.5 ns CO3 tF(CLKOUT1) Fall time, sys_clkout1 (1) 5.5 ns (1) With a load capacitance of 25 pF. CO0 CO1 CO1 sys_clkout 030-014 Figure 4-7. sys_clkout1 System Output Clock Table 4-12 summarizes the sys_clkout2 output clock electrical characteristics. Table 4-12. sys_clkout2 Output Clock Electrical Characteristics NAME DESCRIPTION f Frequency, sys_clkout2 CL Load capacitance (1) (1) MIN f(max) = 166 MHz 2 TYP 8 MAX UNIT 322 MHz 12 pF The load capacitance is adapted to a frequency. Table 4-13 details the sys_clkout2 output clock timing characteristics. Submit Documentation Feedback CLOCK SPECIFICATIONS 139 PRODUCT PREVIEW Table 4-10. sys_clkout1 Output Clock Electrical Characteristics OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 4-13. sys_clkout2 Output Clock Switching Characteristics NAME DESCRIPTION MIN f 1 / CO0 Frequency CO1 tw(CLKOUT2) Pulse duration, sys_clkout2 low or high CO2 tR(CLKOUT2) Rise time, sys_clkout2 (1) CO3 tF(CLKOUT2) Fall time, sys_clkout2 (1) (1) TYP 0.40 * tc(CLKOUT2) MAX UNIT 322 MHz 0.60 * tc(CLKOUT2) ns 3.7 ns 4.3 ns With a load capacitance of 12 pF. CO0 CO1 CO1 sys_clkout 030-015 PRODUCT PREVIEW Figure 4-8. sys_clkout2 System Output Clock 140 CLOCK SPECIFICATIONS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 4.3 DPLL and DLL Specifications The OMAP3515/03 integrates six DPLLs and a DLL. The PRM and CM drive five of them, while the sixth (not supported) is controlled by the display controller. The five main DPLLs are: • DPLL1 (MPU) • DPLL2 (not supported on OMAP3515/03 devices) • DPLL3 (Core) • DPLL4 (Peripherals) • DPLL5 (Second Peripherals DPLL) Figure 4-9 illustrates the DLL and DPLL implementation. vdds_dpll_dll PRODUCT PREVIEW OMAP Power Rail DPLL1 DPLL2 DLL DPLL3 DPLL4 DPLL5 vdds_dpll_per 030-016 (1) DPLL2 is not supported on OMAP3515/03 devices. Figure 4-9. DPLL and DLL Implementation For more information on the OMAP3530/25 Applications Processor DPLLs and clocking structure, see the Power, Reset, and Clock management (PRCM) chapter of the OMAP35x Applications Processor TRM (literature number SPRUFA5). 4.3.1 Digital Phase-Locked Loop (DPLL) The DPLL provides all interface clocks and some functional clocks (such as the processor clocks) of the OMAP3515/03 device. DPLL1 and DPLL2 get an always-on clock used to produce the synthesized clock. They get a high-speed bypass clock used to switch the DPLL output clock on this high-speed clock during bypass mode. The high-speed bypass clock is an L3 divided clock (programmable by 1 or 2) that saves DPLL processor power consumption when the processor does not need to run faster than the L3 clock speed, or optimizes performance during frequency scaling. Each DPLL synthesized frequency is set by programming M (multiplier) and N (divider) factors. In addition, all DPLL outputs can be controlled by an independent divider (M2 to M6). The clock generating DPLLs of the OMAP3515/03 device have following features: • Independent power domain per DPLL • Controlled by clock-manager (CM) Submit Documentation Feedback CLOCK SPECIFICATIONS 141 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 • • • www.ti.com Fed with always-on system clock with independent gating control per DPLL Analog part supplied through dedicated power supply (1.8 V) and an embedded LDO to get rid of 1-MHz noise Up to five independent output dividers for simultaneous generation of multiple clock frequencies 4.3.1.1 DPLL1 (MPU) DPLL1 is located in the MPU subsystem and supplies all clocks of the subsystem. All MPU subsystem clocks are internally generated in the subsystem. When the core domain is on, it can use the DPLL3 (CORE DPLL) output as a high-frequency bypass input clock. 4.3.1.2 DPLL3 (CORE) PRODUCT PREVIEW DPLL3 supplies all interface clocks and also a few module functional clocks. It can be also source of the emulation trace clock. It is located in the core domain area. All interface clocks and a few module functional clocks are generated in the CM. When the core domain is on, it can be used as a bypass input to DPLL1 and DPLL2. 4.3.1.3 DPLL4 (Peripherals) DPLL4 generates clocks for the peripherals. It supplies five clock sources: 96-MHz functional clocks to subsystems and peripherals, 54 MHz to TV DAC, display functional clock, camera sensor clock, and emulation trace clock. It is located in the core domain area. All interface clocks and few module functional clocks are generated in the CM. Its outputs to the DSS, PER, and EMU domains are propagated with always-on clock trees. 4.3.1.4 DPLL5 (Second peripherals DPLL) DPLL5 supplies the 120-MHz functional clock to the CM. 4.3.2 Delay-Locked Loops (DLL) The SDRC includes analog-controlled delay technology for interfacing high-speed mobile DDR memory components. For more information, see the SDRC-GPMC chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. A DLL is a calibration module used on dynamic track of voltage and temperature variations, as well as to compensate the silicon process dispersion. The SDRC DLL has four modes of operation: 1. APPLICATION MODE 0: used to generate 72° delay 2. APPLICATION MODE 1: used to generate 90° delay 3. MODEMAXDELAY: used for low frequency operation where we do not have the requirement of accurate 72° or 90° phase shift 4. IDLE MODE: a low-power state that allows the DLL to gain lock quickly on exit from this mode 142 CLOCK SPECIFICATIONS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com 4.3.3 SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 DPLLs and DLL Characteristics Several specifications characterize the six DPLLs. Table 4-14 summarizes the DPLL characteristics and assumes testing over recommended operating conditions. Table 4-14. DPLL Characteristics PARAMETER MIN TYP MAX UNIT vdds_dpll_per 1.71 1.8 1.89 V vdds_dpll_dll 1.71 1.8 1.89 V 25 107 °C COMMENTS (1) At module pins (+5%, –10%) TJ Junction temperature –40 Will not unlock after lock over this range for slow temperature drifts finput Input reference frequency (2) 0.75 65 MHz FINP finternal Internal reference frequency 0.75 2.1 MHz FREQSEL3 = 0; FINT = FINP/(N+1) 7.5 21 MHz FREQSEL3 = 1; FINT = FINP/(N+1) foutput CLKOUT output frequency 25 900 MHz foutput*2 CLKOUTx2 output frequency 50 1800 MHz tlock Frequency lock time (3) 71.4 200 µs 150 FINT cycles; FREQSEL3 = 0 37.1 104 µs 780 FINT cycles; FREQSEL3 = 1 166.7 466.7 µs 350 FINT cycles; FREQSEL3 = 0 46.7 130.7 µs 980 FINT cycles; FREQSEL3 = 1 4.8 13.3 µs 10 FINT cycles plock trelock Phase lock time Relock time – frequency lock (4) PRODUCT PREVIEW NAME Lowcurrstby = 0; FREQSEL3 = 0 4.8 13.3 µs 19 53.3 µs 19 53.3 µs 100 FINT cycles Lowcurrstby = 0; FREQSEL3 = 1 40 FINT cycles Lowcurrstby = 1; FREQSEL3 = 0 400 FINT cycles Lowcurrstby = 1; FREQSEL3 = 1 prelock Relock time – Phase lock (4) 71.4 200 µs 11.9 33.3 µs 150 FINT cycles Lowcurrstby = 0; FREQSEL3 = 0 250 FINT cycles Lowcurrstby = 0; FREQSEL3 = 1 95.2 266.7 µs 26.7 74.7 µs 200 FINT cycles Lowcurrstby = 1; FREQSEL3 = 0 560 FINT cycles Lowcurrstby = 1; FREQSEL3 = 1 Table 4-15 shows the DPLL1 clock frequency ranges. Note: The DPLL1 clock frequency ranges depend on the VDD1 (vdd_mpu) operating point. (1) (2) (3) (4) freqsel needs to be programmed accordingly to reference clock and DPLL divider (register setting), Lowcurrstdby depends on the targeted DPLL power state (dynamic). Lowcurrstdby = 0 then DPLL is in normal mode Lowcurrstdby = 1 then DPLL is in low-power mode Input frequencies below 0.75 MHz are possible with performance penalty. Maximum frequency for nominal conditions. Speed binning possible above fmax. Relock time assumes typical operating conditions, 4°C maximum temperature drift (see the Functional Specification for more detailed information). Submit Documentation Feedback CLOCK SPECIFICATIONS 143 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 4-15. DPLL1 Clock Frequency Ranges Clock Signal Description Max Unit DPLL1_ALWON _FCLK DPLL1 reference clock input, taken from PRM SYS_CLK. TBD MHz DPLL1_FCLK DPLL1 high-frequency bypass clock input, taken from CM CORE_CLK. TBD MHz OPP5 600 MHz OPP4 550 MHz OPP3 500 MHz OPP2 500 MHz OPP1 500 MHz OPP5 600 MHz OPP4 550 MHz OPP3 500 MHz OPP2 250 MHz OPP1 125 MHz DPLL1 internal clock signal, generated through DPLL1 Multiplier and Divider. DPLL1: CLKOUTX2 PRODUCT PREVIEW MPU_CLK DPLL1 output clock, generated from CLKOUT_M2X2. Table 4-16 through Table 4-18 show the DPLL3 clock frequency ranges. Note: The DPLL3 clock frequency ranges depend on the VDD2 (vdd_core) operating point and the L3 clock speed configuration. Table 4-16. DPLL3 Clock Frequency Ranges, VDD2 OPP3 Config 1 (166 MHz) Clock Signal Description Config 2 (133 MHz) Config 3 (100 MHz) Min Max Min Max Min Max Unit DPLL3_ALWON_FCLK DPLL3 input reference clock, generated by PRM. TBD TBD TBD TBD TBD TBD MHz DPLL3: CLKOUTX2 DPLL3 internal clock signal, generated through DPLL3 Multiplier and Divider. 50 664 50 532 50 400 MHz DPLL3: CLKOUT DPLL3 internal clock signal, generated by dividing DPLL3 CLKOUTX2 by 2. 25 332 25 266 25 200 MHz CM: CORE_CLK Output of clock manager (CM), generated directly from DPLL3 CLKOUT_M2. - 332 - 266 - 200 MHz CM: L3_ICLK Output of clock manager (CM), generated using DPLL3 CLKOUT_M2X2 and divider. - 166 - 133 - 100 MHz CM: L4_ICLK Output of clock manager (CM), generated using CM L3_ICLK and divider. - 83 - 66.5 - 50 MHz SGX SGX input clock, taken from CM CORE_CLK. - 110.67 - 88.67 - 66.67 MHz SDRC SDRC input clock, taken from CM L3_ICLK. - 166 - 133 - 100 MHz GPMC GPMC input clock, taken from CM L3_ICLK. - 83 - 66.5 - 100 MHz Table 4-17. DPLL3 Clock Frequency Ranges, VDD2 OPP2 Config 1 (83 MHz) Clock Signal DPLL3_ALWON_FCLK 144 Description DPLL3 input reference clock, generated by PRM. CLOCK SPECIFICATIONS Config 2 (100 MHz) Min Max Min Max TBD TBD TBD TBD Unit MHz Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 4-17. DPLL3 Clock Frequency Ranges, VDD2 OPP2 (continued) Clock Signal Description Config 2 (100 MHz) Min Max Min Max Unit DPLL3: CLKOUTX2 DPLL3 internal clock signal, generated through DPLL3 Multiplier and Divider. 50 664 50 400 MHz DPLL3: CLKOUT DPLL3 internal clock signal, generated by dividing DPLL3 CLKOUTX2 by 2. 25 332 25 200 MHz CM: CORE_CLK Output of clock manager (CM), generated directly from DPLL3 CLKOUT_M2. - 166 - 200 MHz CM: L3_ICLK Output of clock manager (CM), generated using DPLL3 CLKOUT_M2X2 and divider. - 83 - 100 MHz CM: L4_ICLK Output of clock manager (CM), generated using CM L3_ICLK and divider. - 41.5 - 50 MHz SGX SGX input clock, taken from CM CORE_CLK. - 55.53 - 66.67 MHz SDRC SDRC input clock, taken from CM L3_ICLK. - 83 - 100 MHz GPMC GPMC input clock, taken from CM L3_ICLK. - 83 - 50 MHz PRODUCT PREVIEW Config 1 (83 MHz) Table 4-18. DPLL3 Clock Frequency Ranges, VDD2 OPP1 Config 1 (40 MHz) Clock Signal Description Unit Min Max DPLL3_ALWON_FCLK DPLL3 input reference clock, generated by PRM. TBD TBD MHz DPLL3: CLKOUTX2 DPLL3 internal clock signal, generated through DPLL3 Multiplier and Divider. 50 664 MHz DPLL3: CLKOUT DPLL3 internal clock signal, generated by dividing DPLL3 CLKOUTX2 by 2. 25 332 MHz CM: CORE_CLK Output of clock manager (CM), generated directly from DPLL3 CLKOUT_M2. - 83 MHz CM: L3_ICLK Output of clock manager (CM), generated using DPLL3 CLKOUT_M2X2 and divider. - 41.5 MHz CM: L4_ICLK Output of clock manager (CM), generated using CM L3_ICLK and divider. - 20.75 MHz SGX SGX input clock, taken from CM CORE_CLK. - N/A MHz SDRC SDRC input clock, taken from CM L3_ICLK. - 41.5 MHz GPMC GPMC input clock, taken from CM L3_ICLK. - 41.5 MHz Table 4-19 summarizes the DLL characteristics. Table 4-19. DLL Characteristics MIN NOM MAX UNIT Supply voltage vdds_dpll_dll PARAMETER 1.71 1.8 1.89 V Junction operating temperature –40 25 107 °C Input clock frequency 66 120 133 MHz 83 120 166 Input load (1) APPLICATION MODE 0 APPLICATION MODE 1 15 fF Lock time (2) 500 Clocks Relock time 500 ns (1) (2) COMMENTS IDLE to MODEMAXDELAY This parameter is design goal and is not tested on silicon. Lock signal would go high from power down within 500 clocks. Lock signal switches to low state when the input clock is switched off after 3 µs. Submit Documentation Feedback CLOCK SPECIFICATIONS 145 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 4-19. DLL Characteristics (continued) PARAMETER (Mode transitions through idle mode) MIN NOM MAX UNIT 150 372 Clocks COMMENTS 1 2 µs IDLE to APPLICATION MODE @133 MHz 1 1.5 µs IDLE to APPLICATION MODE @166 MHz IDLE to APPLICATION MODE 1 or 0 PRODUCT PREVIEW 146 CLOCK SPECIFICATIONS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com 4.3.4 SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 DPLL and DLL Noise Isolation The DPLL and DLL require dedicated power supply pins to isolate the core analog circuit from the switching noise generated by the core logic that can cause jitter on the clock output signal. Guard rings are added to the cell to isolate it from substrate noise injection. The vdd supplies are the most sensitive to noise; decoupling capacitance is recommended below the supply rails. The maximum input noise level allowed is 30 mVPP for frequencies below 1 MHz. Figure 4-10 illustrates an example of a noise filter. OMAP Device Noise Filter DPLL_MPU DPLL2 DPLL_CORE PRODUCT PREVIEW vdds_dpll_dll C DLL Noise Filter vdds_dpll_per DPLL5 C DPLL4 030-017 (1) DPLL2 is not supported on OMAP3515/03 devices. Figure 4-10. DPLL and DLL Noise Filter(1) Table 4-20 specifies the noise filter requirements. Table 4-20. DPLL and DLL Noise Filter Requirements NAME MIN Filtering capacitor (1) (2) (3) (4) TYP 100 MAX UNIT nF The capacitors must be inserted between power and ground as close as possible. This circuit is provided only as an example. The filter must be located as close as possible to the device. No filtering required if noise is below 10 mVPP. Submit Documentation Feedback CLOCK SPECIFICATIONS 147 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 5 VIDEO DAC SPECIFICATIONS A dual-display interface equips the OMAP3515/03 processor. This display subsystem provides the necessary control signals to interface the memory frame buffer directly to the external displays (TV-set). Two (one per channel) 10-bit current steering DACs are inserted between the DSS and the TV set to generate the video analog signal. One of the video DACs also includes TV detection and power-down mode. Figure 5-1 illustrates the OMAP3515/03 DAC architecture. For more information, see the DSS chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. OMAP Device TV DCT PRODUCT PREVIEW DIN1[9:0] ROUT1 tv_vfb1 TVOUT BUFFER Video DAC 1 tv_out1 DSS tv_vfb2 TVOUT TVOUT BUFFER BUFFER Video DAC 2 ROUT2 DIN2[9:0] tv_out2 vdda_dac V_ref vssa_dac tv_vref CBG 030-018 Figure 5-1. Video DAC Architecture The following paragraphs detail the 10-bit DAC interface pinout, static and dynamic specifications, and noise requirements. The operating conditions and absolute maximum ratings are detailed in Table 5-2 and Table 5-4. 5.1 Interface Description Table 5-1 summarizes the external pins of the video DAC. Table 5-1. External Pins of 10-bit Video DAC PIN NAME I/O DESCRIPTION tv_out1 O TV analog output composite 148 VIDEO DAC SPECIFICATIONS DAC1 video output. An external resistor is connected between this node and tv_vfb1. The nominal value of ROUT1 is 1650 Ω. Finally, note that this is the output node that drives the load (75 Ω). Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 5-1. External Pins of 10-bit Video DAC (continued) I/O DESCRIPTION tv_out2 O TV analog output S-VIDEO DAC2 video output. An external resistor is connected between this node and tv_vfb2. The nominal value of ROUT2 is 1650 Ω. Finally, note that this is the output node that drives the load (75 Ω). tv_vref I Reference output voltage from internal bandgap A decoupling capacitor (CBG) needs to be connected for optimum performance. tv_vfb1 O Amplifier feedback node Amplifier feedback node. An external resistor is connected between this node and tv_out1. The nominal value of ROUT1 is 1650 Ω (1%). tv_vfb2 O Amplifier feedback node Amplifier feedback node. An external resistor is connected between this node and tv_out2. The nominal value of ROUT2 is 1650 Ω (1%). PRODUCT PREVIEW PIN NAME Submit Documentation Feedback VIDEO DAC SPECIFICATIONS 149 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 5.2 Electrical Specifications Over Recommended Operating Conditions (TMIN to TMAX, vdda_dac = 1.8 V, ROUT1/2 = 1650 Ω, RLOAD = 75 Ω, unless otherwise noted) Table 5-2. DAC – Static Electrical Specification PARAMETER R CONDITIONS/ASSUMPTIONS MIN Resolution TYP MAX 10 UNIT Bits DC ACCURACY INL (1) Integral nonlinearity –1 1 LSB DNL (2) Differential nonlinearity –1 1 LSB ANALOG OUTPUT RLOAD = 75 Ω PRODUCT PREVIEW - Full-scale output voltage - Output offset voltage 0,7 - Output offset voltage drift - Gain error –17 RVOUT Output impedance 67.5 0.525 0.88 1 V 50 mV 20 mV/°C 19 % FS 75 82.5 Ω 0.55 0.575 V REFERENCE VREF Reference voltage range - Reference noise density RSET Full-scale current adjust resistor PSRR Reference PSRR (3) (Up to 6 MHz) 100-kHz reference noise bandwidth 129 3700 4000 4200 Ω 40 dB POWER CONSUMPTION Ivdda-up Analog Supply Current (4) 2 channels, no load 8 mA - Analog supply driving a 75-Ω load (RMS) 2 channels 50 mA Lasts less than 1 ns 60 mA Measured at fCLK = 54 MHz, fOUT = 2 MHz sine wave, vdd = 1.3 V 2 mA Ivdda-up (peak) Peak analog supply current: Ivdd-up Digital supply current (5) Peak digital supply current (6) Lasts less than 1 ns 2.5 mA Ivdda-down Analog power at power-down T = 30°C, vdda = 1.8 V 1.5 mA Ivdd-down Digital power at power-down T = 30°C, vdd = 1.3 V 1 mA Ivdd-up (1) (2) (3) (4) (5) (6) 150 (peak) The INL is measured at the output of the DAC (accessible at an external pin during bypass mode). The DNL is measured at the output of the DAC (accessible at an external pin during bypass mode). Assuming a capacitor of 0.1 µF at the tv_ref node. The analog supply current Ivdda is directly proportional to the full-scale output current IFS and is insensitive to fCLK The digital supply current IVDD is dependent on the digital input waveform, the DAC update rate fCLK, and the digital supply VDD. The peak digital supply current occurs at full-scale transition for duration less than 1 ns. VIDEO DAC SPECIFICATIONS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 (TMIN to TMAX, vdda_dac = 1.8 V, ROUT1/2 = 1650 Ω, RLOAD = 75 Ω, unless otherwise noted) Table 5-3. Video DAC – Dynamic Electrical Specification CONDITIONS/ASSUMPTIONS MIN TYP MAX Equal to input clock frequency Clock jitter rms clock jitter required in order to assure 10-bit accuracy Attenuation at 5.1 MHz Corner frequency for signal 0.1 Attenuation at 54 MHz (1) Image frequency 25 tST Output settling time Time from the start of the output transition to output within ± 1 LSB of final value. 85 ns tRout Output rise time Measured from 10% to 90% of full-scale transition 25 ns tFout Output fall time Measured from 10% to 90% of full-scale transition 25 ns BW Signal bandwidth 6 MHz Differential gain (2) Within bandwidth 40 ps 0.5 1.5 dB 30 33 dB fCLK = 54 MHz, fOUT = 1 MHz 1 deg. 45 dB (3) SNR Signal-to-noise ratio 1 kHz to 6 MHz bandwidth fCLK = 54 MHz, fOUT = 1 MHz 55 PSRR Power supply rejection ratio Up to 6 MHz 20 (4) Crosstalk Between the two video channels (1) (2) (3) (4) MHz 1.5% Differential phase (2) SFDR 54 UNIT Output update rate PRODUCT PREVIEW PARAMETER fCLK (1) –50 dB dB –40 dB For internal input clock information, For more information, see the DSS chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. The differential gain and phase value is for dc coupling. Note that there is degradation for the ac coupling. The SNR value is for dc coupling. Note that there is a 6-dB degradation for ac coupling. The PSSR value is for dc coupling. Note that there is a 10-dB degradation for ac coupling. Submit Documentation Feedback VIDEO DAC SPECIFICATIONS 151 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 5.3 Analog Supply (vdda_dac) Noise Requirements In order to assure 10-bit accuracy of the DAC analog output, the analog supply vdda_dac has to meet the noise requirements stated in this section. The DAC Power Supply Rejection Ratio is defined as the relative variation of the full-scale output current divided by the supply variation. Thus, it is expressed in percentage of Full-Scale Range (FSR) per volt of DI OUT I OUTFS VAC 100 × supply variation as shown in the following equation: PSRRDAC = % FSR V Depending on frequency, the PSRR is defined in Table 5-4. Table 5-4. Video DAC – Power Supply Rejection Ratio Supply Noise Frequency PSRR % FSR/V PRODUCT PREVIEW 0 to 100 kHz 1 > 100 kHz The rejection decreases 20 dB/dec. Example: at 1 MHz the PSRR is 10% of FSR/V A graphic representation is shown in Figure 5-2. PSRR (% FSR/V) First pole of DAC output load 10 1 f 100 kHz 1 MHz 030-019 Figure 5-2. Video DAC – Power Supply Rejection Ratio To ensure that the DAC SFDR specification is met, the PSRR values and the clock jitter requirements translate to the following limits on vdda_dac (for the Video DAC). The maximum peak-to-peak noise on vdda (ripple) is defined in Table 5-5: Table 5-5. Video DAC – Maximum Peak-to-Peak Noise on vdda_dac Tone Frequency Maximum Peak-to-Peak Noise on vdda_dac 0 to 100 kHz < 30 mVpp > 100 kHz Decreases 20 dB/dec. Example: at 1 MHz the maximum is 3 mVpp The maximum noise spectral density (white noise) is defined in Table 5-6: Table 5-6. Video DAC – Maximum Noise Spectral Density Supply Noise Bandwidth 152 Maximum Supply Noise Density 0 to 100 kHz < 20 µV / √Hz > 100 kHz Decreases 20 dB/dec. Example: at 1 MHz the maximum noise density is 2 µ / √Hz VIDEO DAC SPECIFICATIONS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Because the DAC PSRR deteriorates at a rate of 20 dB/dec after 100 kHz, it is highly recommended to have vdda_dac low pass filtered (proper decoupling) (see the illustrated application: Section 5.4, External Component Value Choice). 5.4 External Component Value Choice The full-scale output voltage VOUTMAX is regulated by the reference amplifier, and is set by an internal resistor RSET. IOUTMAX can be expressed as: IOUTMAX = IREF /8 * (63 + 15/16) Where: The output current IOUT appearing at DAC output is a function of both the input code and IOUTMAX and can be expressed as: IOUT = (DAC_CODE/1023) * IOUTMAX Where: DAC_CODE = 0 to 1023 is the DAC input code in decimal. The output voltage is: VOUT = IOUT *N* RCABLE Where: (N = amplifier gain = 21) RCABLE = 75 Ω (cable typical impedance) The TV-out buffer requires a per channel external resistors: ROUT1/2. The equation below can be used to select different resistor values (if necessary): ROUT = (N+1) RCABLE = 1650 Ω Recommended parameter values are: Table 5-7. Video DAC – Recommended External Components Values Recommended Value UNIT CBG 100 nF ROUT1/2 1650 Ω In order to limit the reference noise bandwidth and to suppress transients on VREF, it is necessary to connect a large decoupling capacitor BG) between the tv_vref and vssa_dac pins. Submit Documentation Feedback VIDEO DAC SPECIFICATIONS 153 PRODUCT PREVIEW VREF = 0.5V IREF = VREF/RSET OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 6 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 6.1 Timing Test Conditions All timing requirements and switching characteristics are valid over the recommended operating conditions of Table 3-3, unless otherwise specified. 6.2 Interface Clock Specifications 6.2.1 Interface Clock Terminology The Interface clock is used at the system level to sequence the data and/or control transfers accordingly with the interface protocol. 6.2.2 Interface Clock Frequency PRODUCT PREVIEW The two interface clock characteristics are: • The maximum clock frequency • The maximum operating frequency The interface clock frequency documented in this document is the maximum clock frequency, which corresponds to the maximum frequency programmable on this output clock. This frequency defines the maximum limit supported by the OMAP3515/03 IC and doesn’t take into account any system consideration (PCB, peripherals). The system designer will have to consider these system considerations and OMAP3515/03 IC timings characteristics as well, to define properly the maximum operating frequency, which corresponds to the maximum frequency supported to transfer the data on this interface. 6.2.3 Clock Jitter Specifications Jitter is a phase noise, which may alter different characteristics of a clock signal. The jitter specified in this document is the time difference between the typical cycle period and the actual cycle period affected by noise sources on the clock. The cycle (or period) jitter terminology identifies this type of jitter. Cycle (or Period) Jitter Tn-1 Tn Tn+1 Max. Cycle Jitter = Max (Ti) Min. Cycle Jitter = Min (Ti) Jitter Standard Deviation (or rms Jitter) = Standard Deviation (Ti) 030-020 Figure 6-1. Cycle (or Period) Jitter 6.2.4 Clock Duty Cycle Error The duty cycle error is the ratio between either the high-level pulse duration or the low-level pulse duration and the cycle time of a clock signal. 154 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 6.3 Timing Parameters The timing parameter symbols used in the timing requirement and switching characteristic tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies have been abbreviated as follows: Table 6-1. Timing Parameters Symbols Parameter c Cycle time (period) d Delay time dis Disable time en Enable time h Hold time su Setup time START Start bit t Transition time v Valid time Submit Documentation Feedback w Pulse duration (width) X Unknown, changing, or don’t care level H High L Low V Valid IV Invalid AE Active Edge FE First Edge LE Last Edge Z High impedance TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS PRODUCT PREVIEW LOWERCASE SUBSCRIPTS 155 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 6.4 External Memory Interfaces The OMAP3515/03 processor includes the following external memory interfaces: • General-purpose memory controller (GPMC) • SDRAM controller (SDRC) 6.4.1 General-Purpose Memory Controller (GPMC) The GPMC is the OMAP3515/03 unified memory controller used to interface external memory devices such as: • Asynchronous SRAM-like memories and ASIC devices • Asynchronous page mode and synchronous burst NOR flash • NAND flash PRODUCT PREVIEW 6.4.1.1 GPMC/NOR Flash Interface Synchronous Timing Table 6-3 and Table 6-4 assume testing over the recommended operating conditions (see Figure 6-2 through Figure 6-5) and electrical characteristic conditions. Table 6-2. GPMC/NOR Flash Synchronous Mode Timing Conditions TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 1.8 ns tF Input signal fall time 1.8 ns 15.94 pF Output Conditions CLOAD Output load capacitance Table 6-3. GPMC/NOR Flash Interface Timing Requirements – Synchronous Mode NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN 0.9 V MAX MIN UNIT MAX F12 tsu(DV-CLKH) Setup time, read gpmc_d[15:0] valid before gpmc_clk high 1.9 1.9 3.2 ns F13 th(CLKH-DV) Hold time, read gpmc_d[15:0] valid after gpmc_clk high 2.5 2.5 2.5 ns F21 tsu(WAITV-CLKH) Setup time, gpmc_waitx (1) valid before gpmc_clk high 1.9 1.9 3.2 ns F22 th(CLKH-WAITV) Hold Time, gpmc_waitx (1) valid after gpmc_clk high 2.5 2.5 2.5 ns (1) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see the OMAP35x Technical Reference Manual (literature number Table 6-4. GPMC/NOR Flash Interface Switching Characteristics – Synchronous Mode NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN 0.9 V MAX MIN UNIT MAX F0 tc(CLK) Cycle time(15), output clock gpmc_clk period 10 F1 tw(CLKH) Typical pulse duration, output clock gpmc_clk high 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) ns F1 tw(CLKL) Typical pulse duration, output clock gpmc_clk low 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) ns tdc(CLK) Duty cycle error, output clk gpmc_clk –500 500 –602 602 –1250 1250 ps 156 12.05 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 25 ns Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-4. GPMC/NOR Flash Interface Switching Characteristics – Synchronous Mode (continued) PARAMETER 1.15 V MIN 1.0 V MAX MIN 0.9 V MAX MIN UNIT MAX tj(CLK) Jitter standard deviation(16), output clock gpmc_clk 33.3 33.3 33.3 ps tR(CLK) Rise time, output clock gpmc_clk 1.6 2 2 ns tF(CLK) Fall time, output clock gpmc_clk 1.6 2 2 ns tR(DO) Rise time, output data 2 2 2 ns tF(DO) Fall time, output data 2 ns F2 td(CLKH-nCSV) Delay time, gpmc_clk rising edge to gpmc_ncsx(11) transition F(6) – 1.9 F(6) + 3.3 F(6) – 1.8 F(6) + 4.1 F(6) – 2.6 F(6) + 4.9 ns F3 td(CLKH-nCSIV) Delay time, gpmc_clk rising edge to gpmc_ncsx(11) invalid E(5) – 1.9 E(5) + 3.3 E(5) – 1.8 E(5) + 4.1 E(5) – 2.6 E(5) + 4.9 ns F4 td(ADDV-CLK) Delay time, address bus valid to gpmc_clk first edge B(2) – 4.1 B(2) + 2.1 B(2) – 4.1 B(2) + 2.1 B(2) – 4.9 B(2) + 2.6 ns F5 td(CLKH-ADDIV) Delay time, gpmc_clk rising edge to gpmc_a[16:1] invalid F6 td(nBEV-CLK) Delay time, gpmc_nbe0_cle, gpmc_nbe1 valid to gpmc_clk first edge B(2) – 1.1 B(2) + 2.1 B(2) – 0.9 B(2) + 1.9 B(2) – 2.6 B(2) + 2.6 ns F7 td(CLKH-nBEIV) Delay time, gpmc_clk rising edge to gpmc_nbe0_cle, gpmc_nbe1 invalid D(4) – 2.1 D(4) + 1.1 D(4) – 1.9 D(4) + 0.9 D(4) – 2.6 D(4) + 2.6 ns F8 td(CLKH-nADV) Delay time, gpmc_clk rising edge to gpmc_nadv_ale transition G(7) – 1.9 G(7) + 4.1 G(7) – 2.1 G(7) + 4.1 G(7) – 2.6 G(7) + 4.9 ns F9 td(CLKH-nADVIV) Delay time, gpmc_clk rising edge to gpmc_nadv_ale invalid D(4) – 1.9 D(4) + 4.1 D(4) – 2.1 D(4) + 4.1 D(4) – 2.6 D(4) + 4.9 ns F10 td(CLKH-nOE) Delay time, gpmc_clk rising edge to gpmc_noe transition H(8) – 2.1 H(8) + 2.1 H(8) – 2.1 H(8) + 2.1 H(8) – 2.6 H(8) + 4.9 ns F11 td(CLKH-nOEIV) Delay time, gpcm rising edge to gpmc_noe invalid E(5) – 2.1 E(5) + 2.1 E(5) – 2.1 E(5) + 2.1 E(5) – 2.6 E(5) + 4.9 ns F14 td(CLKH-nWE) Delay time, gpmc_clk rising edge to gpmc_nwe transition I(9) – 1.9 I(9) + 4.1 I(9) – 2.1 I(9) + 4.1 I(9) – 2.6 I(9) + 4.9 ns F15 td(CLKH-Data) Delay time, gpmc_clk rising edge to data bus transition J(10) – 2.1 J(10) + 1.1 J(10) – 1.9 J(10) + 0.9 J(10) – 2.6 J(10) + 2.6 ns F17 td(CLKH-nBE) Delay time, gpmc_clk rising edge to gpmc_nbex_cle transition J(10) – 2.1 J(10) + 1.1 J(10) – 1.9 J(10) + 0.9 J(10) – 2.6 J(10) + 2.6 ns F18 tW(nCSV) Pulse duration, gpmc_ncsx(11) low F19 F20 tW(nBEV) tW(nADVV) Submit Documentation Feedback –2.1 2 –2.1 –2.6 ns Read A(1) A(1) A(1) ns Write (1) (1) A(1) ns C(3) C(3) C(3) ns (3) (3) (3) ns (13) Pulse duration, Read gpmc_nbe0_cle, Write gpmc_nbe1 low Pulse duration, gpmc_nadv_ale low 2 A C (13) A C (13) PRODUCT PREVIEW NO. C Read K K K ns Write K(13) K(13) K(13) ns TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 157 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-4. GPMC/NOR Flash Interface Switching Characteristics – Synchronous Mode (continued) NO. PARAMETER 1.15 V 1.0 V 0.9 V UNIT MIN MAX MIN MAX MIN MAX H(8) – 2.1 H(8) + 4.1 H(8) – 2.1 H(8) + 4.1 H(8) – 2.6 F23 td(CLKH-IODIR) Delay time, gpmc_clk rising edge to gpmc_io_dir high (IN direction) H(8) + 4.9 ns F24 td(CLKH-IODIV) Delay time, gpmc_clk M(17) – 2.1 M(17) + 4.1 M(17) – 2.1 M(17) + 4.1 M(17) – 2.6 M(17) + 4.9 rising edge to gpmc_io_dir low (OUT direction) ns PRODUCT PREVIEW (1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period with n being the page burst access number. (2) B = ClkActivationTime * GPMC_FCLK (3) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: C = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write: C = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n being the page burst access number. (4) For single read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write: D = (WrCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK (5) For single read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write: E = (CSWrOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK (6) For nCS falling edge (CS activated): – Case GpmcFCLKDivider = 0: – F = 0.5 * CSExtraDelay * GPMC_FCLK – Case GpmcFCLKDivider = 1: – F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even) – F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise – Case GpmcFCLKDivider = 2: – F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime – ClkActivationTime) is a multiple of 3) – F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3) – F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3) (7) For ADV falling edge (ADV activated): – Case GpmcFCLKDivider = 0: – G = 0.5 * ADVExtraDelay * GPMC_FCLK – Case GpmcFCLKDivider = 1: – G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even) – G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise – Case GpmcFCLKDivider = 2: – G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVOnTime – ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3) – G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3) For ADV rising edge (ADV deactivated) in Reading mode: – Case GpmcFCLKDivider = 0: – G = 0.5 * ADVExtraDelay * GPMC_FCLK – Case GpmcFCLKDivider = 1: – G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even) – G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise – Case GpmcFCLKDivider = 2: – G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3) – G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3) For ADV rising edge (ADV deactivated) in Writing mode: – Case GpmcFCLKDivider = 0: – G = 0.5 * ADVExtraDelay * GPMC_FCLK – Case GpmcFCLKDivider = 1: – G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even) – G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise – Case GpmcFCLKDivider = 2: 158 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 For OE rising edge (OE deactivated): – GpmcFCLKDivider = 0: – H = 0.5 * OEExtraDelay * GPMC_FCLK – Case GpmcFCLKDivider = 1: – H = 0.5 * OEExtraDelay * GPMC_FC if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even) – H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise – Case GpmcFCLKDivider = 2: – H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 3) – H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3) – H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3) (9) For WE falling edge (WE activated): – Case GpmcFCLKDivider = 0: – I = 0.5 * WEExtraDelay * GPMC_FCLK – Case GpmcFCLKDivider = 1: – I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even) – I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise – Case GpmcFCLKDivider = 2: – I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime – ClkActivationTime) is a multiple of 3) – I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3) – I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3) For WE rising edge (WE deactivated): – Case GpmcFCLKDivider = 0: – I = 0.5 * WEExtraDelay * GPMC_FCLK – Case GpmcFCLKDivider = 1: – I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even) – I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise – Case GpmcFCLKDivider = 2: – I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime – ClkActivationTime) is a multiple of 3) – I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3) – I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3) (10) J = GPMC_FCLK period (11) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. (12) P = gpmc_clk period (13) For read: K = (ADVRdOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK For write: K = (ADVWrOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK (14) GPMC_FCLK is General-Purpose Memory Controller internal functional clock. (15) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the I/F module by setting the GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider. (16) The jitter probability density can be approximated by a Gaussian function. (17) M = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR behavior is automatically handled by GPMC controller. For a full description of the gpmc_io_dir feature, see the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 159 PRODUCT PREVIEW – G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3) – G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3) (8) For OE falling edge (OE activated) / IO DIR rising edge (Data Bus input direction): – Case GpmcFCLKDivider = 0: – H = 0.5 * OEExtraDelay * GPMC_FCLK – Case GpmcFCLKDivider = 1: – H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even) – H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise – Case GpmcFCLKDivider = 2: – H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime – ClkActivationTime) is a multiple of 3) – H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3) – H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3) OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com F1 F1 F0 gpmc_clk F2 F3 F18 gpmc_ncsx F4 gpmc_a[10:1] Valid Address F6 F7 F19 gpmc_nbe0_cle F19 PRODUCT PREVIEW gpmc_nbe1 F6 F8 F8 F20 F9 gpmc_nadv_ale F10 F11 gpmc_noe F13 F12 D0 gpmc_d[15:0] gpmc_waitx F23 gpmc_io_dir OUT F24 IN OUT 030-021 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. Figure 6-2. GPMC/NOR Flash – Synchronous Single Read – (GpmcFCLKDivider = 0) 160 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 F1 F1 F0 gpmc_clk F2 F3 gpmc_ncsx F4 Valid Address gpmc_a[10:1] F6 F7 gpmc_nbe0_cle F7 gpmc_nbe1 F6 F8 F8 F9 F10 PRODUCT PREVIEW gpmc_nadv_ale F11 gpmc_noe F13 F13 F12 D0 gpmc_d[15:0] F21 F12 D1 D2 D3 F22 gpmc_waitx F24 F23 gpmc_io_dir OUT IN OUT 030-022 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. Figure 6-3. GPMC/NOR Flash – Synchronous Burst Read – 4x16-bit (GpmcFCLKDivider = 0) Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 161 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com F1 F1 F0 gpmc_clk F2 F3 gpmc_ncsx F4 gpmc_a[10:1] Valid Address F17 F6 F17 F17 gpmc_nbe0_cle F17 F17 F17 PRODUCT PREVIEW gpmc_nbe1 F6 F8 F8 F9 gpmc_nadv_ale F14 F14 gpmc_nwe F15 gpmc_d[15:0] D0 D1 F15 D2 F15 D3 gpmc_waitx gpmc_io_dir OUT 030-023 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. Figure 6-4. GPMC/NOR Flash – Synchronous Burst Write – (GpmcFCLKDivider = 0) 162 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 F1 F0 F1 gpmc_clk F2 F3 gpmc_ncsx F6 F7 gpmc_nbe0_cle Valid F6 F7 gpmc_nbe1 Valid F4 gpmc_a[26:17] Address (MSB) F4 gpmc_a[16:1]_d[15:0] F13 F5 Address (LSB) F8 D0 D1 F12 D2 F8 D3 F9 gpmc_nadv_ale F10 F11 gpmc_noe gpmc_waitx F24 F23 gpmc_io_dir OUT IN OUT 030-024 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. Figure 6-5. GPMC/Multiplexed NOR Flash – Synchronous Burst Read Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 163 PRODUCT PREVIEW F12 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com F1 F1 F0 gpmc_clk F2 F3 gpmc_ncsx F4 Address (MSB) gpmc_a[26:17] F17 F6 F17 F17 gpmc_nbe0_cle F17 F17 F17 PRODUCT PREVIEW gpmc_nbe1 F6 F8 F8 F9 gpmc_nadv_ale F14 F14 gpmc_nwe F15 gpmc_d[15:0] Address (LSB) D0 D1 F15 F15 D2 D3 gpmc_waitx OUT gpmc_io_dir 030-025 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. Figure 6-6. GPMC/Multiplexed NOR Flash – Synchronous Burst Write 6.4.1.2 GPMC/NOR Flash Interface Asynchronous Timing Table 6-7 and Table 6-8 assume testing over the recommended operating conditions (see Figure 6-7 through Figure 6-12) and electrical characteristic conditions. Table 6-5. GPMC/NOR Flash Asynchronous Mode Timing Conditions TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 1.8 ns tF Input signal fall time 1.8 ns 15.94 pF Output Conditions CLOAD Output load capacitance Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters (1) (2) NO. PARAMETER 1.15 V MIN FI1 Maximum output data generation delay from internal functional clock FI2 Maximum input data capture delay by internal functional clock FI3 Maximum device select generation delay from internal functional clock (1) (2) 164 1.0 V MAX MIN 0.9 V MAX MIN UNIT MAX 6.5 9.1 13.7 ns 4 5.6 8.1 ns 6.5 9.1 13.7 ns The internal parameters table must be used to calculate Data Access Time stored in the corresponding CS register bit field. Internal parameters are referred to the GPMC functional internal clock which is not provided externally. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters (continued) PARAMETER 1.15 V MIN 1.0 V MAX MIN 0.9 V MAX MIN UNIT MAX FI4 Maximum address generation delay from internal functional clock 6.5 9.1 13.7 ns FI5 Maximum address valid generation delay from internal functional clock 6.5 9.1 13.7 ns FI6 Maximum byte enable generation delay from internal functional clock 6.5 9.1 13.7 ns FI7 Maximum output enable generation delay from internal functional clock 6.5 9.1 13.7 ns FI8 Maximum write enable generation delay from internal functional clock 6.5 9.1 13.7 ns FI9 Maximum functional clock skew 100 170 200 ps Table 6-7. GPMC/NOR Flash Interface Timing Requirements – Asynchronous Mode NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN 0.9 V MAX MIN UNIT MAX FA5 (1) tacc(DAT) Data maximum access time H (2) H (2) H (2) GPMC_FCLK cycles FA20 (3) tacc1-pgmode(DAT) Page mode successive data maximum access time P (4) P (4) P (4) GPMC_FCLK cycles FA21 (5) tacc2-pgmode(DAT) Page mode first data maximum access time H (2) H (2) H (2) GPMC_FCLK cycles (1) (2) (3) (4) (5) The FA5 parameter illustrates the amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data is internally sampled by active functional clock edge. FA5 value must be stored inside the AccessTime register bit field. H = AccessTime * (TimeParaGranularity + 1) The FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of GPMC functional clock cycles. After each access to input Page Data, next input Page Data is internally sampled by active functional clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field. P = PageBurstAccessTime * (TimeParaGranularity + 1) The FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data is internally sampled by active functional clock edge. FA21 value must be stored inside the AccessTime register bit field. Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode NO. PARAMETER 1.15 V MIN FA0 FA1 FA3 FA4 1.0 V MAX 0.9 V MIN MAX UNIT MIN MAX tR(DO) Rise time, output data 2.0 2.0 2.0 ns tF(DO) Fall time, output data 2.0 2.0 2.0 ns tW(nBEV) Pulse duration, Read gpmc_nbe0_cl Write e, gpmc_nbe1 valid time N(12) N(12) N(12) ns (12) (12) (12) ns Pulse duration, Read gpmc_ncsx(13) Write v low A(1) A(1) A(1) (1) (1) (1) tW(nCSV) td(nCSV-nADVIV) td(nCSV-nOEIV) Delay time, gpmc_ncsx(13) valid to gpmc_nadv_al e invalid Read Write Delay time, gpmc_ncsx(13) valid to gpmc_noe invalid (Single read) Submit Documentation Feedback N N A (2) B (2) B – 0.2 – 0.2 C(3) – 0.2 N A (2) B (2) B + 2.0 + 2.0 C(3) + 2.0 (2) B (2) B – 0.2 – 0.2 C(3) – 0.2 ns A (2) B (2) B + 2.6 + 2.6 C(3) + 2.6 (2) B (2) B – 0.2 – 0.2 C(3) – 0.2 ns (2) + 3.7 ns (2) + 3.7 ns C(3) + 3.7 ns B B TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 165 PRODUCT PREVIEW NO. OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode (continued) NO. PARAMETER 1.15 V 1.0 V 0.9 V UNIT MIN MAX MIN MAX MIN MAX PRODUCT PREVIEW FA9 td(AV-nCSV) Delay time, address bus valid to gpmc_ncsx(13) valid J(9) – 0.2 J(9) + 2.0 J(9) – 0.2 J(9) + 2.6 J(9) – 0.2 J(9) + 3.7 ns FA10 td(nBEV-nCSV) Delay time, gpmc_nbe0_cle, gpmc_nbe1 valid to gpmc_ncsx(13) valid J(9) – 0.2 J(9) + 2.0 J(9) – 0.2 J(9) + 2.6 J(9) – 0.2 J(9) + 3.7 ns FA12 td(nCSV-nADVV) Delay time, gpmc_ncsx(13) valid to gpmc_nadv_ale valid K(10) – 0.2 K(10) + 2.0 K(10) – 0.2 K(10) + 2.6 K(10) – 0.2 K(10) + 3.7 ns FA13 td(nCSV-nOEV) Delay time, gpmc_ncsx(13) valid to gpmc_noe valid L(11) – 0.2 L(11) + 2.0 L(11) – 0.2 L(11) + 2.6 L(11) – 0.2 L(11) + 3.7 ns FA14 td(nCSV-IODIR) Delay time, gpmc_ncsx(13) valid to gpmc_io_dir high L(11) – 0.2 L(11) + 2.0 L(11) – 0.2 L(11) + 2.6 L(11) – 0.2 L(11) + 3.7 ns FA15 td(nCSV-IODIR) Delay time, gpmc_ncsx(13) valid to gpmc_io_dir low M(14) – 0.2 M(14) + 2.0 M(14) – 0.2 M(14) + 2.6 M(14) – 0.2 M(14) + 3.7 ns FA16 tw(AIV) Address invalid duration between 2 successive R/W accesses FA18 td(nCSV-nOEIV) Delay time, gpmc_ncsx(13) valid to gpmc_noe invalid (Burst read) FA20 tw(AV) Pulse duration, address valid – 2nd, 3rd, and 4th accesses FA25 td(nCSV-nWEV) Delay time, gpmc_ncsx(13) valid to gpmc_nwe valid E(5) – 0.2 E(5) + 2.0 E(5) – 0.2 E(5) + 2.6 E(5) – 0.2 E(5) + 3.7 ns FA27 td(nCSV-nWEIV) Delay time, gpmc_ncsx(13) valid to gpmc_nwe invalid F(6) – 0.2 F(6) + 2.0 F(6) – 0.2 F(6) + 2.6 F(6) – 0.2 F(6) + 3.7 ns FA28 td(nWEV-DV) Delay time, gpmc_ new valid to data bus valid 3.7 ns FA29 td(DV-nCSV) Delay time, data bus valid to gpmc_ncsx(13) valid J(9) + 3.7 ns FA37 td(nOEV-AIV) Delay time, gpmc_noe valid to gpmc_a[16:1]_d[15:0] address phase end 3.7 ns G(7) I(8) – 0.2 G(7) I(8) + 2.0 I(8) – 0.2 D(4) I(8) + 2.6 I(8) – 0.2 D(4) 2.0 J(9) – 0.2 G(7) J(9) + 2.0 2.0 I(8) + 3.7 D(4) 2.6 J(9) – 0.2 ns J(9) + 2.6 2.6 J(9) – 0.2 ns ns (1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK For single write: A = (CSWrOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n being the page burst access number (2) For reading: B = ((ADVRdOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK For writing: B = ((ADVWrOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK (3) C = ((OEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK (4) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK (5) E = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK (6) F = ((WEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK (7) G = Cycle2CycleDelay * GPMC_FCLK (8) I = ((OEOffTime + (n – 1) * PageBurstAccessTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK 166 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 (9) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK (10) K = ((ADVOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK (11) L = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK (12) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: N = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write: N = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK (13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. (14) M = ((RdCycleTime - CSOnTime) * (TimeParaGranularity + 1) - 0.5 * CSExtraDelay) * GPMC_FCLK Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR behavior is automatically handled by GPMC controller. For a full description of the gpmc_io_dir feature, see the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. PRODUCT PREVIEW GPMC_FCLK gpmc_clk FA5 FA1 gpmc_ncsx FA9 Valid Address gpmc_a[10:1] FA0 FA10 gpmc_nbe0_cle Valid gpmc_nbe1 Valid FA0 FA10 FA3 FA12 gpmc_nadv_ale FA4 FA13 gpmc_noe gpmc_d[15:0] Data IN 0 Data IN 0 gpmc_waitx FA14 gpmc_io_dir OUT FA15 IN OUT 030-026 Figure 6-7. GPMC/NOR Flash – Asynchronous Read – Single Word Timing(1)(2)(3) (1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. (2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bit field. (3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 167 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com GPMC_FCLK gpmc_clk FA5 FA5 FA1 FA1 gpmc_ncsx FA16 FA9 FA9 gpmc_a[10:1] Address 0 Address 1 FA0 FA0 FA10 FA10 PRODUCT PREVIEW gpmc_nbe0_cle Valid FA0 FA0 gpmc_nbe1 Valid Valid Valid FA10 FA10 FA3 FA3 FA12 FA12 gpmc_nadv_ale FA4 FA4 FA13 FA13 gpmc_noe gpmc_d[15:0] Data Upper gpmc_waitx FA15 gpmc_io_dir FA14 OUT FA15 IN FA14 OUT IN 030-027 Figure 6-8. GPMC/NOR Flash – Asynchronous Read – 32-bit Timing (1)(2)(3) (1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. (2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bit field. (3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. 168 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 GPMC_FCLK gpmc_clk FA21 FA20 FA20 FA20 FA1 gpmc_ncsx FA9 Add0 gpmc_a[10:1] Add1 Add2 Add3 D0 D1 D2 Add4 FA0 FA10 gpmc_nbe0_cle gpmc_nbe1 FA12 gpmc_nadv_ale FA18 FA13 gpmc_noe gpmc_d[15:0] D3 D3 gpmc_waitx FA15 gpmc_io_dir OUT FA14 IN OUT 030-028 Figure 6-9. GPMC/NOR Flash – Asynchronous Read – Page Mode 4x16-bit Timing(1)(2)(3)(4) (1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. (2) FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by active functional clock edge. FA21 value must be stored inside AccessTime register bit field. (3) FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input page data). FA20 value must be stored in PageBurstAccessTime register bit field. (4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 169 PRODUCT PREVIEW FA0 FA10 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com gpmc_fclk gpmc_clk FA1 gpmc_ncsx FA9 Valid Address gpmc_a[10:1] FA0 FA10 gpmc_nbe0_cle FA0 FA10 PRODUCT PREVIEW gpmc_nbe1 FA3 FA12 gpmc_nadv_ale FA27 FA25 gpmc_nwe FA29 gpmc_d[15:0] Data OUT gpmc_waitx gpmc_io_dir OUT 030-029 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. Figure 6-10. GPMC/NOR Flash – Asynchronous Write – Single Word Timing 170 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 GPMC_FCLK gpmc_clk FA1 FA5 gpmc_ncsx FA9 gpmc_a[26:17] Address (MSB) FA0 FA10 gpmc_nbe0_cle Valid gpmc_nbe1 Valid FA3 FA12 gpmc_nadv_ale FA4 FA13 gpmc_noe FA29 gpmc_a[16:1]_d[15:0] FA37 Address (LSB) FA14 gpmc_io_dir OUT Data IN Data IN FA15 OUT IN gpmc_waitx 030-030 Figure 6-11. GPMC/Multiplexed NOR Flash – Asynchronous Read – Single Word Timing (1)(2)(3) (1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. (2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bit field. (3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 171 PRODUCT PREVIEW FA0 FA10 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com gpmc_fclk gpmc_clk FA1 gpmc_ncsx FA9 gpmc_a[26:17] Address (MSB) FA0 FA10 gpmc_nbe0_cle FA0 FA10 PRODUCT PREVIEW gpmc_nbe1 FA3 FA12 gpmc_nadv_ale FA27 FA25 gpmc_nwe FA29 gpmc_a[16:1]_d[15:0] FA28 Valid Address (LSB) Data OUT gpmc_waitx gpmc_io_dir OUT 030-031 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. Figure 6-12. GPMC/Multiplexed NOR Flash – Asynchronous Write – Single Word Timing 6.4.1.3 GPMC/NAND Flash Interface Timing Table 6-10 through Table 6-12 assume testing over the recommended operating conditions (see Figure 6-13 through Figure 6-16) and electrical characteristic conditions. Table 6-9. GPMC/NAND Flash Asynchronous Mode Timing Conditions TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 1.8 ns tF Input signal fall time 1.8 ns 15.94 pF Output Conditions CLOAD Output load capacitance Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing – Internal Parameters (1) (2) NO. PARAMETER 1.15 V MIN GNFI1 Maximum output data generation delay from internal functional clock GNFI2 Maximum input data capture delay by internal functional clock (1) (2) 172 1.0 V MAX MIN 0.9 V MAX MIN UNIT MAX 6.5 9.1 13.7 ns 4 5.6 8.1 ns Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field. Internal parameters are referred to the GPMC functional internal clock which is not provided externally. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing – Internal Parameters (continued) PARAMETER 1.15 V MIN 1.0 V MAX MIN 0.9 V MAX MIN UNIT MAX GNFI3 Maximum device select generation delay from internal functional clock 6.5 9.1 13.7 ns GNFI4 Maximum address latch enable generation delay from internal functional clock 6.5 9.1 13.7 ns GNFI5 Maximum command latch enable generation delay from internal functional clock 6.5 9.1 13.7 ns GNFI6 Maximum output enable generation delay from internal functional clock 6.5 9.1 13.7 ns GNFI7 Maximum write enable generation delay from internal functional clock 6.5 9.1 13.7 ns GNFI8 Maximum functional clock skew 100 170 200 ps Table 6-11. GPMC/NAND Flash Interface Timing Requirements NO. PARAMETER 1.15 V MIN GNF12 (1) tacc(DAT) (1) (2) 1.0 V MAX MIN J (2) Data maximum access time 0.9 V MAX MIN UNIT MAX J (2) J (2) GPMC_FCLK cycles The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field. J = AccessTime * (TimeParaGranularity + 1) Table 6-12. GPMC/NAND Flash Interface Switching Characteristics NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN 0.9 V MAX MIN UNIT MAX tR(DO) Rise time, output data 2.0 2.0 2.0 ns tF(DO) Fall time, output data 2.0 2.0 2.0 ns GNF0 tw(nWEV) Pulse duration, gpmc_nwe valid time GNF1 td(nCSV-nWEV) Delay time, gpmc_ncsx(13) valid to gpmc_nwe valid B(2) – 0.2 B(2) + 2.0 B(2) – 0.2 B(2) + 2.6 B(2) – 0.2 B(2) + 3.7 ns GNF2 tw(CLEH-nWEV) Delay time, gpmc_nbe0_cle high to gpmc_nwe valid C(3) – 0.2 C(3) + 2.0 C(3) – 0.2 C(3) + 2.6 C(3) – 0.2 C(3) + 3.7 ns GNF3 tw(nWEV-DV) Delay time, gpmc_d[15:0] valid to gpmc_nwe valid D(4) – 0.2 D(4) + 2.0 D(4) – 0.2 D(4) + 2.6 D(4) – 0.2 D(4) + 3.7 ns GNF4 tw(nWEIV-DIV) Delay time, gpmc_nwe invalid to gpmc_d[15:0] invalid E(5) – 0.2 E(5) + 2.0 E(5) – 0.2 E(5) + 2.6 E(5) – 0.2 E(5) + 3.7 ns GNF5 tw(nWEIV-CLEIV) Delay time, gpmc_nwe invalid to gpmc_nbe0_cle invalid F(6) – 0.2 F(6) + 2.0 F(6) – 0.2 F(6) + 2.6 F(6) – 0.2 F(6) + 3.7 ns Submit Documentation Feedback A(1) A(1) A(1) ns TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 173 PRODUCT PREVIEW NO. OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-12. GPMC/NAND Flash Interface Switching Characteristics (continued) NO. PARAMETER 1.15 V 1.0 V 0.9 V UNIT MIN MAX MIN MAX MIN MAX PRODUCT PREVIEW GNF6 tw(nWEIV-nCSIV) Delay time, gpmc_nwe invalid to gpmc_ncsx(13) invalid G(7) – 0.2 G(7) + 2.0 G(7) – 0.2 G(7) + 2.6 G(7) – 0.2 G(7) + 3.7 ns GNF7 tw(ALEH-nWEV) Delay time, gpmc_nadv_ale High to gpmc_nwe valid C(3) – 0.2 C(3) + 2.0 C(3) – 0.2 C(3) + 2.6 C(3) – 0.2 C(3) + 3.7 ns GNF8 tw(nWEIV-ALEIV) Delay time, gpmc_nwe invalid to gpmc_nadv_ale invalid F(6) – 0.2 F(6) + 2.0 F(6) – 0.2 F(6) + 2.6 F(6) – 0.2 F(6) + 3.7 ns GNF9 tc(nWE) Cycle time, Write cycle time GNF10 td(nCSV-nOEV) Delay time, gpmc_ncsx(13) valid to gpmc_noe valid GNF13 tw(nOEV) Pulse duration, gpmc_noe valid time K(10) K(10) K(10) ns GNF14 tc(nOE) Cycle time, Read cycle time L(11) L(11) L(11) ns GNF15 tw(nOEIV-nCSIV) Delay time, gpmc_noe invalid to gpmc_ncsx(13) invalid H(8) I(9) – 0.2 H(8) I(9) + 2.0 M(12) – 0.2 M(12) + 2.0 I(9) – 0.2 H(8) I(9) + 2.6 M(12) – 0.2 M(12) + 2.6 I(9) – 0.2 ns I(9) + 3.7 M(12) – 0.2 M(12) + 3.7 ns ns (1) A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK (2) B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK (3) C = ((WEOnTime – ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK (4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK (5) E = (WrCycleTime – WEOffTime * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay ) * GPMC_FCLK (6) F = (ADVWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay ) * GPMC_FCLK (7) G = (CSWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay ) * GPMC_FCLK (8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK (9) I = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK (10) K = (OEOffTime – OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK (11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK (12) M = (CSRdOffTime – OEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay ) * GPMC_FCLK (13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. 174 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 GPMC_FCLK GNF1 GNF6 GNF2 GNF5 gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe GNF0 gpmc_nwe GNF3 GNF4 PRODUCT PREVIEW Command gpmc_a[16:1]_d[15:0] 030-032 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. Figure 6-13. GPMC/NAND Flash – Command Latch Cycle Timing GPMC_FCLK GNF1 GNF6 GNF7 GNF8 gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe GNF9 GNF0 gpmc_nwe GNF3 gpmc_a[16:1]_d[15:0] GNF4 Address 030-033 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. Figure 6-14. GPMC/NAND Flash – Address Latch Cycle Timing Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 175 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com GPMC_FCLK GNF12 GNF10 GNF15 gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale GNF14 GNF13 PRODUCT PREVIEW gpmc_noe gpmc_a[16:1]_d[15:0] DATA gpmc_waitx 030-034 Figure 6-15. GPMC/NAND Flash – Data Read Cycle Timing (1)(2)(3) (1) The GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data is internally sampled by active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field. (2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. (3) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 ,1, 2, or 3. GPMC_FCLK GNF1 GNF6 gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe GNF9 GNF0 gpmc_nwe GNF3 gpmc_a[16:1]_d[15:0] GNF4 DATA 030-035 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 or 1. Figure 6-16. GPMC/NAND Flash – Data Write Cycle Timing 176 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com 6.4.2 SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 SDRAM Controller Subsystem (SDRC) The SDRAM controller subsystem (SDRC) module provides connectivity between the OMAP3530/2530/2530/2530/25 Applications Processor and external DRAM memory components. The SDRC module only supports low-power double-data-rate (LPDDR) SDRAM devices. Memory devices can be interfaced to the SDRC using a stacked-memory approach or through the printed circuit board (PCB). The stacked-memory approach uses the package-on-package memory interface pins (available only on CBB package). 6.4.2.1 SDRAM Controller Subsystem Device-Specific Information For the SDRC memory bus, the approach is to specify compatible memory devices and provide the printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI) has performed the simulation and system characterization to ensure all interface timings in this solution are met. 6.4.2.2 LPDDR Interface The LPDDR interface is balled out on the bottom side of all OMAP35x packages and on the top side of OMAP35x POP packages. The LPDDR interface on the top of the POP package has been designed for compatibility any POP LPDDR device with a matching footprint and compliance with the JEDEC LPDDR-266 specification. This section provides the timing specification for the bottom-side LPDDR interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable LPDDR memory system without the need for a complex timing closure process. For more information regarding guidelines for using this LPDDR specification, see the Understanding TI's PCB Routing Rule-Based DDR Timing Specification Application Report (literature number SPRAAV0). 6.4.2.2.1 LPDDR Interface Schematic Figure 6-17 and Figure 6-18 show the LPDDR interface schematics for a LPDDR memory system. The 1 x16 LPDDR system schematic is identical to Figure 6-17 except that the high word LPDDR device is deleted. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 177 PRODUCT PREVIEW The approach to specifying interface timing for the SDRC memory bus is different than on other interfaces such as the general-purpose memory controller (GPMC) and the multi-channel buffered serial ports (McBSPs). For these other interfaces the device timing was specified in terms of data manual specifications and I/O buffer information specification (IBIS) models. OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com LPDDR OMAP35x sdrc_d0 T DQ0 sdrc_d7 sdrc_dm0 sdrc_dqs0 sdrc_d8 T DQ7 LDM LDQS DQ8 sdrc_d15 sdrc_dm1 sdrc_dqs1 T T T T T T LPDDR PRODUCT PREVIEW sdrc_d16 T DQ0 sdrc_d23 sdrc_dm2 sdrc_dqs2 sdrc_d24 T DQ7 LDM LDQS DQ8 sdrc_d31 sdrc_dm3 sdrc_dqs3 sdrc_ba0 sdrc_ba1 sdrc_a0 T sdrc_a14 sdrc_ncs0 sdrc_ncs1 sdrc_ncas sdrc_nras sdrc_nwe sdrc_cke0 sdrc_cke1 sdrc_clk sdrc_nclk T T T T T T T T T T DQ15 UDM UDQS DQ15 UDM UDQS BA0 BA1 A0 BA0 BA1 A0 A14 CS A14 CS CAS RAS WE CKE CAS RAS WE CKE CK CK CK CK N/C T T T T N/C T T Figure 6-17. OMAP35x LPDDR High Level Schematic (x16 memories) 178 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 LPDDR sdrc_d0 T DQ0 sdrc_d7 sdrc_dm0 sdrc_dqs0 sdrc_d8 T DQ7 DM0 DQS0 DQ8 sdrc_d15 sdrc_dm1 sdrc_dqs1 T T DQ15 DM1 DQS1 sdrc_d16 T DQ16 sdrc_d23 sdrc_dm2 sdrc_dqs2 sdrc_d24 T DQ23 DM2 DQS2 DQ24 sdrc_d31 sdrc_dm3 sdrc_dqs3 sdrc_ba0 sdrc_ba1 sdrc_a0 T sdrc_a14 sdrc_ncs0 sdrc_ncs1 sdrc_ncas sdrc_nras sdrc_nwe sdrc_cke0 sdrc_cke1 sdrc_clk sdrc_nclk T T T T T T T T T T T T T PRODUCT PREVIEW OMAP35x DQ31 DM3 DQS3 BA0 BA1 A0 A14 CS T N/C T CAS RAS WE CKE T T T N/C T CK CK T Figure 6-18. OMAP35x LPDDR High Level Schematic (x32 memory) 6.4.2.2.2 Compatible JEDEC LPDDR Devices Table 6-13 shows the parameters of the JEDEC LPDDR devices that are compatible with this interface. Generally, the LPDDR interface is compatible with x16 and x32 LPDDR266 and LPDDR333 speed grade LPDDR devices. Table 6-13. Compatible JEDEC LPDDR Devices (1) (2) NO. PARAMETER MIN 1 JEDEC LPDDR Device Speed Grade MAX UNIT LPDDR-266 2 JEDEC LPDDR Device Bit Width 16 32 Bits 3 JEDEC LPDDR Device Count 1 2 Devices 4 JEDEC LPDDR Device Ball Count 60 90 Balls NOTES See Note (1) See Note (2) Higher LPDDR speed grades are supported due to inherent JEDEC LPDDR backwards compatibility. 1 x16 LPDDR device is used for 16 bit LPDDR memory system. 1x32 or 2x16 LPDDR devices are used for a 32-bit LPDDR memory system. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 179 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 6.4.2.2.3 PCB Stackup The minimum stackup required for routing the OMAP35x is a six layer stack as shown in Table 6-14. Additional layers may be added to the PCB stack up to accommodate other circuity or to reduce the size of the PCB footprint. Table 6-14. OMAP35x Minimum PCB Stack Up PRODUCT PREVIEW LAYER TYPE DESCRIPTION 1 Signal Top Routing Mostly Horizontal 2 Plane Ground 3 Plane Power 4 Signal Internal Routing 5 Plane Ground 6 Signal Bottom Routing Mostly Vertical Table 6-15. PCB Stack Up Specifications NO. PARAMETER MIN 1 PCB Routing/Plane Layers 6 2 Signal Routing Layers 3 3 Full ground layers under LPDDR routing region 2 4 Number of ground plane cuts allowed within LPDDR routing region 5 Number of ground reference planes required for each LPDDR routing 1 layer 6 Number of layers between LPDDR routing layer and reference ground 0 plane 7 PCB Routing Feature Size 4 Mils 8 PCB Trace Width w 4 Mils 9 PCB BGA escape via pad size 18 Mils 10 PCB BGA escape via hole size 8 Mils 11 Device BGA Pad Size See Note (1) 12 LPDDR Device BGA Pad Size See Note (2) 13 Single Ended Impedance, ZO 50 14 Impedance Control Z-5 (1) (2) (3) TYP MAX UNIT NOTES 0 1 0 Z 75 Ω Z+5 Ω See Note (3) Please see the Flip Chip Ball Grid Array Package Reference Guide (literature number SPRU811) for device BGA pad size. Please see the LPDDR device manufacturer documentation for the LPDDR device BGA pad size. Z is the nominal singled ended impedance selected for the PCB specified by item 12. 6.4.2.3 Placement Figure 6-19 shows the required placement for the OMAP35x device as well as the LPDDR devices. The dimensions for Figure 6-19 are defined in Table 6-16. The placement does not restrict the side of the PCB that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For 1x16 and 1x32 LPDDR memory systems, the second LPDDR device is omitted from the placement. 180 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 X Y OFFSET LPDDR Device Y Y OFFSET LPDDR Controller A1 OMAP A1 Figure 6-19. OMAP35x and LPDDR Device Placement Table 6-16. Placement Specifications NO. 1 (1) (2) (3) (4) (5) PARAMETER MIN X MAX UNIT 1440 Mils 2 Y 1030 Mils 3 Y Offset 525 Mils 4 LPDDR Keepout Region 5 Clearance from non-LPDDR signal to LPDDR Keepout Region NOTES See Notes (1), See Notes (2) (1) (2) , See Notes (1), (2), (3) See Note (4) 4 w See Note (5) See Figure 6-17 for dimension definitions. Measurements from center of device to center of LPDDR device. For 16 bit memory systems it is recommended that Y Offset be as small as possible. LPDDR keepout region to encompass entire LPDDR routing area. Non-LPDDR signals allowed within LPDDR keepout region provided they are separated from LPDDR routing layers by a ground plane. 6.4.2.4 LPDDR Keep Out Region The region of the PCB used for the LPDDR circuitry must be isolated from other signals. The LPDDR keep out region is defined for this purpose and is shown in Figure 6-20. The size of this region varies with the placement and LPDDR routing. Additional clearances required for the keep out region are shown in Table 6-16. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 181 PRODUCT PREVIEW Recommended LPDDR Device Orientation OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com LPDDR Controller A1 LPDDR Device A1 PRODUCT PREVIEW Region should encompass all LPDDR circuitry and varies depending on placement. Non-LPDDR signals should not be routed on the LPDDR signal layers within the LPDDR keep out region. Non-LPDDR signals may be routed in the region provided they are routed on layers separated from LPDDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this region. In addition, the 1.8 V power plane should cover the entire keep out region. Figure 6-20. LPDDR Keepout Region 6.4.2.5 Net Classes Table 6-17 lists the clock net classes for the LPDDR interface. Table 6-18 lists the signal net classes, and associated clock net classes, for the signals in the LPDDR interface. These net classes are used for the termination and routing rules that follow. Table 6-17. Clock Net Class Definitions CLOCK NET CLASS OMAP PIN NAMES CK sdrc_clk/sdrc_nclk DQS0 sdrc_dqs0 DQS1 sdrc_dqs1 DQS2 sdrc_dqs2 DQS3 sdrc_dqs3 Table 6-18. Signal Net Class Definitions CLOCK NET CLASS ASSOCIATED CLOCK NET CLASS OMAP PIN NAMES ADDR_CTRL CK sdrc_ba, sdrc_a, sdrc_ncs0, sdrc_ncas, sdrc_nras, sdrc_nwe, sdrc_cke0 DQ0 DQS0 sdrc_d, sdrc_dm0 DQ1 DQS1 sdrc_d, sdrc_dm1 DQ2 DQS2 sdrc_d, sdrc_dm2 DQ3 DQS3 sdrc_d, sdrc_dm3 6.4.2.6 LPDDR Signal Termination No terminations of any kind are required in order to meet signal integrity and overshoot requirements. Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only type permitted. Table 6-19 shows the specifications for the series terminators. Table 6-19. LPDDR Signal Terminations NO. PARAMETER MIN 1 CK Net Class 0 TYP (1) Only series termination is permitted, parallel or SST specifically disallowed. 182 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS MAX UNIT NOTES 10 Ω See Note (1) Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-19. LPDDR Signal Terminations (continued) NO. PARAMETER MIN TYP MAX UNIT NOTES 2 ADDR_CTRL Net Class 0 22 Zo Ω See Notes (1), (2), (3) 3 Data Byte Net Classes (DQS0-DQS3, DQ0-DQ3) 0 22 Zo Ω See Notes (1), (2), (3) (2) (3) Terminator values larger than typical only recommended to address EMI issues. Termination value should be uniform across net class. 6.4.2.7 LPDDR CK and ADDR_CTRL Routing Figure 6-21 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized. C PRODUCT PREVIEW T A LPDDR Controller B A1 OMAP A1 Figure 6-21. CK and ADDR_CTRL Routing and Topology Table 6-20. CK and ADDR_CTRL Routing Specification NO. PARAMETER 1 Center to Center CK-CK spacing 2w 2 CK A to B/A to C Skew Length Mismatch 3 CK B to C Skew Length Mismatch 4 Center to Center CK to other LPDDR trace spacing 4w 5 CK/ADDR_CTRL nominal trace length CACLM-50 6 (1) (2) (3) MIN TYP MAX UNIT NOTES 25 Mils See Note (1) 25 Mils See Note (2) CACLM See Note (3) CACLM+50 Mils ADDR_CTRL to CK Skew Length Mismatch 100 Mils 7 ADDR_CTRL to ADDR_CTRL Skew Length Mismatch 100 Mils 8 Center to Center ADDR_CTRL to other LPDDR trace 4w spacing 4w See Note (2) 9 Center to Center ADDR_CTRL to other ADDR_CTRL 3w trace spacing 3w See Note (2) 10 ADDR_CTRL A to B/A to C Skew Length Mismatch 100 Mils 11 ADDR_CTRL B to C Skew Length Mismatch 100 Mils See Note (1) Series terminator, if used, should be located closest to device. Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 183 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Figure 6-22 shows the topology and routing for the DQS and DQ net classes; the routes are point to point. Skew matching across bytes is not needed nor recommended. T E0 T E1 LPDDR Controller A1 OMAP T PRODUCT PREVIEW A1 E2 T E3 Figure 6-22. DQS and DQ Routing and Topology Table 6-21. DQS and DQ Routing Specification (1) NO. PARAMETER 2 DQS E Skew Length Mismatch 3 Center to Center DQS to other LPDDR trace spacing 4w 4 DQS/DQ nominal trace length DQLM - 50 5 6 7 Center to Center DQ to other LPDDR trace spacing 4w See Note (2) 8 Center to Center DQ to other DQ trace spacing 3w See Note (2), (4) 9 DQ E Skew Length Mismatch (1) (2) (3) (4) 184 MIN TYP MAX UNIT 25 Mils NOTES See Note (2) DQLM DQLM + 50 Mils DQ to DQS Skew Length Mismatch 100 Mils DQ to DQ Skew Length Mismatch 100 Mils 100 See Note (3) Mils Series terminator, if used, should be located closest to LPDDR. Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. DQLM is the longest Manhattan distance of the DQS and DQ net classes. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 6.5 Video Interfaces 6.5.1 Camera Interface The camera subsystem provides the system interfaces and the processing capability to connect raw, YUV, or JPEG image sensor modules to the OMAP3515/03 device for video-preview, video-record, and still-image-capture applications. The camera subsystem supports up to two simultaneous pixel flows but only one of them can use the video processing hardware: • PARALLEL: the parallel interface data must go through the video processing hardware. The parallel camera interface is a 12-bit interface which can be used in two modes: 1. SYNC mode: progressive and interlaced image sensor modules for 8-, 10-, 11-, and 12-bit data. The pixel clock can be up to 75 MHz in 12-bit mode. The pixel clock can be up to 130 MHz in 8-bit packed mode. 2. ITU mode provides an ITU-R BT 656 compatible data stream with progressive image sensor modules only in 8- and 10-bit configurations. The pixel clock can be up to 75 MHz. 6.5.1.1.1 SYNC Normal Mode 6.5.1.1.1.1 12-Bit SYNC Normal – Progressive Mode Table 6-23 and Table 6-24 assume testing over the recommended operating conditions and electrical characteristic conditions (see Figure 6-23). Table 6-22. ISP Timing Conditions – 12-Bit SYNC Normal – Progressive Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2.7 ns tF Input signal fall time 2.7 ns Output load capacitance 8.6 pF Output Condition CLOAD Table 6-23. ISP Timing Requirements – 12-Bit SYNC Normal – Progressive Mode (1) NO. PARAMETER 1.15 V MIN ISP17 tc(pclk) Cycle time (2), cam_pclk period 1.0 V MAX 13.3 MIN 22.2 (3) ISP18 tW(pclkH) Typical pulse duration, cam_pclk high 0.5*P ISP18 tW(pclkL) Typical pulse duration, cam_pclk low 0.5*P (3) tdc(pclk) Duty cycle error, cam_pclk ns 0.5*P (3) ns 0.5*P 133 1111 ps 200 ps tj(pclk) Cycle jitter ISP19 tsu(dV-pclkH) Setup time, cam_d[11:0] valid before cam_pclk rising edge 1.82 3.25 ns ISP20 th(pclkH-dV) Hold time, cam_d[11:0] valid after cam_pclk rising edge 1.82 3.25 ns ISP21 tsu(dV-vsH) Setup time, cam_vs valid before cam_pclk rising edge 1.82 3.25 ns ISP22 th(pclkH-vsV) Hold time, cam_vs valid after cam_pclk rising edge 1.82 3.25 ns ISP23 tsu(dV-hsH) Setup time, cam_hs valid before cam_pclk rising edge 1.82 3.25 ns (1) (2) (3) (4) , cam_pclk ns (3) 667 (4) UNIT MAX The timing requirements are assured for the cycle jitter and duty cycle error conditions specified. Related with the input maximum frequency supported by the ISP module. P = cam_pclk period in ns Maximum cycle jitter supported by cam_pclk input clock. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 185 PRODUCT PREVIEW 6.5.1.1 Parallel Camera Interface Timing OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-23. ISP Timing Requirements – 12-Bit SYNC Normal – Progressive Mode (continued) NO. PARAMETER 1.15 V MIN MAX 1.0 V MIN UNIT MAX ISP24 th(pclkH-hsV) Hold time, cam_hs valid after cam_pclk rising edge 1.82 3.25 ns ISP25 tsu(dV-hsH) Setup time, cam_wen valid before cam_pclk rising edge 1.82 3.25 ns ISP26 th(pclkH-hsV) Hold time, cam_wen valid after cam_pclk rising edge 1.82 3.25 ns Table 6-24. ISP Switching Characteristics – 12-Bit SYNC Normal – Progressive Mode NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX PRODUCT PREVIEW ISP15 tc(xclk) Cycle time (1), cam_xclk period ISP16 tW(xclkH) Typical pulse duration, cam_xclk high 0.5*PO (2) 0.5*PO (2) ns ISP16 tW(xclkL) Typical pulse duration, cam_xclk low 0.5*PO (2) 0.5*PO (2) ns tdc(xclk) Duty cycle error, cam_xclk 231 231 ps tj(xclk) Jitter standard deviation (3), cam_xclk 33 33 ps tR(xclk) Rise time, cam_xclk 0.93 0.93 ns tF(xclk) Fall time, cam_xclk 0.93 0.93 ns (1) (2) (3) 186 4.6 4.6 ns Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module. Warning: The camera sensor or the camera module must be disabled to change the frequency configuration. For more information, see the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98] PO = cam_xclk period in ns The jitter probability density can be approximated by a Gaussian function. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 ISP16 ISP15 ISP16 cam_xclki ISP17 ISP18 ISP18 cam_pclk ISP19 ISP20 ISP21 ISP22 PRODUCT PREVIEW cam_vs cam_hs ISP23 cam_d[11:0] D(0) D(n-3) D(n-2) ISP24 D(n-1) D(0) D(1) D(n-1) ISP25 ISP26 cam_wen cam_fld 030-056 (1)(2)(3)(4)(5)(6)(7)(8) Figure 6-23. ISP – 12-Bit SYNC Normal – Progressive Mode (1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output, the signal length can be set. (2) The parallel camera in SYNC mode supports progressive image sensor modules and 8-, 10-, 11-, or 12-bit data. (3) When the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be grounded. (4) However, it is possible to shift the data to 0, 2, or 4 data internal lanes. (5) The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit mode, and cam_d[11:0] in 12-bit mode. (6) Optionally, the data write to memory can be qualified by the external cam_wen signal. (7) The cam_wen signal can be used as a external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. (8) In cam_xclki; I is equal to a or b. 6.5.1.1.1.2 8-bit Packed SYNC – Progressive Mode Table 6-26 and Table 6-27 assume testing over the recommended operating conditions and electrical characteristic conditions (see Figure 6-24). Table 6-25. ISP Timing Conditions – 8-bit Packed SYNC – Progressive Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2.5 ns tF Input signal fall time 2.5 ns Output Conditions Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 187 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-25. ISP Timing Conditions – 8-bit Packed SYNC – Progressive Mode (continued) TIMING CONDITION PARAMETER CLOAD VALUE UNIT 8.6 pF Output load capacitance Table 6-26. ISP Timing Requirements – 8-bit Packed SYNC – Progressive Mode (1) NO. PARAMETER 1.15 V MIN ISP3 tc(pclk) Cycle time (2), cam_pclk period 1.0 V MAX MIN 7.7 UNIT MAX 15.4 (3) ISP4 tW(pclkH) Typical pulse duration, cam_pclk high 0.5*P ISP4 tW(pclkL) Typical pulse duration, cam_pclk low 0.5*P (3) tdc(pclk) Duty cycle error, cam_pclk ns (3) ns 0.5*P (3) ns 0.5*P 385 (4) 83 ps 167 ps PRODUCT PREVIEW tj(pclk) Cycle jitter ISP5 tsu(dV-pclkH) Setup time, cam_d[11:0] valid before cam_pclk rising edge 1.08 2.27 ns ISP6 th(pclkH-dV) Hold time, cam_d[11:0] valid after cam_pclk rising edge 1.08 2.27 ns ISP7 tsu(dV-vsH) Setup time, cam_vs valid before cam_pclk rising edge 1.08 2.27 ns ISP8 th(pclkH-vsV) Hold time, cam_vs valid after cam_pclk rising edge 1.08 2.27 ns ISP9 tsu(dV-hsH) Setup time, cam_hs valid before cam_pclk rising edge 1.08 2.27 ns ISP10 th(pclkH-hsV) Hold time, cam_hs valid after cam_pclk rising edge 1.08 2.27 ns ISP11 tsu(dV-hsH) Setup time, cam_wen valid before cam_pclk rising edge 1.08 2.27 ns ISP12 th(pclkH-hsV) Hold time, cam_wen valid after cam_pclk rising edge 1.08 2.27 ns (1) (2) (3) (4) , cam_pclk 769 The timing requirements are assured for the cycle jitter and duty cycle error conditions specified. Related with the input maximum frequency supported by the ISP module. P = cam_pclk period in ns. Maximum cycle jitter supported by cam_pclk input clock. Table 6-27. ISP Switching Characteristics – 8-bit packed SYNC – Progressive Mode NO. PARAMETER 1.15 V MIN ISP1 tc(xclk) Cycle time (1), cam_xclk period 1.0 V MAX 4.6 MIN UNIT MAX 4.6 (2) ns ISP2 tW(xclkH) Typical pulse duration, cam_xclk high 0.5*PO ISP2 tW(xclkL) Typical pulse duration, cam_xclk low 0.5*PO (2) tdc(xclk) Duty cycle error, cam_xclk 231 231 ps tj(xclk) Jitter standard deviation (3), cam_xclk 67 67 ps tR(xclk) Rise time, cam_xclk 0.93 0.93 ns tF(xclk) Fall time, cam_xclk 0.93 0.93 ns (1) (2) (3) 188 0.5*PO (2) ns 0.5*PO (2) ns Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module. Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98 PO = cam_xclk period in ns The jitter probability density can be approximated by a Gaussian function. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 ISP1 ISP2 ISP2 cam_xclki ISP4 ISP3 ISP4 ISP5 ISP6 ISP7 ISP8 PRODUCT PREVIEW cam_pclk cam_vs cam_hs ISP9 cam_d[7:0] D(0) D(n-3) D(n-2) ISP10 D(n-1) D(0) D(1) D(n-1) ISP12 ISP11 cam_wen cam_fld 030-059 (1)(2)(3)(4)(5) Figure 6-24. ISP – 8-bit Packed SYNC – Progressive Mode (1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. (2) The image sensor must be connected to the lower data lines and the unused lines must be grounded. However, it is possible to shift the data to 0, 2, or 4 data internal lanes. The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode. (3) Optionally, the data write to memory can be qualified by the external cam_wen signal. The cam_wen signal can be used as a external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. The polarity of cam_fld is programmable. (4) The camera module can pack 8-bit data into 16 bits. It doubles the maximum pixel clock. This mode can be particularly useful to transfer a YCbCr data stream or compressed stream to memory at very high speed. (5) In cam_xclki; I is equal to a or b. 6.5.1.1.1.3 12-Bit SYNC Normal – Interlaced Mode Table 6-29 and Table 6-30 assume testing over the recommended operating conditions and electrical characteristic conditions (see Figure 6-25). Table 6-28. ISP Timing Conditions – 12-Bit SYNC Normal – Interlaced Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2.7 ns tF Input signal fall time 2.7 ns Output Conditions Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 189 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-28. ISP Timing Conditions – 12-Bit SYNC Normal – Interlaced Mode (continued) TIMING CONDITION PARAMETER CLOAD VALUE UNIT 8.6 pF Output load capacitance Table 6-29. ISP Timing Requirements – 12-Bit SYNC Normal – Interlaced Mode (1) NO. PARAMETER 1.15 V 1.0 V MIN ISP17 tc(pclk) Cycle time (2), cam_pclk period MAX 13.3 UNIT MIN MAX 22.2 (3) ISP18 tW(pclkH) Typical pulse duration, cam_pclk high 0.5*P ISP18 tW(pclkL) Typical pulse duration, cam_pclk low 0.5*P (3) tdc(pclk) Duty cycle error, cam_pclk ns 0.5*P (3) ns 0.5*P (3) 667 (4) 133 ps 200 ps PRODUCT PREVIEW tj(pclk) Cycle jitter ISP19 tsu(dV-pclkH) Setup time, cam_d[11:0] valid before cam_pclk rising edge 1.82 3.25 ns ISP20 th(pclkH-dV) Hold time, cam_d[11:0] valid after cam_pclk rising edge 1.82 3.25 ns ISP21 tsu(dV-vsH) Setup time, cam_vs valid before cam_pclk rising edge 1.82 3.25 ns ISP22 th(pclkH-vsV) Hold time, cam_vs valid after cam_pclk rising edge 1.82 3.25 ns ISP23 tsu(dV-hsH) Setup time, cam_hs valid before cam_pclk rising edge 1.82 3.25 ns ISP24 th(pclkH-hsV) Hold time, cam_hs valid after cam_pclk rising edge 1.82 3.25 ns ISP25 tsu(dV-hsH) Setup time, cam_wen valid before cam_pclk rising edge 1.82 3.25 ns ISP26 th(pclkH-hsV) Hold time, cam_wen valid after cam_pclk rising edge 1.82 3.25 ns ISP27 tsu(dV-fldH) Setup time, cam_fld valid before cam_pclk rising edge 1.82 3.25 ns ISP28 th(pclkH-fldV) Hold time, cam_fld valid after cam_pclk rising edge 1.82 3.25 ns (1) (2) (3) (4) , cam_pclk ns 1111 The timing requirements are assured for the cycle jitter and duty cycle error conditions specified. Related with the input maximum frequency supported by the ISP module. P = cam_lclk period in ns. Maximum cycle jitter supported by cam_pclk input clock. Table 6-30. ISP Switching Characteristics – 12-Bit SYNC Normal – Interlaced Mode NO. PARAMETER 1.15 V MIN ISP15 tc(xclk) Cycle time (1), cam_xclk period 1.0 V MAX 4.6 tW(xclkH) Typical pulse duration, cam_xclk high 0.5*PO ISP16 tW(xclkL) Typical pulse duration, cam_xclk low 0.5*PO (2) tdc(xclk) Duty cycle error, cam_xclk (1) (2) (3) 190 , cam_xclk UNIT MAX 4.6 (2) ISP16 (3) MIN ns 0.5*PO (2) ns 0.5*PO 231 ns (2) 231 ps tj(xclk) Jitter standard deviation 33 33 ps tR(xclk) Rise time, cam_xclk 0.93 0.93 ns tF(xclk) Fall time, cam_xclk 0.93 0.93 ns Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module. Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98 PO = cam_xclk period in ns. The jitter probability density can be approximated by a Gaussian function. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 ISP16 ISP15 ISP16 cam_xclki ISP18 ISP17 ISP18 cam_pclk ISP20 FRAME(0) cam_vs FRAME(0) ISP21 L(0) cam_hs ISP22 L(n-1) L(0) ISP23 cam_d[11:0] D(0) D(n-3) D(n-2) PRODUCT PREVIEW ISP19 D(n-1) D(0) D(1) ISP24 D(2) ISP25 D(n-1) ISP26 cam_wen ISP28 ISP27 cam_fld PAIR IMPAIR 030-057 (1)(2)(3)(4)(5)(6)(7)(8) Figure 6-25. ISP – 12-Bit SYNC Normal – Interlaced Mode (1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output, the signal length can be set. (2) The parallel camera in SYNC mode supports interlaced image sensor modules and 8-, 10-, 11-, or 12-bit data. (3) When the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be grounded. (4) It is possible to shift the data to 0, 2, or 4 data internal lanes. (5) The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit mode, and cam_d[11:0] in 12-bit mode. (6) Optionally, the data write to memory can be qualified by the external cam_wen signal. (7) The cam_wen signal can be used as a external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. (8) In cam_xclki; I is equal to a or b. 6.5.1.1.1.4 8-bit Packed SYNC – Interlaced Mode Table 6-32 and Table 6-33 assume testing over the recommended operating conditions and electrical characteristic conditions (see Figure 6-26). Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 191 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-31. ISP Timing Conditions – 8-bit Packed SYNC – Interlaced Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2.5 ns tF Input signal fall time 2.5 ns Output load capacitance 8.6 pF Output Conditions CLOAD Table 6-32. ISP Timing Requirements – 8-bit Packed SYNC – Interlaced Mode (1) NO. PARAMETER 1.15 V MIN PRODUCT PREVIEW ISP3 tc(pclk) Cycle time (2), cam_pclk period ISP4 tW(pclkH) Typical pulse duration, cam_pclk high ISP4 1.0 V MAX 7.7 MIN UNIT MAX 15.4 ns 0.5*P (3) 0.5*P (3) (3) (3) tW(pclkL) Typical pulse duration, cam_pclk low tdc(pclk) Duty cycle error, cam_pclk 385 769 ps tj(pclk) Cycle jitter (4), cam_pclk 83 167 ps ISP5 tsu(dV-pclkH) Setup time, cam_d[11:0] valid before cam_pclk rising edge 1.08 2.27 ns ISP6 th(pclkH-dV) Hold time, cam_d[11:0] valid after cam_pclk rising edge 1.08 2.27 ns ISP7 tsu(dV-vsH) Setup time, cam_vs valid before cam_pclk rising edge 1.08 2.27 ns ISP8 th(pclkH-vsV) Hold time, cam_vs valid after cam_pclk rising edge 1.08 2.27 ns ISP9 tsu(dV-hsH) Setup time, cam_hs valid before cam_pclk rising edge 1.08 2.27 ns ISP10 th(pclkH-hsV) Hold time, cam_hs valid after cam_pclk rising edge 1.08 2.27 ns ISP11 tsu(dV-hsH) Setup time, cam_wen valid before cam_pclk rising edge 1.08 2.27 ns ISP12 th(pclkH-hsV) Hold time, cam_wen valid after cam_pclk rising edge 1.08 2.27 ns ISP13 tsu(dV-fldH) Setup time, cam_fld valid before cam_pclk rising edge 1.08 2.27 ns ISP14 th(pclkH-fldV) Hold time, cam_fld valid after cam_pclk rising edge 1.08 2.27 ns (1) (2) (3) (4) 0.5*P 0.5*P ns ns The timing requirements are assured for the cycle jitter and duty cycle error conditions specified. Related with the input maximum frequency supported by the ISP module. P = cam_lclk period in ns. Maximum cycle jitter supported by cam_pclk input clock. Table 6-33. ISP Switching Characteristics – 8-bit Packed SYNC – Interlaced Mode NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX ISP16 tc(xclk) Cycle time (1), cam_xclk period ISP2 tW(xclkH) Typical pulse duration, cam_xclk high 0.5*PO (2) 0.5*PO (2) ns ISP2 tW(xclkL) Typical pulse duration, cam_xclk low 0.5*PO (2) 0.5*PO (2) ns tdc(xclk) Duty cycle error, cam_xclk (1) (2) (3) 192 (3) , cam_xclk 4.6 4.6 231 ns 231 ps tj(xclk) Jitter standard deviation 67 67 ps tR(xclk) Rise time, cam_xclk 0.93 0.93 ns tF(xclk) Fall time, cam_xclk 0.93 0.93 ns Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module. Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98 PO = cam_xclk period in ns. The jitter probability density can be approximated by a Gaussian function. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 ISP2 ISP1 ISP2 cam_xclki ISP4 ISP3 ISP4 cam_pclk ISP6 cam_vs FRAME(0) FRAME(0) ISP7 cam_hs L(0) ISP8 L(n-1) L(0) ISP10 ISP9 cam_d[7:0] D(0) D(n-3) D(n-2) PRODUCT PREVIEW ISP5 D(n-1) D(0) D(1) D(2) ISP11 D(n-1) ISP12 cam_wen ISP14 ISP13 cam_fld PAIR IMPAIR 030-060 Figure 6-26. ISP – 8-bit Packed SYNC – Interlaced Mode(1)(2)(3)(4)(5) (1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. (2) The image sensor must be connected to the lower data lines and the unused lines must be grounded. However, it is possible to shift the data to 0, 2, or 4 data internal lanes. The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode. (3) Optionally, the data write to memory can be qualified by the external cam_wen signal. The cam_wen signal can be used as a external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. (4) The camera module can pack 8-bit data into 16 bits. It doubles the maximum pixel clock. This mode can be particularly useful to transfer a YCbCr data stream or compressed stream to memory at very high speed. (5) In cam_xclki; I is equal to a or b. 6.5.1.1.2 ITU Mode Table 6-35 and Table 6-36 assume testing over the recommended operating conditions and electrical characteristic conditions (see Figure 6-27). Table 6-34. ISP Timing Conditions – ITU Mode TIMING CONDITION PARAMETER VALUE UNIT 2.7 ns Input Conditions tR Submit Documentation Feedback Input signal rise time TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 193 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-34. ISP Timing Conditions – ITU Mode (continued) TIMING CONDITION PARAMETER tF VALUE UNIT Input signal fall time 2.7 ns Output load capacitance 8.6 pF Output Conditions CLOAD Table 6-35. ISP Timing Requirements – ITU Mode (1) NO. PARAMETER 1.15 V MIN ISP17 tc(pclk) Cycle time (2), cam_pclk period ISP18 tW(pclkH) Typical pulse duration, cam_pclk high ISP18 1.0 V MAX 13.3 MIN UNIT MAX 22.2 ns 0.5*P (3) 0.5*P (3) ns (3) (3) ns PRODUCT PREVIEW tW(pclkL) Typical pulse duration, cam_pclk low tdc(pclk) Duty cycle error, cam_pclk 667 1111 ps tj(pclk) Cycle jitter (4), cam_pclk 133 200 ps ISP23 tsu(dV-pclkH) Setup time, cam_d[9:0] valid before cam_pclk rising edge 1.82 3.25 ns ISP24 th(pclkH-dV) Hold time, cam_d[9:0] valid after cam_pclk rising edge 1.82 3.25 ns (1) (2) (3) (4) 0.5*P 0.5*P The timing requirements are assured for the cycle jitter and duty cycle error conditions specified. Related with the input maximum frequency supported by the ISP module. P = cam_lclk period in ns. Maximum cycle jitter supported by cam_lclk input clock. Table 6-36. ISP Switching Characteristics – ITU Mode NO. PARAMETER 1.15 V MIN ISP15 tc(xclk) Cycle time (1), cam_xclk period 1.0 V MAX 4.6 MIN UNIT MAX 4.6 (2) ns (2) ns 0.5*PO (2) ns ISP16 tW(xclkH) Typical pulse duration, cam_xclk high 0.5*PO ISP16 tW(xclkL) Typical pulse duration, cam_xclk low 0.5*PO (2) tdc(xclk) Duty cycle error, cam_xclk 231 231 ps tj(xclk) Jitter standard deviation (3), cam_xclk 33 33 ps tR(xclk) Rise time, cam_xclk 0.93 0.93 ns tF(xclk) Fall time, cam_xclk 0.93 0.93 ns (1) (2) (3) 194 0.5*PO Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module. Warning: The camera sensor or the camera module must be disabled to change the frequency configuration. For more information, see the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98 PO = cam_xclk period in ns The jitter probability density can be approximated by a Gaussian function. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 ISP16 ISP15 ISP16 cam_xclki ISP17 ISP18 ISP18 cam_pclk ISP23 cam_d[9:0] SOF D (0) ISP24 D(n-1) EOF SOF D(0) D(n-1) EOF Figure 6-27. ISP – ITU Mode (1) The unused lines must be grounded and the data bus must be connected to the lower data lines. It is possible to shift the data to 0, 2, or 4 data internal lanes. The different configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode and cam_d[11:2] or cam_d[9:0] in 10-bit mode. (2) The parallel camera in ITU mode supports progressive camera modules. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 195 PRODUCT PREVIEW 030-058 (1)(2) OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 6.5.2 www.ti.com Display Subsystem (DSS) The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or internal (SRAM) memory on an LCD panel or a TV set. The DSS integrates a display controller, a remote frame buffer module (RFBI), and a TV-out module. It can be used in two configurations: • LCD display support in: – Bypass mode (RFBI module bypassed) – RFBI mode (through RFBI module) • TV display support (not discussed in this document because of its analog IO signals) The two display supports can be active at the same time. 6.5.2.1 LCD Display Support in Bypass Mode PRODUCT PREVIEW Two types of LCD panel are supported: • Thin film transistor (TFT) or active matrix technology • Supertwisted nematic (STN) or passive matrix technology Both configurations are discussed in the following paragraphs. 6.5.2.1.1 LCD Display in TFT Mode Table 6-37 assumes testing over the recommended operating conditions (see Figure 6-28). Table 6-37. LCD Display Interface Switching Characteristics in TFT Mode (1) (2) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX DL0 td(PCLKA-HSYNCT) Delay time, dss_pclk active edge to dss_hsync transition –3.9 3.9 –4.6 4.6 ns DL1 td(PCLKA-VSYNCT) Delay time, dss_pclk active edge to dss_vsync transition –3.9 3.9 –4.6 4.6 ns DL2 td(PCLKA-ACBIASA) Delay time, dss_pclk active edge to dss_acbias active level –3.9 3.9 –4.6 4.6 ns DL3 td(PCLKA-DATAV) Delay time, dss_pclk active edge to dss_data bus valid –3.9 3.9 –4.6 4.6 ns DL4 tc(PCLK) Cycle time (3), dss_pclk 13.5 DL5 (1) (2) (3) (4) 196 tw(PCLK) Pulse duration, dss_pclk low or high 0.45*P 13.5 (4) 0.55*P (4) 0.45*P ns (4) 0.55*P (4) ns The capacitive load is equivalent to 25 pF at 1.15 V and 30 pF at 1.0 V. For more information, see the DSS chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the DISPC_DIVISOR register. P = dss_pclk period. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 DL5 DL4 dss_pclk DL1 dss_vsync DL0 dss_hsync DL2 DL3 dss_data[23:0] 030-061 (1)(2)(3)(4) Figure 6-28. LCD Display in TFT Mode (1) (2) (3) (4) The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins. The pixel clock frequency is programmable. All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk. For more information, see the DSS chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. 6.5.2.1.2 LCD Display in STN Mode Table 6-38 assumes testing over the recommended operating conditions (see Figure 6-29). Table 6-38. LCD Display Interface Switching Characteristics in STN Mode (1) (2) (3) NO. PARAMETER 1.15 V DL3 td(PCLKA-DATAV) Delay time, dss_pclk active edge to dss_data bus valid DL4 tc(PCLK) Cycle time (4), dss_pclk DL5 (1) (2) (3) (4) (5) tw(PCLK) Pulse duration, dss_pclk low or high 1.0 V UNIT MIN MAX MIN MAX –7 7 –7 7 22.7 0.45*P ns 22.7 (5) 0.55*P (5) 0.45*P ns (5) 0.55*P (5) ns The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low. The capacitive load is equivalent to 40 pF. For more information, see the DSS chapter of theOMAP35x Technical Reference Manual (TRM) [literature number SPRUF98] . The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the DISPC_DIVISOR register. P = dss_pclk period. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 197 PRODUCT PREVIEW dss_acbias OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com DL5 DL4 dss_pclk dss_vsync dss_hsync dss_acbias DL3 PRODUCT PREVIEW dss_data[23:0] 030-062 (1)(2)(3)(4)(5) Figure 6-29. LCD Display in STN Mode (1) (2) (3) (4) (5) The pixel data bus depends on the use 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins. All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk. dss_vsync width must be programmed to be as small as possible. The pixel clock frequency is programmable. For more information, see the DSS chapter of theOMAP35x Technical Reference Manual (TRM) [literature number SPRUF98] . 6.5.2.2 LCD Display Support in RFBI Mode Table 6-40 and Table 6-41 assume testing over the recommended operating conditions (see Figure 6-30 through Figure 6-32). Table 6-39. LCD Timing Conditions – RFBI Mode TIMING CONDITION PARAMETER Input Conditions VALUE UNIT MIN MAX tR Input signal rise time 15 ns tF Input signal fall time 15 ns Output load capacitance 30 pF Output Conditions CLOAD Table 6-40. LCD Display Interface Timing Requirements in RFBI Mode NO. PARAMETER 1.15 V 1.0 V 0.95 V UNIT MIN MAX MIN MAX MIN MAX DR1 6 ts(DAV-RDH) Setup time, rfbi_da[15:0] valid to rfbi_rd high 2.5 2.5 + I (1) 2.5 2.5 + I (1) TBD TBD ns DR1 7 th(RDH-DAIV) Hold time, rfbi_rd high to rfbi_da[15:0] invalid 2.5 2.5 + I (1) 2.5 2.5 + I (1) TBD TBD ns (1) 198 I = ((REOffTime – AccessTime) * (TimeParaGranularity + 1) * L4CLK TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-41. LCD Display Interface Switching Characteristics in RFBI Mode PARAMETER 1.15 V MIN DR2 tw(rfbi_wrH) 1.0 V MAX Pulse duration, rfbi_wr high MIN A (1) A (1) (2) B (2) MIN UNIT MAX ns DR3 tw(rfbi_wrL) Pulse duration, rfbi_wr low DR4 td(rfbi_a0- Delay time, rfbi_a0 transition to rfbi_wr low A (1) – 2.5 A (1) + 2.5 A (1) – 2.5 A (1) + 2.5 ns Delay time, rfbi_a0 transition to rfbi_wr high C (3) – 2.5 C (3) + 2.5 C (3) – 2.5 C (3) + 2.5 ns Delay time, rfbi_csx (4) low to rfbi_wr low C (3) – 2.5 C (3) + 2.5 C (3) – 2.5 C (3) + 2.5 ns Delay time, rfbi_wr high to rfbi_csx (4) high D (5) – 2.5 D (5) + 2.5 D (5) – 2.5 D (5) + 2.5 ns Delay time, rfbi_wr low to rfbi_da[15:0] valid B (2) – 2.5 B (2) + 2.5 B (2) – 2.5 B (2) + 2.5 ns rfbi_daV) td(rfbi_a0H- Delay time, rfbi_a0 high to rfbi_rd low F (6) – 2.5 F (6) + 2.5 F (6) – 2.5 F (6) + 2.5 ns Delay time, rfbi_csx (4) low to rfbi_rd low G (7) – 2.5 G (7) + 2.5 G (7) – 2.5 G (7) + 2.5 ns rfbi_rdL) DR12 tw(rfbi_rdH) Pulse duration, rfbi_rd high J (8) J (8) DR13 tw(rfbi_rdL) Pulse duration, rfbi_rd low E (9) E (9) rfbi_wrL) DR5 td(rfbi_a0rfbi_wrH) DR6 td(rfbi_csxrfbi_wrL) DR7 td(rfbi_wrHrfbi_csH) DR8 DR9 td(rfbi_wrL- B 0.95 V MAX rfbi_rdL) DR10 DR14 td(rfbi_csL- td(rfbi_rdLrfbi_csL) DR15 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) Delay time, rfbi_rd low to rfbi_csx low (4) H (10) – H (10) + H (10) – ns H ns ns (10) + ns 2.5 2.5 2.5 2.5 H (10) – 2.5 H (10) + 2.5 H (10) – 2.5 H (10) + 2.5 ns rfbi_csH) Delay time, rfbi_rd high to rfbi_csx (4) high tR(rfbi_wr) Rise time, rfbi_wr 15 15 ns tF(rfbi_wr) Fall time, rfbi_wr 15 15 ns tR(rfbi_a0) Rise time, rfbi_a0 15 15 ns tF(rfbi_a0) Fall time, rfbi_a0 15 15 ns tR(rfbi_csx) Rise time, rfbi_csx 15 15 ns tF(rfbi_csx) Fall time, rfbi_csx 15 15 ns tR(rfbi_da[15:0]) Rise time, rfbi_da[15:0] 15 15 ns tF(rfbi_da[15:0]) Fall time, rfbi_da[15:0] 15 15 ns tR(rfbi_rd) Rise time, rfbi_rd 15 15 ns tF(rfbi_rd) Fall time, rfbi_rd 15 15 ns td(rfbi_rdH- A = (WEOnTime) * (TimeParaGranularity + 1) * L4CLK B = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * L4CLK C = (WEOnTime – CSOnTime) * (TimeParaGranularity + 1) * L4CLK In RFBI_nCSx, x stands for 0 or 1. D = (CSOffTime – WEOffTime) * (TimeParaGranularity + 1) * L4CLK F = REOnTime * (TimeParaGranularity + 1) * L4CLK G = (REOnTime – CSOnTime) * (TimeParaGranularity + 1) * L4CLK J = (REOnTime) * L4CLK E = (REOffTime – REOnTime) * (TimeParaGranularity + 1) * L4CLK H = (CSOffTime – REOffTime) * (TimeParaGranularity + 1) * L4CLK Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 199 PRODUCT PREVIEW NO. OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com CsPulseWidth WeCycleTime WeCycleTime rfbi_a0 CsOffTime CsOffTime CsOnTime CsOnTime rfbi_csx WeOffTime WeOffTime WeOnTime WeOnTime rfbi_wr PRODUCT PREVIEW rfbi_da[15:0] DATA1 DATA0 rfbi_rd 034-002 Figure 6-30. LCD Display Interface in RFBI Mode – Command / Data Write Mode(1)(2) (1) In rfbi_csx, x is equal to 0 or 1. (2) For more information, see the DSS chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. AccessTime AccessTime ReCycleTime ReCycleTime CsPulseWidth rfbi_a0 CsOffTime CsOffTime CsOnTime CsOnTime ReOffTime ReOffTime rfbi_csx ReOnTime ReOnTime rfbi_rd DR0 rfbi_da[15:0] DR1 DATA0 DATA1 rfbi_wr 034-003 Figure 6-31. LCD Display Interface in RFBI Mode – Data Read Mode(1)(2) (1) In rfbi_csx, x is equal to 0 or 1. (2) For more information, see the DSS chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. 200 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 WeCycleTime ReCycleTime AccessTime WeCycleTime rfbi_a0 CsOffTime CsOnTime CsOffTime CsOnTime CsOffTime CsOnTime rfbi_csx WeOffTime WeOffTime WeOnTime WeOnTime rfbi_wr ReOnTime rfbi_rd CsPulseWidth rfbi_da[15:0] WRITE READ CsPulseWidth WRITE 034-004 Figure 6-32. LCD Display Interface in RFBI Mode – Data Read-to-Write and Write-to-Read Modes(1)(2) (1) In rfbi_csx, x is equal to 0 or 1. (2) For more information, see the DSS chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 201 PRODUCT PREVIEW ReOffTime OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 6.6 Serial Communications Interfaces 6.6.1 Multichannel Buffered Serial Port (McBSP) Timing There are five McBSP modules called McBSP1 through McBSP5. McBSP provides a full-duplex, direct serial interface between the OMAP3515/03 device and other devices in a system such as other application devices or codecs. It can accommodate a wide range of peripherals and clocked frame-oriented protocols (I2S, PCM, and TDM) due to its high level of versatility. PRODUCT PREVIEW The McBSP1-5 modules may support two types of data transfer at the system level: • The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge and captured on the same edge (one clock period later). • The half-cycle mode, for which one half clock period is used to transfer the data, generated on one edge and captured on the opposite edge (one half clock period later). Note that a new data is generated only every clock period, which secures the required hold time. The interface clock (CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be configured accordingly with the external peripheral (activation edge capability) and the type of data transfer required at the system level. The OMAP3515/03 McBSP1-5 timing characteristics are described for both rising and falling activation edges. McBSP1 supports: • 6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins. • 4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are internally looped back via software configuration, respectively, to the clkr and fsr internal signals for data receive. McBSP2, 3, 4, and 5 support only the 4-pin mode. The following sections describe the timing characteristics for applications in normal mode (that is, OMAP3515/03 McBSPx connected to one peripheral) and TDM applications in multipoint mode. 6.6.1.1 McBSP in Normal Mode Table 6-42. McBSP Timing Conditions—Normal Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2 ns tF Input signal fall time 2 ns Output load capacitance 10 pF Output Conditions CLOAD Table 6-43. McBSP Output Clock Pulse Duration NO. PARAMETER 1.15 V MIN (1) (2) 202 1.0 V MAX MIN UNIT MAX tW(CLKH) Typical pulse duration, mcbsp1_clkr / mcbspx_clkx high (1) 0.5*P (2) 0.5*P (2) ns tW(CLKL) Typical pulse duration, mcbsp1_clkr / mcbspx_clkx low (1) 0.5*P (2) 0.5*P (2) ns tdc(CLK) Duty cycle error, mcbsp1_clkr / mcbspx_clkx (1) –0.75 0.75 –0.75 0.75 ns In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5. P = mcbsp1_clkr / mcbspx_clkx clock period. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 6.6.1.1.1 Receive Timing with Rising Edge as Activation Edge Table 6-44 through Table 6-49 assume testing over the recommended operating conditions (see Figure 6-33 through Figure 6-34). Table 6-44. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Rising Edge and Receive Mode (1) PARAMETER 1.15 V MIN B3 tsu(DRV-CLKAE) B4 th(CLKAE-DRV) MAX 1.0 V MIN UNIT MAX Setup time, mcbspx_dr valid before mcbsp1_clkr / mcbspx_clkx active edge Master 3.5 7.7 ns Slave 3.7 7.9 ns Hold time, mcbspx_dr valid after mcbsp1_clkr / mcbspx_clkx active edge Master 1 1 ns Slave 0.4 0.4 ns B5 tsu(FSV-CLKAE) Setup time, mcbsp1_fsr / mcbspx_fsx valid before mcbsp1_clkr / mcbspx_clkx active edge 3.7 7.9 ns B6 th(CLKAE-FSV) Hold time, mcbsp1_fsr / mcbspx_fsx valid after mcbsp1_clkr / mcbspx_clkx active edge 0.5 0.5 ns (1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). Table 6-45. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Rising Edge and Receive Mode (1) NO. B2 (1) PARAMETER td(CLKAE-FSV) 1.15 V Delay time, mcbsp1_clkr / mcbspx_clkx active edge to mcbsp1_fsr / mcbspx_fsx valid 1.0 V MIN MAX MIN MAX 0.7 14.8 0.7 29.6 UNIT ns In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). Table 6-46. McBSP4 (Set #1) Timing Requirements – Rising Edge and Receive Mode (1) NO. PARAMETER 1.15 V MIN B3 B4 B5 B6 (1) tsu(DRV-CLKXAE) th(CLKXAE-DRV) MAX 1.0 V MIN UNIT MAX Setup time, mcbspx_dr valid before mcbspx_clkx active edge Master 2.7 7.7 ns Slave 3.7 7.9 ns Hold time, mcbspx_dr valid after mcbspx_clkx active edge Master 1 1 ns Slave 0.4 0.4 ns tsu(FSXV-CLKXAE) Setup time mcbspx_fsx valid before mcbspx_clkx active edge 3.7 7.9 ns th(CLKXAE-FSXV) Hold Time mcbspx_fsx valid after mcbspx_clkx active edge 0.5 0.5 ns In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-48 and Table 6-49 Table 6-47. McBSP4 (Set #1) Switching Characteristics – Rising Edge and Receive Mode (1) NO. B2 (1) PARAMETER td(CLKXAE-FSXV) 1.15 V Delay time, mcbspx_clkx active edge to mcbspx_fsx valid 1.0 V MIN MAX MIN MAX 0.7 16.6 0.7 33.1 UNIT ns In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-48 and Table 6-49 Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 203 PRODUCT PREVIEW NO. OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-48. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Receive Mode (1) NO. PARAMETER 1.15 V MIN B3 tsu(DRV-CLKXAE) 1.0 V MAX MIN UNIT MAX Setup time, mcbspx_dr valid before mcbspx_clkx active edge Master 5.6 12 ns Slave 5.8 12.2 ns Master 1 1 ns Slave B4 th(CLKXAE-DRV) Hold time, mcbspx_dr valid after mcbspx_clkx active edge 0.4 0.4 ns B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx active edge 5.8 12.2 ns B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active edge 0.5 0.5 ns (1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in Table 6-46 and Table 6-47. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). PRODUCT PREVIEW Table 6-49. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Rising Edge and Receive Mode (1) NO. B2 PARAMETER td(CLKXAE-FSXV) 1.15 V 1.0 V UNIT MIN MAX MIN MAX 0.7 22.2 0.7 44.4 Delay time, mcbspx_clkx active edge to mcbspx_fsx valid ns mcbspx_clkr B2 B2 mcbspx_fsr B3 mcbspx_dr B4 D7 D5 D6 030-068 Figure 6-33. McBSP Rising Edge Receive Timing in Master Mode mcbspx_clkr B5 B6 mcbspx_fsr B3 mcbspx_dr B4 D7 D6 D5 030-069 Figure 6-34. McBSP Rising Edge Receive Timing in Slave Mode (1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in Table 6-46 and Table 6-47. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). 6.6.1.1.2 Transmit Timing with Rising Edge as Activation Edge Table 6-50 through Table 6-55 assume testing over the recommended operating conditions (see Figure 6-35 and Figure 6-36). Table 6-50. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Rising Edge and Transmit Mode (1) NO. PARAMETER 1.15 V MIN B5 (1) 204 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx active edge 3.7 MAX 1.0 V MIN 7.9 UNIT MAX ns In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-50. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Rising Edge and Transmit Mode (continued) NO. PARAMETER 1.15 V MIN B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active edge MAX 0.5 1.0 V MIN UNIT MAX 0.5 ns Table 6-51. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Rising Edge and Transmit Mode (1) PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx valid 0.7 14.8 0.7 29.6 ns B8 td(CLKXAE-DXV) Delay time, mcbspx_clkx active edge to mcbspx_dx valid Master 0.6 14.8 0.6 29.6 ns Slave 0.6 14.8 0.6 29.6 ns (1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). Table 6-52. McBSP4 (Set #1) Timing Requirements – Rising Edge and Transmit Mode (1) NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx active edge 3.7 7.9 ns B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active edge 0.5 0.5 ns (1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-54. Table 6-53. McBSP4 (Set #1) Switching Characteristics – Rising Edge and Transmit Mode (1) NO. PARAMETER 1.15 V B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx valid B8 td(CLKXAE-DXV) Delay time, mcbspx_clkx active edge to mcbspx_dx valid (1) 1.0 V UNIT MIN MAX MIN MAX 0.7 16.6 0.7 33.1 ns Master 0.6 16.6 0.6 33.1 ns Slave 0.6 17.3 0.6 33.1 ns In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-54. Table 6-54. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Transmit Mode (1) NO. PARAMETER 1.15 V MIN MAX 1.0 V MIN UNIT MAX B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx active edge 5.8 12.2 ns B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active edge 0.5 0.5 ns (1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-54. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 205 PRODUCT PREVIEW NO. OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-55. McBSP 3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Rising Edge and Transmit Mode (1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx valid 0.7 22.2 0.7 44.4 ns B8 td(CLKXAE-DXV) Delay time, mcbspx_clkx active edge to mcbspx_dx valid Master 0.6 22.2 0.6 44.4 ns Slave 0.6 22.2 0.6 44.4 ns mcbspx_clkx B2 B2 mcbspx_fsx PRODUCT PREVIEW B8 mcbspx_dx D7 D6 D5 030-070 Figure 6-35. McBSP Rising Edge Transmit Timing in Master Mode mcbspx_clkx B5 B6 mcbspx_fsx B8 mcbspx_dx D7 D6 D5 030-071 Figure 6-36. McBSP Rising Edge Transmit Timing in Slave Mode (1) In mcbspx, x identifies the McBSP number: 3, 4 or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). 6.6.1.1.3 Receive Timing with Falling Edge as Activation Edge Table 6-56 through Table 6-61 assume testing over the recommended operating conditions (see Figure 6-37 and Figure 6-38). Table 6-56. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Falling Edge and Receive Mode (1) NO. PARAMETER 1.15 V MIN MAX 1.0 V MIN UNIT MAX B3 tsu(DRV-CLKAE) Setup time, mcbspx_dr valid before mcbsp1_clkr / mcbspx_clkx active edge Master 3.5 7.7 ns Slave 3.7 7.9 ns B4 th(CLKAE-DRV) Hold time, mcbspx_dr valid after mcbsp1_clkr / mcbspx_clkx active edge Master 1 1 ns Slave 0.4 0.4 ns B5 tsu(FSV-CLKAE) Setup time, mcbsp1_fsr / mcbspx_fsx valid before mcbsp1_clkr /mcbspx_clkx active edge 3.7 7.9 ns B6 th(CLKAE-FSV) Hold time, mcbsp1_fsr / mcbspx_fsx valid after mcbsp1_clkr /mcbspx_clkx active edge 0.5 0.5 ns (1) 206 In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-57. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Falling Edge and Receive Mode (1) NO. B2 (1) PARAMETER td(CLKAE-FSV) 1.15 V Delay time, mcbsp1_clkr / mcbspx_clkx active edge to mcbsp1_fsr / mcbspx_fsx valid 1.0 V UNIT MIN MAX MIN MAX 0.7 14.8 0.7 29.6 ns In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). Table 6-58. McBSP4 (Set #1) Timing Requirements – Falling Edge and Receive Mode (1) PARAMETER 1.15 V MIN MAX 1.0 V MIN UNIT MAX B3 tsu(DRV-CLKXAE) Setup time, mcbspx_dr valid before mcbspx_clkx active edge Master 2.7 7.7 ns Slave 3.7 7.9 ns B4 th(CLKXAE-DRV) Hold time, mcbspx_dr valid after mcbspx_clkx active edge Master 1 1 ns Slave 0.4 0.4 ns B5 tsu(FSXV-CLKXAE) Setup time mcbspx_fsx valid before mcbspx_clkx active edge 3.7 7.9 ns B6 th(CLKXAE-FSXV) Hold time mcbspx_fsx valid after mcbspx_clkx active edge 0.5 0.5 ns (1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-60 Table 6-59. McBSP4 (Set #1) Switching Characteristics – Falling Edge and Receive Mode (1) NO. B2 (1) PARAMETER td(CLKXAE-FSXV) 1.15 V Delay time, mcbspx_clkx active edge to mcbspx_fsx valid 1.0 V UNIT MIN MAX MIN MAX 0.7 16.6 0.7 33.1 ns In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-60 Table 6-60. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Falling Edge and Receive Mode (1) NO. PARAMETER 1.15 V MIN B3 B4 tsu(DRV-CLKXAE) th(CLKXAE-DRV) MAX 1.0 V MIN UNIT MAX Setup time, mcbspx_dr valid before mcbspx_clkx active edge Master 5.6 12 ns Slave 5.8 12.2 ns Hold time, mcbspx_dr valid after mcbspx_clkx active edge Master 1 1 ns Slave 0.4 0.4 ns B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx active edge 5.8 12.2 ns B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active edge 0.5 0.5 ns (1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 207 PRODUCT PREVIEW NO. OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-61. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Falling Edge and Receive Mode (1) NO. B2 PARAMETER td(CLKXAE-FSXV) (1) 1.15 V Delay time, mcbspx_clkx active edge to mcbspx_fsx valid 1.0 V UNIT MIN MAX MIN MAX 0.7 22.2 0.7 44.4 ns In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). mcbspx_clkr B2 B2 mcbspx_fsr PRODUCT PREVIEW B3 mcbspx_dr B4 D7 D6 D5 030-072 Figure 6-37. McBSP Falling Edge Receive Timing in Master Mode mcbspx_clkr B5 B6 mcbspx_fsr B3 mcbspx_dr B4 D7 D6 D5 030-073 Figure 6-38. McBSP Falling Edge Receive Timing in Slave Mode 6.6.1.1.4 Transmit Timing with Falling Edge as Activation Edge Table 6-62 through Table 6-67 assume testing over the recommended operating conditions (see Figure 6-39 and Figure 6-40). Table 6-62. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Falling Edge and Transmit Mode (1) NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx active edge 3.7 7.9 ns B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active edge 0.5 0.5 ns (1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). Table 6-63. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Falling Edge and Transmit Mode (1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx valid 0.7 14.8 0.7 29.6 ns B8 td(CLKXAE-DXV) Delay time, mcbspx_clkx active edge to mcbspx_dx valid Master 0.6 14.8 0.6 29.6 ns Slave 0.6 14.8 0.6 29.6 ns (1) 208 In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-64. McBSP4 (Set #1) Timing Requirements – Falling Edge and Transmit Mode (1) NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx active edge 3.7 7.9 ns B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active edge 0.5 0.5 ns (1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-66. Table 6-65. McBSP4 (Set #1) Switching Characteristics – Falling Edge and Transmit Mode (1) PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx valid 0.7 16.6 0.7 33.1 ns B8 td(CLKXAE-DXV) Delay time, mcbspx_clkx active edge to mcbspx_dx valid Master 0.6 16.6 0.6 33.1 ns Slave 0.6 17.3 0.6 33.1 ns (1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-66. Table 6-66. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Falling Edge and Transmit Mode (1) NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx active edge 5.8 12.2 ns B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active edge 0.5 0.5 ns (1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in Table 6-66. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). Table 6-67. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Falling Edge and Transmit Mode (1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx valid 0.7 22.2 0.7 44.4 ns B8 td(CLKXAE-DXV) Delay time, mcbspx_clkx active edge to mcbspx_dx valid Master 0.6 22.2 0.6 44.4 ns Slave 0.6 22.2 0.6 44.4 ns (1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in Table 6-66. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). mcbspx_clkx B2 B2 mcbspx_fsx B8 mcbspx_dx D7 D6 D5 030-074 Figure 6-39. McBSP Falling Edge Transmit Timing in Master Mode Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 209 PRODUCT PREVIEW NO. OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com mcbspx_clkx B5 B6 mcbspx_fsx B8 mcbspx_dx D7 D6 D5 030-075 Figure 6-40. McBSP Falling Edge Transmit Timing in Slave Mode 6.6.1.2 McBSP in TDM—Multipoint Mode (McBSP3) For TDM application in multipoint mode, OMAP3515/03 is considered as a slave. Table 6-69 and Table 6-70 assume testing over the operating conditions and electrical characteristic conditions described below. PRODUCT PREVIEW Table 6-68. McBSP3 Timing Conditions—TDM in Multipoint Mode TIMING CONDITION PARAMETER VALUE UNIT MIN MAX Input Conditions tR Input signal rising time 1.0 8.5 ns tF Input signal falling time 1.0 8.5 ns 40 pF Output Conditions CLOAD Output Load Capacitance Table 6-69. McBSP3 Timing Requirements—TDM in Multipoint Mode (1) NO. PARAMETER 1.15 V MIN tW(CLKH) Cycle Time, mcbsp3_clkx tW(CLKH) Typical Pulse duration, mcbsp3_clkx high tW(CLKL) Typical Pulse duration, mcbsp3_clkx low tdc(CLK) Duty cycle error, mcbsp3_clkx B3 (3) tsu(DRV-CLKAE) Setup time, mcbsp3_dr valid before mcbsp3_clkx active edge B4 (3) th(CLKAE-DRV) Hold time, mcbsp3_dr valid after mcbsp3_clkx active edge B5 (3) tsu(FSV-CLKAE) Setup time, mcbsp3_fsx valid before mcbsp3_clkx active edge B6 (3) th(CLKAE-FSV) Hold time, mcbsp3_fsx valid after mcbsp3_clkx active edge (1) (2) (3) 1.0 V MAX 162.8 MIN UNIT MAX 162.8 ns 0.5*P (2) 0.5*P (2) (2) (2) 0.5*P –8.14 0.5*P 8.14 –8.14 ns ns 8.14 ns 9 9 ns 2.4 2.4 ns 9 9 ns 2.4 2.4 ns For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins). P = mcbsp3_clkx period in ns See Section 6.6.1.1, McBSP in Normal Mode for corresponding figures. Table 6-70. McBSP3 Switching Characteristics—TDM in Multipoint Mode (1) NO. B8 (2) (1) (2) 210 PARAMETER td(CLKXAE-DXV) Delay time, mcbsp3_clkx active edge to mcbsp3_dx valid 1.15 V 1.0 V UNIT MIN MAX MIN MAX 0.6 16.8 0.6 29.6 ns For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins). See Section 6.6.1.1, McBSP in Normal Mode for corresponding figures. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com 6.6.2 SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Multichannel Serial Port Interface (McSPI) Timing The multichannel SPI is a master/slave synchronous serial bus. The McSPI1 module supports up to four peripherals and the others (McSPI2, McSPI3, and McSPI4) support up to two peripherals. The following timings are applicable to the different configurations of McSPI in master/slave mode for any McSPI and any channel (n). 6.6.2.1 McSPI in Slave Mode Table 6-71 and Table 6-72 assume testing over the recommended operating conditions (see Figure 6-41). Table 6-71. McSPI Interface Timing Requirements – Slave Mode (1) (2) PARAMETER 1.15 V MIN SS0 tc(CLK) Cycle time, mcspix_clk 1.0 V MAX 41.7 UNIT MAX 83.3 (3) 0.55*P (3) 0.45*P ns (3) 0.55*P (3) SS1 tw(CLK) Pulse duration, mcspix_clk high or low SS2 tsu(SIMOV-CLKAE) Setup time, mcspix_simo valid before mcspix_clk active edge 4.2 9.5 ns SS3 th(SIMOV-CLKAE) Hold time, mcspix_simo valid after mcspix_clk active edge 4.6 9.9 ns SS4 tsu(CS0V-CLKFE) Setup time, mcspix_cs0 valid before mcspix_clk first edge 13.8 28.6 ns SS5 th(CS0I-CLKLE) Hold time, mcspix_cs0 invalid after mcspix_clk last edge 13.8 28.6 ns (1) (2) (3) 0.45*P MIN ns The input timing requirements are given by considering a rise time and a fall time of 4 ns. In mcspix, x is equal to 1, 2, 3, or 4. P = mcspix_clk clock period Table 6-72. McSPI Interface Switching Requirements (1) (2) (3) (4) NO. PARAMETER 1.15 V SS6 td(CLKAE-SOMIV) Delay time, mcspix_clk active edge to mcspix_somi shifted SS7 td(CS0AE-SOMIV) Delay time, mcspix_cs0 active edge to Modes 0 and 2 mcspix_somi shifted (1) (2) (3) (4) 1.0 V UNIT MIN MAX MIN MAX 1.8 15.9 3.2 31.7 ns 31.7 ns 15.9 The capacitive load is equivalent to 20 pF. In mcspix, x is equal to 1, 2, 3, or 4. The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all software configurable. This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and capture input data. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 211 PRODUCT PREVIEW NO. OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Mode 0 & 2 mcspix_cs0(EPOL=1) SS0 SS4 SS5 SS1 mcspix_clk(POL=0) SS0 SS1 mcspix_clk(POL=1) SS2 SS3 Bit n-1 PRODUCT PREVIEW mcspix_simo Bit n-2 SS7 Bit n-4 Bit 0 SS6 Bit n-1 mcspix_somi Bit n-3 Bit n-2 Bit n-3 Bit n-4 Bit 0 Mode 1 & 3 mcspix_cs0(EPOL=1) SS0 SS1 mcspix_clk(POL=0) SS0 SS1 SS4 SS5 mcspix_clk(POL=1) SS3 SS2 Bit n-1 mcspix_simo Bit n-2 Bit n-3 Bit 1 Bit 0 SS6 Bit n-1 mcspix_somi Bit n-2 Bit n-3 Bit 1 Bit 0 030-076 Figure 6-41. McSPI Interface – Transmit and Receive in Slave Mode(1)(2) (1) The active clock edge (rising or falling) on which mcspi_somi is driven and mcspi_simo data is latched is software configurable with the bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL. (2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL In mcspix, x is equal to 1, 2, 3, or 4. 6.6.2.2 McSPI in Master Mode Table 6-73 and Table 6-74 assume testing over the recommended operating conditions (see Figure 6-42). Table 6-73. McSPI1, 2, and 4 Interface Timing Requirements – Master Mode (1) (2) NO. PARAMETER 1.15 V MIN MAX 1.0 V MIN UNIT MAX SM2 tsu(SOMIV-CLKAE) Setup time, mcspix_somi valid before mcspix_clk active edge 1.1 1.5 ns SM3 th(SOMIV-CLKAE) Hold time, mcspix_somi valid after mcspix_clk active edge 1.9 2.8 ns (1) (2) 212 The input timing requirements are given by considering a rise time and a fall time of 4 ns. In mcspix, x is equal to 1, 2, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-74. McSPI1, 2, and 4 Interface Switching Characteristics – Master Mode (1) (2) (3) PARAMETER 1.15 V MIN SM0 tc(CLK) Cycle time, mcspix_clk SM1 tw(CLK) Pulse duration, mcspix_clk high or low SM4 td(CLKAE-SIMOV) Delay time, mcspix_clk active edge to mcspix_simo shifted SM5 td(CSnA-CLKFE) Delay time, mcspix_csi active to mcspix_clk first edge SM6 SM7 (1) (2) (3) (4) (5) (6) td(CLKLE-CSnI) td(CSnAE-SIMOV) 1.0 V MIN 0.45*P (4) 0.55*P (4) 0.45*P ( 0.55*P (4) ns –2.1 5 –2.1 11.3 ns 20.8 Delay time, mcspix_clk last edge to mcspix_csi inactive Delay time, mcspix_csi active edge to mcspix_simo shifted UNIT MAX MAX 41.7 ns 4) Modes 1 and 3 A (5) – 3.1 A (5) – 4.4 ns Modes 0 and 2 B (6) – 3.1 B (6) – 4.4 ns Modes 1 and 3 B (6) – 3.1 B (6) – 4.4 ns Modes 0 and 2 A (5) – 3.1 A (5) – 4.4 ns Modes 0 and 2 5.0 11.3 ns Timings are given for a maximum load capacitance of 20 pF for spix_csn signals, 30 pF for spix_clk and spix_simo signals with x = 1 or 2, and 20 pF for spi4_clk and spi4_simo signals. In mcspix, x is equal to 1, 2, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4. The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all software configurable. P = mcspix_clk clock period Case P = 20.8 ns, A = (TCS+0.5)*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P (TCS is a bitfield of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. Table 6-75 and Table 6-76 assume testing over the recommended operating conditions (see Figure 6-42). Table 6-75. McSPI 3 Interface Timing Requirements – Master Mode (1) (2) NO. PARAMETER 1.15 V MIN MAX 1.0 V MIN UNIT MAX SM2 tsu(SOMIV-CLKAE) Setup time, mcspi3_somi valid before mcspi3_clk active edge 1.5 4.3 ns SM3 th(SOMIV-CLKAE) Hold time, mcspi3_somi valid after mcspi3_clk active edge 2.8 5.9 ns (1) (2) The input timing requirements are given by considering a rise time and a fall time of 4 ns. In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and mcspi3_somi is latched is all software configurable. Table 6-76. McSPI3 Interface Switching Requirements – Master Mode (1) (2) (3) NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN MAX SM0 tc(CLK) Cycle time, mcspix_clk SM1 tw(CLK) Pulse duration, mcspix_clk high or low 0.45*P (4) 0.55*P (4) 0.45*P (4) 0.55*P (4) ns SM4 td(CLKAE-SIMOV) Delay time, mcspix_clk active edge to mcspix_simo shifted –2.1 11.3 –5.3 23.6 ns (1) (2) (3) (4) 41.7 UNIT 83.3 ns The capacitive load is equivalent to 20 pF. In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and mcspi3_somi is latched is all software configurable. This timing applies to all configurations regardless of McSPI3_CLK polarity and which clock edges are used to drive output data and capture input data. P = mcspi3_clk clock period Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 213 PRODUCT PREVIEW NO. OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-76. McSPI3 Interface Switching Requirements – Master Mode (continued) NO. PARAMETER 1.15 V MIN SM5 SM6 SM7 (5) PRODUCT PREVIEW (6) td(CSnA-CLKFE) td(CLKLE-CSnI) MIN UNIT MAX Delay time, mcspix_csi active Modes 1 to mcspix_clk first edge and 3 –4.4 + A (5) –10.1 + A (5) ns Modes 0 and 2 –4.4 + B (6) –10.1 + B (6) ns Modes 1 and 3 –4.4 + A (5) –10.1 + A (5) ns Modes 0 and 2 –4.4 + B (6) –10.1 + B (6) ns Delay time, mcspix_clk last edge to mcspix_csi inactive td(CSnAE-SIMOV) 1.0 V MAX Delay time, mcspix_csi active Modes 0 edge to mcspix_simo shifted and 2 11.3 23.6 ns Case P = 20.8 ns, A = (TCS + 0.5)*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. Mode 0 & 2 mcspix_csn(EPOL=1) SM0 SM1 SM5 SM6 mcspix_clk(POL=0) SM0 SM1 mcspix_clk(POL=1) SM4 SM7 Bit n-1 mcspix_simo Bit n-2 Bit n-3 Bit n-4 Bit 0 SM2 SM3 Bit n-1 mcspix_somi Bit n-2 Bit n-3 Bit 0 Bit n-4 Mode 1 & 3 mcspix_csn(EPOL=1) SM0 SM1 mcspix_clk(POL=0) SM0 SM1 SM5 SM6 mcspix_clk(POL=1) SM4 mcspix_simo Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 SM2 SM3 mcspix_somi Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 030-077 Figure 6-42. McSPI Interface – Transmit and Receive in Master Mode(1)(2)(3) (1) The active clock edge (rising or falling) on which mcspix_simo is driven and mcspi_somi data is latched is software configurable with the bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL. 214 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 PRODUCT PREVIEW (2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL. (3) In mcspix, x is equal to 1. In mcspix_csn, n is equal to 0, 1, 2, or 3. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 215 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 6.6.3 www.ti.com Multiport Full-Speed Universal Serial Bus (USB) Interface The OMAP3515/03 processor provides three USB ports working in full- and low-speed data transactions (up to 12Mbit/s). Connected to either a serial link controller (TLL modes) or a serial PHY (PHY interface modes) it supports: • 6-pin (Tx: Dat/Se0 or Tx: Dp/Dm) unidirectional mode • 4-pin bidirectional mode • 3-pin bidirectional mode 6.6.3.1 Multiport Full-Speed Universal Serial Bus (USB) – Unidirectional Standard 6-pin Mode Table 6-78 and Table 6-79 assume testing over the recommended operating conditions (see Figure 6-43). Table 6-77. Low-/Full-Speed USB Timing Conditions – Unidirectional Standard 6-pin Mode PRODUCT PREVIEW TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2.0 ns tF Input signal fall time 2.0 ns Output load capacitance 15.0 pF Output Conditions CLOAD Table 6-78. Low-/Full-Speed USB Timing Requirements – Unidirectional Standard 6-pin Mode NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX FSU1 td(Vp,Vm) Time duration, mmx_rxdp and mmx_rxdm low together during transition 14.0 14.0 ns FSU2 td(Vp,Vm) Time duration, mmx_rxdp and mmx_rxdm high together during transition 8.0 8.0 ns FSU3 td(RCVU0) Time duration, mmx_rrxcv undefine during a single end 0 (mmx_rxdp and mmx_rxdm low together) 14.0 14.0 ns FSU4 td(RCVU1) Time duration, mmx_rxrcv undefine during a single end 1 (mmx_rxdp and mmx_rxdm high together) 8.0 8.0 ns Table 6-79. Low-/Full-Speed USB Switching Characteristics – Unidirectional Standard 6-pin Mode NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX FSU5 td(TXENL-DATV) Delay time, mmx_txen_n low to mmx_txdat valid 81.8 84.8 81.8 84.8 ns FSU6 td(TXENL-SE0V) Delay time, mmx_txen_n low to mmx_txse0 valid 81.8 84.8 81.8 84.8 ns FSU7 ts(DAT-SE0) Skew between mmx_txdat and mmx_txse0 transition 1.5 ns FSU8 td(DATI-TXENH) Delay time, mmx_txdat invalid to mmx_txen_n high 81.8 81.8 ns FSU9 td(SE0I-TXENH) Delay time, mmx_txse0 invalid to mmx_txen_n high 81.8 81.8 ns tR(do) Rise time, mmx_txen_n 4.0 4.0 ns tF(do) Fall time, mmx_txen_n 4.0 4.0 ns tR(do) Rise time, mmx_txdat 4.0 4.0 ns tF(do) Fall time, mmx_txdat 4.0 4.0 ns tR(do) Rise time, mmx_txse0 4.0 4.0 ns tF(do) Fall time, mmx_txse0 4.0 4.0 ns 216 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 1.5 Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Transmit mmx_txen_n Receive FSU5 FSU8 mmx_txdat FSU6 FSU7 FSU9 mmx_txse0 FSU1 FSU2 FSU1 FSU2 FSU3 FSU4 mmx_rxdp mmx_rxrcv 030-080 In mmx, x is equal to 0, 1, or 2. Figure 6-43. Low-/Full-Speed USB – Unidirectional Standard 6-pin Mode 6.6.3.2 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional Standard 4-pin Mode Table 6-81 and Table 6-82 assume testing over the recommended operating conditions (see Figure 6-44). Table 6-80. Low-/Full-Speed USB Timing Conditions – Bidirectional Standard 4-pin Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2.0 ns tF Input signal fall time 2.0 ns Output load capacitance 15.0 pF Output Conditions CLOAD Table 6-81. Low-/Full-Speed USB Timing Requirements – Bidirectional Standard 4-pin Mode NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX FSU10 td(DAT,SE0) Time duration, mmx_txdat and mmx_txse0 low together during transition 14.0 14.0 ns FSU11 td(DAT,SE0) Time duration, mmx_txdat and mmx_txse0 high together during transition 8.0 8.0 ns FSU12 td(RCVU0) Time duration, mmx_rrxcv undefine during a single end 0 (mmx_txdat and mmx_txse0 low together) 14.0 14.0 ns FSU13 td(RCVU1) Time duration, mmx_rxrcv undefine during a single end 1 (mmx_txdat and mmx_txse0 high together) 8.0 8.0 ns Table 6-82. Low-/Full-Speed USB Switching Characteristics – Bidirectional Standard 4-pin Mode NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX FSU14 td(TXENL-DATV) Delay time, mmx_txen_n low to mmx_txdat valid 81.8 84.8 81.8 84.8 ns FSU15 td(TXENL-SE0V) Delay time, mmx_txen_n low to mmx_txse0 valid 81.8 84.8 81.8 84.8 ns FSU16 ts(DAT-SE0) Skew between mmx_txdat and mmx_txse0 transition 1.5 ns FSU17 td(DATV-TXENH) Delay time, mmx_txdat invalid before mmx_txen_n high Submit Documentation Feedback 1.5 81.8 81.8 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS ns 217 PRODUCT PREVIEW mmx_rxdm OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-82. Low-/Full-Speed USB Switching Characteristics – Bidirectional Standard 4-pin Mode (continued) NO. PARAMETER 1.15 V MIN FSU18 1.0 V MAX 81.8 MIN UNIT MAX td(SE0V-TXENH) Delay time, mmx_txse0 invalid before mmx_txen_n high 81.8 tR(txen) Rise time, mmx_txen_n 4.0 4.0 ns tF(txen) Fall time, mmx_txen_n 4.0 4.0 ns tR(dat) Rise time, mmx_txdat 4.0 4.0 ns tF(dat) Fall time, mmx_txdat 4.0 4.0 ns tR(se0) Rise time, mmx_txse0 4.0 4.0 ns tF(se0) Fall time, mmx_txse0 4.0 4.0 ns PRODUCT PREVIEW Transmit mmx_txen_n FSU14 ns FSU17 Receive FSU10 FSU11 FSU18 FSU10 FSU11 FSU12 FSU13 mmx_txdat FSU15 FSU16 mmx_txse0 mmx_rxrcv 030-081 In mmx, x is equal to 0, 1, or 2. Figure 6-44. Low-/Full-Speed USB – Bidirectional Standard 4-pin Mode 6.6.3.3 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional Standard 3-pin Mode Table 6-84 and Table 6-85 assume testing over the recommended operating conditions below (see Figure 6-45). Table 6-83. Low-/Full-Speed USB Timing Conditions – Bidirectional Standard 3-pin Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2.0 ns tF Input signal fall time 2.0 ns Output load capacitance 15.0 pF Output Conditions CLOAD Table 6-84. Low-/Full-Speed USB Timing Requirements – Bidirectional Standard 3-pin Mode NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX FSU19 td(DAT,SE0) Time duration, mmx_txdat and mmx_txse0 low together during transition 14.0 14.0 ns FSU20 td(DAT,SE0) Time duration, mmx_tsdat and mmx_txse0 high together during transition 8.0 8.0 ns 218 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-85. Low-/Full-Speed USB Switching Characteristics – Bidirectional Standard 3-pin Mode PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX FSU21 td(TXENL-DATV) Delay time, mmx_txen_n low to mmx_txdat valid 81.8 84.8 81.8 84.8 ns FSU22 td(TXENL-SE0V) Delay time, mmx_txen_n low to mmx_txse0 valid 81.8 84.8 81.8 84.8 ns FSU23 ts(DAT-SE0) Skew between mmx_txdat and mmx_txse0 transition 1.5 ns FSU24 td(DATI-TXENH) Delay time, mmx_txdat invalid to mmx_txen_n high 81.8 81.8 ns FSU25 td(SE0I-TXENH) Delay time, mmx_txse0 invalid to mmx_txen_n high 81.8 81.8 ns tR(do) Rise time, mmx_txen_n 4.0 4.0 ns tF(do) Fall time, mmx_txen_n 4.0 4.0 ns tR(do) Rise time, mmx_txdat 4.0 4.0 ns tF(do) Fall time, mmx_txdat 4.0 4.0 ns tR(do) Rise time, mmx_txse0 4.0 4.0 ns tF(do) Fall time, mmx_txse0 4.0 4.0 ns 1.5 Transmit mmx_txen_n PRODUCT PREVIEW NO. Receive FSU21 FSU24 FSU19 FSU20 FSU25 FSU19 FSU20 mmx_txdat FSU22 FSU23 mmx_txse0 030-082 In mmx, x is equal to 0, 1, or 2. Figure 6-45. Low-/Full-Speed USB – Bidirectional Standard 3-pin Mode 6.6.3.4 Multiport Full-Speed Universal Serial Bus (USB) – Unidirectional TLL 6-pin Mode Table 6-87 and Table 6-88 assume testing over the recommended operating conditions (see Figure 6-46). Table 6-86. Low-/Full-Speed USB Timing Conditions – Unidirectional TLL 6-pin Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2 ns tF Input signal fall time 2 ns Output load capacitance 15 pF Output Conditions CLOAD Table 6-87. Low-/Full-Speed USB Timing Requirements – Unidirectional TLL 6-pin Mode NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX FSUT1 td(SE0,DAT) Time duration, mmx_txse0 and mmx_txdat low together during transition 14 14 ns FSUT2 td(SE0,DAT) Time duration, mmx_txse0 and mmx_txdat high together during transition 8 8 ns Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 219 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-88. Low-/Full-Speed USB Switching Characteristics – Unidirectional TLL 6-pin Mode NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX td(TXENH-DPV) Delay time, mmx_txen_n high to mmx_rxdp valid 81.8 84.8 81.8 84.8 ns FSUT4 td(TXENH-DMV) Delay time, mmx_txen_n high to mmx_rxdm valid 81.8 84.8 81.8 84.8 ns FSUT5 td(DPI-TXENL) Delay time, mmx_rxdp invalid mmx_txen_n low 81.8 FSUT6 td(DMI-TXENL) Delay time, mmx_rxdm invalid mmx_txen_n low 81.8 FSUT7 ts(DP-DM) Skew between mmx_rxdp and mmx_rxdm transition 1.5 1.5 ns FSUT8 ts(DP,DM-RCV) Skew between mmx_rxdp, mmx_rxdm, and mmx_rxrcv transition 1.5 1.5 ns tR(rxrcv) Rise time, mmx_rxrcv 4 4 ns tF(rxrcv) Fall time, mmx_rxrcv 4 4 ns tR(dp) Rise time, mmx_rxdp 4 4 ns tF(dp) Fall time, mmx_rxdp 4 4 ns tR(dm) Rise time, mmx_rxdm 4 4 ns tF(dm) Fall time, mmx_rxdm 4 4 ns PRODUCT PREVIEW FSUT3 mmx_txen_n 81.8 ns 81.8 Transmit ns Receive FSUT1 FSUT2 FSUT1 FSUT2 mmx_txdat mmx_txse0 FSUT3 FSUT5 mmx_rxdp FSUT4 FSUT7 FSUT6 mmx_rxdm FSUT8 mmx_rxrcv 030-083 In mmx, x is equal to 0, 1, or 2. Figure 6-46. Low-/Full-Speed USB – Unidirectional TLL 6-pin Mode 6.6.3.5 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional TLL 4-pin Mode Table 6-90 and Table 6-91 assume testing over the recommended operating conditions (see Figure 6-47). Table 6-89. Low-/Full-Speed USB Timing Conditions – Bidirectional TLL 4-pin Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2 ns tF Input signal fall time 2 ns Output load capacitance 15 pF Output Conditions CLOAD 220 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-90. Low-/Full-Speed USB Timing Requirements – Bidirectional TLL 4-pin Mode NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX FSUT9 td(DAT,SE0) Time duration, mmx_txdat and mmx_txse0 low together during transition 14 14 ns FSUT10 td(DAT,SE0) Time duration, mmx_tsdat and mmx_txse0 high together during transition 8 8 ns Table 6-91. Low-/Full-Speed USB Switching Characteristics – Bidirectional TLL 4-pin Mode PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX FSUT11 td(TXENL-DATV) Delay time, mmx_txen_n active to mmx_txdat valid 81.8 84.8 81.8 84.8 ns FSUT12 td(TXENL-SE0V) Delay time, mmx_txen_n active to mmx_txse0 valid 81.8 84.8 81.8 84.8 ns FSUT13 ts(DAT-SE0) Skew between mmx_txdat and mmx_txse0 transition 1.5 1.5 ns FSUT14 ts(DP,DM-RCV) Skew between mmx_rxdp, mmx_rxdm, and mmx_rxrcv transition 1.5 1.5 ns FSUT15 td(DATI-TXENL) Delay time, mmx_txse0 invalid to mmx_txen_n Low 81.8 81.8 FSUT16 td(SE0I-TXENL) Delay time, mmx_txdat invalid to mmx_txen_n Low 81.8 81.8 tR(rcv) Rise time, mmx_rxrcv 4 4 ns tF(rcv) Fall time, mmx_rxrcv 4 4 ns tR(dat) Rise time, mmx_txdat 4 4 ns tF(dat) Fall time, mmx_txdat 4 4 ns tR(se0) Rise time, mmx_txse0 4 4 ns tF(se0) Fall time, mmx_txse0 4 4 ns mmx_txen_n ns ns Receive Transmit FSUT11 PRODUCT PREVIEW NO. FSUT15 FSUT9 FSUT10 FSUT16 FSUT9 FSUT10 mmx_txdat FSUT12 FSUT13 mmx_txse0 FSUT14 mmx_rxrcv 030-084 In mmx, x is equal to 0, 1, or 2. Figure 6-47. Low-/Full-Speed USB – Bidirectional TLL 4-pin Mode 6.6.3.6 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional TLL 3-pin Mode Table 6-93 and Table 6-94 assume testing over the recommended operating conditions (see Figure 6-48). Table 6-92. Low-/Full-Speed USB Timing Conditions – Bidirectional TLL 3-pin Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2 ns tF Input signal fall time 2 ns Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 221 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-92. Low-/Full-Speed USB Timing Conditions – Bidirectional TLL 3-pin Mode (continued) TIMING CONDITION PARAMETER VALUE UNIT 15 pF Output Conditions CLOAD Output load capacitance Table 6-93. Low-/Full-Speed USB Timing Requirements – Bidirectional TLL 3-pin Mode NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX FSUT17 td(DAT,SE0) Time duration, mmx_txdat and mmx_txse0 low together during transition 14 14 ns FSUT18 td(DAT,SE0) Time duration, mmx_tsdat and mmx_txse0 high together during transition 8 8 ns PRODUCT PREVIEW Table 6-94. Low-/Full-Speed USB Switching Characteristics – Bidirectional TLL 3-pin Mode NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX FSUT19 td(TXENH-DATV) Delay time, mmx_txen_n high to mmx_txdat valid 81.8 84.8 81.8 84.8 ns FSUT20 td(TXENH-SE0V) Delay time, mmx_txen_n high to mmx_txse0 valid 81.8 84.8 81.8 84.8 ns FSUT21 ts(DAT-SE0) Skew between mmx_txdat and mmx_txse0 transition 1.5 ns FSUT22 td(DATI-TXENL) Delay time, mmx_txdat invalid mmx_txen_n low 81.8 81.8 ns FSUT23 td(SE0I-TXENL) Delay time, mmx_txse0 invalid mmx_txen_n low 81.8 81.8 ns tR(dat) Rise time, mmx_txdat 4 4 ns tF(dat) Fall time, mmx_txdat 4 4 ns tR(se0) Rise time, mmx_txse0 4 4 ns tF(se0) Fall time, mmx_txse0 4 4 ns tR(do) Rise time, mmx_txse0 4 4 ns tF(do) Fall time, mmx_txse0 4 4 ns mmx_txen_n 1.5 Receive Transmit FSUT19 FSUT22 FSUT17 FSUT18 FSUT23 FSUT17 FSUT18 mmx_txdat FSUT20 FSUT21 mmx_txse0 030-085 In mmx, x is equal to 0, 1, or 2. Figure 6-48. Low-/Full-Speed USB – Bidirectional TLL 3-pin Mode 6.6.4 Multiport High-Speed Universal Serial Bus (USB) Timing In addition to the full-speed USB controller, a high-speed (HS) USB OTG controller is instantiated inside OMAP3515/03. It allows high-speed transactions (up to 480 Mbit/s) on the USB ports 0, 1, 2, and 3. • Port 0: – 12-bit slave mode (SDR) • Port 1 and port 2: – 12-bit master mode (SDR) – 12-bit TLL master mode (SDR) 222 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com • SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 – 8-bit TLL master mode (DDR) Port 3: – 12-bit TLL master mode (SDR) – 8-bit TLL master mode (DDR) 6.6.4.1 High-Speed Universal Serial Bus (USB) on Port 0 – 12-bit Slave Mode Table 6-96 and Table 6-97 assume testing over the recommended operating conditions (see Figure 6-49). Table 6-95. High-Speed USB Timing Conditions – 12-bit Slave Mode TIMING CONDITION PARAMETER VALUE UNIT tr Input Signal Rising Time 2.00 ns tf Input Signal Falling Time 2.00 ns Output Load Capacitance 3.50 pF PRODUCT PREVIEW Input Conditions Output Conditions Cload Table 6-96. High-Speed USB Timing Requirements – 12-bit Slave Mode (1) NO. PARAMETER 1.15 V MIN UNIT MAX fp(CLK) hsusb0_clk clock frequency (2) (3) 60.03 MHz tj(CLK) Cycle Jitter (3), hsusb0_clk 500.00 ps ts(DIRV-CLKH) Setup time, hsusb0_dir valid before hsusb0_clk rising edge 6.7 ns ts(NXTV-CLKH) Setup time, hsusb0_nxt valid before hsusb0_clk rising edge 6.7 ns th(CLKH-DIRIV) Hold time, hsusb0_dir valid after hsusb0_clk rising edge 0.0 ns th(CLKH-NXT/IV) Hold time, hsusb0_nxt valid after hsusb0_clk rising edge 0.0 ns HSU5 ts(DATAV-CLKH) Setup time, hsusb0_data[0:7] valid before hsusb0_clk rising edge 6.7 ns HSU6 th(CLKH-DATIV) Hold time, hsusb0_data[0:7] valid after hsusb0_clk rising edge 0.0 ns HSU0 HSU3 HSU4 (1) (2) (3) The timing requirements are assured for the cycle jitter error condition specified. Related with the input maximum frequency supported by the I/F module. Maximum cycle jitter supported by clk input clock. Table 6-97. High-Speed USB Switching Characteristics – 12-bit Slave Mode NO. PARAMETER 1.15 V MIN HSU1 HSU2 UNIT MAX td(clkL-STPV) Delay time, hsusb0_clk high to output usb0_stp valid td(clkL-STPIV) Delay time, hsusb0_clk high to output usb0_stp invalid td(clkL-DV) Delay time, hsusb0_clk high to output hsusb0_data[0:7] valid td(clkL-DIV) Delay time, hsusb0_clk high to output hsusb0_data[0:7] invalid tr(do) Rising time, output signals 2.0 ns tf(do) Falling time, output signals 2.0 ns Submit Documentation Feedback 9.0 0.5 ns ns 9.0 0.5 ns ns TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 223 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com HSU0 hsusb0_clk HSU1 HSU1 hsusb0_stp HSU3 HSU4 hsusb0_dir_&_nxt HSU5 HSU2 hsusb0_data[7:0] HSU2 Data_OUT HSU6 Data_IN 030-086 PRODUCT PREVIEW Figure 6-49. High-Speed USB – 12-bit Slave Mode 6.6.4.2 High-Speed Universal Serial Bus (USB) on Ports 1 and 2 – 12-bit Master Mode Table 6-99 and Table 6-100 assume testing over the recommended operating conditions (see Figure 6-50). Table 6-98. High-Speed USB Timing Conditions – 12-bit Master Mode TIMING CONDITION PARAMETER VALUE UNIT tR Input signal rise time 2 ns tF Input signal fall time 2 ns Output load capacitance 3 pF Input Conditions Output Conditions CLOAD Table 6-99. High-Speed USB Timing Requirements – 12-bit Master Mode (1) NO. PARAMETER 1.15 V MIN HSU3 UNIT MAX ts(DIRV-CLKH) Setup time, hsusbx_dir valid before hsusbx_clk rising edge 9.3 ns ts(NXTV-CLKH) Setup time, hsusbx_nxt valid before hsusbx_clk rising edge 9.3 ns th(CLKH-DIRIV) Hold time, hsusbx_dir valid after hsusbx_clk rising edge 0.2 ns th(CLKH-NXT/IV) Hold time, hsusbx_nxt valid after hsusbx_clk rising edge 0.2 ns HSU5 ts(DATAV-CLKH) Setup time, hsusbx_data[0:7] valid before hsusbx_clk rising edge 9.3 ns HSU6 th(CLKH-DATIV) Hold time, hsusbx_data[0:7] valid after hsusbx_clk rising edge 0.2 ns HSU4 (1) In hsusbx, x is equal to 1 or 2. Table 6-100. High-Speed USB Switching Characteristics – 12-bit Master Mode (1) N O. PARAMETER 1.15 V MIN HSU0 HSU1 HSU2 UNIT MAX fp(CLK) hsusbx_clk clock frequency 60 MHz tj(CLK) Jitter standard deviation (2), hsusbx_clk 200 ps td(clkL-STPV) Delay time, hsusbx_clk high to output hsusbx_stp valid 13 ns td(clkL-STPIV) Delay time, hsusbx_clk high to output hsusbx_stp invalid td(clkL-DV) Delay time, hsusbx_clk high to output hsusbx_data[0:7] valid td(clkL-DIV) Delay time, hsusbx_clk high to output hsusbx_data[0:7] invalid (1) (2) In hsusbx, x is equal to 1 or 2. The jitter probability density can be approximated by a Gaussian function. 224 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 2 ns 13 2 ns ns Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-100. High-Speed USB Switching Characteristics – 12-bit Master Mode (continued) N O. PARAMETER 1.15 V MIN UNIT MAX tR(do) Rise time, output signals 2 ns tF(do) Fall time, output signals 2 ns HSU0 hsusbx_clk HSU1 HSU1 hsusbx_stp HSU4 hsusbx_dir_&_nxt HSU5 HSU2 HSU2 HSU6 Data_OUT hsusbx_data[7:0] Data_IN 030-087 In hsusbx, x is equal to 1 or 2. Figure 6-50. High-Speed USB – 12-bit Master Mode 6.6.4.3 High-Speed Universal Serial Bus (USB) on Ports 1, 2, and 3 – 12-bit TLL Master Mode Table 6-102 and Table 6-103 assume testing over the recommended operating conditions (see Figure 6-51). Table 6-101. High-Speed USB Timing Conditions – 12-bit TLL Master Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2 ns tF Input signal fall time 2 ns Output load capacitance 3 pF Output Conditions CLOAD Table 6-102. High-Speed USB Timing Requirements – 12-bit TLL Master Mode (1) NO. PARAMETER 1.15 V MIN UNIT MAX HSU2 ts(STPV-CLKH) Setup time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge 6 ns HSU3 ts(CLKH-STPIV) Hold time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge 0 ns HSU4 ts(DATAV-CLKH) Setup time, hsusbx_tll_data[7:0] valid before hsusbx_tll_clk rising edge 6 ns HSU5 th(CLKH-DATIV) Hold time, hsusbx_tll_data[7:0] valid after hsusbx_tll_clk rising edge 0 ns (1) In hsusbx, x is equal to 1, 2, or 3. Table 6-103. High-Speed USB Switching Characteristics – 12-bit TLL Master Mode (1) NO. PARAMETER 1.15 V MIN HSU0 (1) fp(CLK) hsusbx_tll_clk clock frequency UNIT MAX 60 MHz In hsusbx, x is equal to 1, 2, or 3. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 225 PRODUCT PREVIEW HSU3 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-103. High-Speed USB Switching Characteristics – 12-bit TLL Master Mode (continued) NO. PARAMETER 1.15 V MIN HSU6 HSU7 PRODUCT PREVIEW (2) UNIT MAX tj(CLK) Jitter standard deviation (2), hsusbx_tll_clk td(CLKL-DIRV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid td(CLKL-DIRIV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid td(CLKL-NXTV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid td(CLKL-NXTIV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid td(CLKL-DV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[7:0] valid td(CLKL-DIV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[7:0] invalid tR(do) Rise time, output signals 2 ns tF(do) Fall time, output signals 2 ns 200 ps 9 ns 0 ns 9 0 ns ns 9 0 ns ns The jitter probability density can be approximated by a Gaussian function. HSU0 hsusbx_tll_clk HSU3 HSU2 hsusbx_tll_stp HSU6 HSU6 hsusbx_tll_dir_&_nxt HSU4 HSU7 HSU5 hsusbx_tll_data[7:0] HSU7 Data_IN Data_OUT 030-088 In hsusbx, x is equal to 1, 2, or 3. Figure 6-51. High-Speed USB – 12-bit TLL Master Mode 6.6.4.4 High-Speed Universal Serial Bus (USB) on Ports 1, 2, and 3 – 8-bit TLL Master Mode Table 6-105 and Table 6-106 assume testing over the recommended operating conditions (see Figure 6-52). Table 6-104. High-Speed USB Timing Conditions – 8-bit TLL Master Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2 ns tF Input signal fall time 2 ns Output load capacitance 3 pF Output Conditions CLOAD Table 6-105. High-Speed USB Timing Requirements – 8-bit TLL Master Mode (1) NO. PARAMETER 1.15 V MIN UNIT MAX HSU2 ts(STPV-CLKH) Setup time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge 6 ns HSU3 ts(CLKH-STPIV) Hold time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge 0 ns HSU4 ts(DATAV-CLKH) Setup time, hsusbx_tll_data[3:0] valid before hsusbx_tll_clk rising edge 3 ns (1) 226 In hsusbx, x is equal to 1, 2, or 3. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-105. High-Speed USB Timing Requirements – 8-bit TLL Master Mode (continued) NO. PARAMETER 1.15 V UNIT MIN HSU5 th(CLKH-DATIV) Hold time, hsusbx_tll_data[3:0] valid after hsusbx_tll_clk rising edge MAX –0.8 ns Table 6-106. High-Speed USB Switching Characteristics – 8-bit TLL Master Mode (1) PARAMETER 1.15 V MIN HSU0 UNIT MAX fp(CLK) hsusbx_tll_clk clock frequency 60 MHz tj(CLK) Jitter standard deviation (2), hsusbx_tll_clk 200 ps HSU1 tj(CLK) Duty cycle, hsusbx_tll_clk pulse duration (low and high) HSU6 td(CLKL-DIRV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid td(CLKL-DIRIV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid td(CLKL-NXTV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid 47.6% 52.4% 9 0 ns ns 9 0 ns td(CLKL-NXTIV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid HSU7 td(CLKL-DV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] valid HSU8 td(CLKL-DIV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] invalid tR(do) Rise time, output signals 2 ns tF(do) Fall time, output signals 2 ns (1) (2) PRODUCT PREVIEW NO. ns 4 0 ns ns In hsusbx, x is equal to 1, 2, or 3. The jitter probability density can be approximated by a Gaussian function. HSU0 HSU1 HSU1 hsusbx_tll_clk HSU3 HSU2 hsusbx_tll_stp HSU6 HSU6 hsusbx_tll_dir_&_nxt HSU5 HSU4 hsusbx_tll_data[3:0] Data_IN HSU5 HSU4 Data_IN_(n+1) HSU8 HSU7 Data_IN_(n+2) HSU7 Data_OUT Data_OUT_(n+1) 030-089 In hsusbx, x is equal to 1, 2, or 3. Figure 6-52. High-Speed USB – 8-bit TLL Master Mode Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 227 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 6.6.5 www.ti.com I2C Interface The multimaster I2C peripheral provides an interface between two or more devices via an I2C serial bus. The I2C controller supports the multimaster mode which allows more than one device capable of controlling the bus to be connected to it. Each I2C device is recognized by a unique address and can operate as either transmitter or receiver, according to the function of the device. In addition to being a transmitter or receiver, a device connected to the I2C bus can also be considered as master or slave when performing data transfers. This data transfer is carried out via two serial bidirectional wires: • An SDA data line • An SCL clock line The following sections illustrate the data transfer is in master or slave configuration with 7-bit addressing format. The I2C interface is compliant with Philips I2C specification version 2.1. It supports standard mode (up to 100K bits/s), fast mode (up to 400K bits/s) and high-speed mode (up to 3.4Mb/s) . PRODUCT PREVIEW 6.6.5.1 I2C Standard/Fast-Speed Mode Table 6-107. I2C Standard/Fast-Speed Mode Timings PARAMETER (1) NO. Standard Mode MIN MAX Fast Mode MIN 100 UNIT MAX fSCL Clock Frequency, i2cX_scl I1 tw(SCLH) Pulse Duration, i2cX_scl high 4 0.6 µs I2 tw(SCLL) Pulse Duration, i2cX_scl low 4.7 1.3 µs I3 tsu(SDAV-SCLH) Setup time, i2cX_sda valid before i2cX_scl active level 250 100 (2) (3) ns µs th(SCLH–SDAV) Hold time, i2cX_sda valid after i2cX_scl active level 0 tsu(SDAL-SCLH) Setup time, i2cX_scl high after i2cX_sda low (for a START (5) condition or a repeated START condition) 4.7 0.6 µs I6 th(SCLH–SDAH) Hold time, i2cX_sda low level after i2cX_scl high level (STOP condition) 4 0.6 µs I7 th(SCLH–RSTART) Hold time, i2cX_sda low level after i2cX_scl high level (for a repeated START condition) 4 0.6 µs I8 tw(SDAH) Pulse duration, i2cX_sda high between STOP and START conditions 4.7 1.3 µs tR(SCL) Rise time, i2cX_scl 1000 300 ns tF(SCL) Fall time, i2cX_scl 300 300 ns tR(SDA) Rise time, i2cX_sda 1000 300 ns tF(SDA) Fall time, i2cX_sda 300 300 ns CB Capacitive load for each bus line 400 400 pF (4) (5) 228 0.9 (4) I5 (3) 0 (3) kHz I4 (1) (2) 3.45 (4) 400 In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDAV-SCLH) ≥ 250 ns must then be met. This is automatically the case if the device does not stretch the low period of the i2cx_scl. If such a device does stretch the low period of the i2cx_scl, it must output the next data bit to the i2cx_sda line tr(SDA) max + tsu(SDAV-SCLH) = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the i2cx_scl line is released. The device provides (via the I2C bus) a hold time of at least 300 ns for the i2cx_sda signal (refer to the fall and rise time of i2cx_scl) to bridge the undefined region of the falling edge of i2cx_scl. The maximum th(SCLH-SDA) has only to be met if the device does not stretch the low period of the i2cx_scl signal. After this time, the first clock is generated. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 START REPEAT START START STOP i2cX_sda I2 I6 I1 I5 I3 I4 I8 I6 I7 i2cX_scl 030-093 PRODUCT PREVIEW Figure 6-53. I2C – Standard/Fast Mode Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 229 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 6.6.5.2 I2C High-Speed Mode Table 6-108. I2C HighSpeed Mode Timings (1) (2) NO. PARAMETER CB = 100 pF MAX MIN I1 fSCL Clock frequency, i2cX_scl tw(SCLH) Pulse duration, i2cX_scl high MAX CB = 400 pF MAX MIN 3.4 60 (3) MAX 1.7 MHz 120 (3) µs (3) µs PRODUCT PREVIEW I2 tw(SCLL) Pulse duration, i2cX_scl low I3 tsu(SDAV-SCLH) Setup time, i2cX_sda valid before i2cX_scl active level 10 I4 th(SCLH–SDAV) Hold time, i2cX_sda valid after i2cX_scl active level 0 (2) I5 tsu(SDAL-SCLH) Setup time, i2cX_scl high after i2cX_sda low (for a START (4) condition or a repeated START condition) 160 160 µs I6 th(SCLH–SDAH) Hold time, i2cX_sda low level after i2cX_scl high level (STOP condition) 160 160 µs I7 th(SCLH–RSTART) Hold time, i2cX_sda low level after i2cX_scl high level (for a repeated START condition) 160 160 ns tR(SCL) Rise time, i2cX_scl 40 80 ns tR(SCL) Rise time, i2cX_scl after a repeated START condition and after a bit acknowledge 80 160 ns tF(SCL) Fall time, i2cX_scl 40 80 ns tR(SDA) Rise time, i2cX_sda 80 160 ns tF(SDA) Fall time, i2cX_sda 80 160 ns (1) (2) (3) (4) 160 (3) UNIT 320 10 0 (2) 70 ns 150 µs In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only. The device provides (via the I2C bus) a hold time of at least 300 ns for the i2cx_sda signal (refer to the fall and rise time of i2cx_scl) to bridge the undefined region of the falling edge of i2cx_scl. HS-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. tw(SCLL) > 2 × tw(SCLH). After this time, the first clock is generated. START REPEAT STOP i2cX_sda I5 I6 I1 I2 I3 I4 I7 i2cX_scl 030-094 Figure 6-54. I2C – High-Speed Mode(1)(2)(3) (1) HS-mode master devices generate a serial clock signal with a high-to-low ratio of 1 to 2. tw(SCLL) > 2 x tw(SCLH). (2) In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only. (3) After this time, the first clock is generated. Table 6-109. Correspondence Standard vs. TI Timing References STANDARD-I2C TI-OMAP I1 230 S/F Mode HS Mode fSCL FSCL FSCLH tw(SCLH) THIGH THIGH I2 tw(SCLL) TLOW TLOW I3 tsu(SDAV-SCLH) TSU;DAT TSU;DAT I4 th(SCLH-SDAV) TSU;DAT TSU;DAT I5 tsu(SDAL-SCLH) TSU;STA TSU;STA I6 th(SCLH-SDAH) THD;STA THD;STA I7 th(SCLH-RSTART) TSU;STO TSU;STO TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-109. Correspondence Standard vs. TI Timing References (continued) STANDARD-I2C TI-OMAP S/F Mode I8 6.6.6 tw(SDAH) HS Mode TBUF HDQ / 1-Wire Interfaces This module is intended to work with both the HDQ and the 1-Wire protocols. The protocols use a single wire to communicate between the master and the slave. The protocols employ an asynchronous return to 1 mechanism where, after any command, the line is pulled high. 6.6.6.1 HDQ Protocol PRODUCT PREVIEW Table 6-110 and Table 6-111 assume testing over the recommended operating conditions (see Figure 6-55 through Figure 6-58). Table 6-110. HDQ Timing Requirements PARAMETER DESCRIPTION MIN tCYCD Bit window 253 tHW1 Reads 1 tHW0 Reads 0 tRSPS Command to host respond time (1) (1) MAX UNIT µs 68 180 Defined by software. Table 6-111. HDQ Switching Characteristics PARAMETER DESCRIPTION tB Break timing MIN TYP tBR Break recovery 63 tCYCH Bit window 253 tDW1 Sends1 (write) 1.3 tDW0 Sends0 (write) 101 MAX UNIT µs 193 tB tBR HDQ 030-095 Figure 6-55. HDQ Break (Reset) Timing tCYCH tHW0 tHW1 HDQ 030-096 Figure 6-56. HDQ Read Bit Timing (Data) Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 231 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com tCYCD tDW0 tDW1 HDQ 030-097 Figure 6-57. HDQ Write Bit Timing (Command/Address or Data) Command _byte_written Data_byte_received 0_(LSB ) Break 1 tRSPS 6 1 7_(MSB) 0_(LSB) 6 HDQ PRODUCT PREVIEW 030-098 Figure 6-58. HDQ Communication Timing 6.6.6.2 1-Wire Protocol Table 6-112 and Table 6-113 assume testing over the recommended operating conditions (see Figure 6-59 through Figure 6-61). Table 6-112. 1-Wire Timing Requirements PARAMETER DESCRIPTION tPDH Presence pulse delay high tPDL Presence pulse delay low tRDV + tREL Read bit-zero time MIN MAX UNIT 68 µs 68 – tPDH 102 Table 6-113. 1-Wire Switching Characteristics PARAMETER DESCRIPTION tRSTL Reset time low MIN TYP 484 tRSTH Reset time high 484 tSLOT Write bit cycle time 102 tLOW1 Write bit-one time 1.3 tLOW0 Write bit-zero time 101 tREC Recovery time 134 tLOWR Read bit strobe time 13 MAX UNIT µs tRSTH 1-WIRE tRTSL tPDH tPDL 030-099 Figure 6-59. 1-Wire Break (Reset) Timing 232 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 tSLOT_and_ tREC tRDV_and_ tREL tLOWR 1-WIRE 030-100 Figure 6-60. 1-Wire Read Bit Timing (Data) tSLOT_and_tREC tLOW0 1-WIRE 030-101 Figure 6-61. 1-Wire Write Bit Timing (Command/Address or Data) 6.6.7 UART IrDA Interface The IrDA module can operate in three different modes: • Slow infrared (SIR) (≤115.2 Kbits/s) • Medium infrared (MIR) (0.576 Mbits/s and 1.152 Mbits/s) • Fast infrared (FIR) (4 Mbits/s) For more information about this interface, see the UART/IrDA chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. Pulse duration 90% 90% 50% 50% 10% 10% tr tf 030-118 Figure 6-62. UART IrDA Pulse Parameters 6.6.7.1 IrDA—Receive Mode Table 6-114. UART IrDA—Signaling Rate and Pulse Duration—Receive Mode SIGNALING RATE ELECTRICAL PULSE DURATION MIN NOMINAL MAX UNIT SIR 2.4 Kbit/s 1.41 78.1 88.55 µs 9.6 Kbit/s 1.41 19.5 22.13 µs 19.2 Kbit/s 1.41 9.75 11.07 µs Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 233 PRODUCT PREVIEW tLOW1 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-114. UART IrDA—Signaling Rate and Pulse Duration—Receive Mode (continued) SIGNALING RATE ELECTRICAL PULSE DURATION UNIT MIN NOMINAL MAX 38.4 Kbit/s 1.41 4.87 5.96 µs 57.6 Kbit/s 1.41 3.25 4.34 µs 115.2 Kbit/s 1.41 1.62 2.23 µs 416 518.8 ns 208 258.4 ns MIR 0.576 Mbit/s 297.2 1.152 Mbit/s 149.6 FIR PRODUCT PREVIEW 4.0 Mbit/s (Single pulse) 67 125 164 ns 4.0 Mbit/s (Double pulse) 190 250 289 ns Table 6-115. UART IrDA—Rise and Fall Time—Receive Mode PARAMETER MAX UNIT tR Rising time, uart3_rx_irrx 200 ns tF Falling time, uart3_rx_irrx 200 ns 6.6.7.2 IrDA—Transmit Mode Table 6-116. UART IrDA—Signaling Rate and Pulse Duration—Transmit Mode SIGNALING RATE ELECTRICAL PULSE DURATION MIN NOMINAL UNIT MAX SIR 2.4 Kbit/s 78.1 78.1 78.1 µs 9.6 Kbit/s 19.5 19.5 19.5 µs 19.2 Kbit/s 9.75 9.75 9.75 µs 38.4 Kbit/s 4.87 4.87 4.87 µs 57.6 Kbit/s 3.25 3.25 3.25 µs 115.2 Kbit/s 1.62 1.62 1.62 µs 416 419 ns 208 211 ns MIR 0.576 Mbit/s 414 1.152 Mbit/s 206 FIR 234 4.0 Mbit/s (Single pulse) 123 125 128 ns 4.0 Mbit/s (Double pulse) 248 250 253 ns TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 6.7 Removable Media Interfaces 6.7.1 High-Speed Multimedia Memory Card (MMC) and Secure Digital IO Card (SDIO) Timing There are three MMC interfaces on the OMAP3515/03: • MMC/SD/SDIO Interface 1: – 1.8 V/3 V support – 8 bits • MMC/SD/SDIO Interface 2: – 1.8 V support – 8 bits – 4 bits with external transceiver allowing to support 3 V peripherals. Transceiver direction control signals are multiplexed with the upper four data bits. • MMC/SD/SDIO Interface 3: – 1.8 V support – 8 bits 6.7.1.1 MMC/SD/SDIO in SD Identification Mode Table 6-118 and Table 6-119 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-117. MMC/SD/SDIO Timing Conditions – SD Identification Mode TIMING CONDITION PARAMETER VALUE UNIT tR Input signal rise time 10 ns tF Input signal fall time 10 ns Output load capacitance 40 pF SD Identification Mode Input Conditions Output Conditions CLOAD Table 6-118. MMC/SD/SDIO Timing Requirements – SD Identification Mode (1) (2) (3) NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX SD Identification Mode MMC/SD/SDIO Interface 1 (1.8 V IO) HSSD3/SD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 1198.4 1198.4 ns HSSD4/SD4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 1249.2 1249.2 ns MMC/SD/SDIO Interface 1 (3.0 V IO) HSSD3/SD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 1198.4 1198.4 ns HSSD4/SD4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 1249.2 1249.2 ns MMC/SD/SDIO Interface 2 (1) (2) (3) Timing parameters are referred to output clock specified in Table 6-119. The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-119. Corresponding figures showing timing parameters are common with other interface modes. (See SD and HS SD modes). Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 235 PRODUCT PREVIEW The MMC/SDIO host controller provides an interface to high-speed and standard MMC, SD memory cards, or SDIO cards. The application interface is responsible for managing transaction semantics. The MMC/SDIO host controller deals with MMC/SDIO protocol at transmission level, packing data, adding CRC, start/end bit, and checking for syntactical correctness. OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-118. MMC/SD/SDIO Timing Requirements – SD Identification Mode (continued) NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX HSSD3/SD3 tsu(CMDV-CLKIH) Setup time, mmc2_cmd valid before mmc2_clk rising clock edge 1198.4 1198.4 ns HSSD4/SD4 tsu(CLKIH-CMDIV) Hold time, mmc2_cmd valid after mmc2_clk rising clock edge 1249.2 1249.2 ns MMC/SD/SDIO Interface 3 HSSD3/SD3 tsu(CMDV-CLKIH) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 1198.4 1198.4 ns HSSD4/SD4 tsu(CLKIH-CMDIV) Hold time, mmc3_cmd valid after mmc3_clk rising clock edge 1249.2 1249.2 ns PRODUCT PREVIEW Table 6-119. MMC/SD/SDIO Switching Characteristics – SD Identification Mode (1) NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX SD Identification Mode HSSD1/SD1 tc(clk) Cycle time (2), output clk period 2500 2500 (3) *PO (4) ns (3) (4) ns Y (5)*PO (4) ns HSSD2/SD2 tW(clkH) Typical pulse duration, output clk high X HSSD2/SD2 tW(clkL) Typical pulse duration, output clk low Y (5)*PO (4) X *PO tdc(clk) Duty cycle error, output clk 125 125 ns tj(clk) Jitter standard deviation (6), output clk 200 200 ps MMC/SD/SDIO Interface 1 (1.8 V IO) HSSD5/SD5 tc(clk) Rise time, output clk 10 10 ns tW(clkH) Fall time, output clk 10 10 ns tW(clkL) Rise time, output data 10 10 ns tdc(clk) Fall time, output data 10 10 ns td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd transition 2492.7 ns 6.3 2492.7 6.3 MMC/SD/SDIO Interface 1 (3.0 V IO) HSSD5/SD5 tc(clk) Rise time, output clk 10 0 ns tW(clkH) Fall time, output clk 10 0 ns tW(clkL) Rise time, output data 10 10 ns tdc(clk) Fall time, output data 10 10 ns td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd transition 2492.7 ns 6.3 2492.7 6.3 MMC/SD/SDIO Interface 2 HSSD5/SD5 tc(clk) Rise time, output clk 10 10 ns tW(clkH) Fall time, output clk 10 10 ns tW(clkL) Rise time, output data 10 10 ns tdc(clk) Fall time, output data 10 10 ns td(CLKOH-CMD) Delay time, mmc2_clk rising clock edge to mmc2_cmd transition 2492.7 ns 6.3 2492.7 6.3 MMC/SD/SDIO Interface 3 (1) (2) (3) (4) (5) (6) 236 tc(clk) Rise time, output clk 10 10 ns tW(clkH) Fall time, output clk 10 10 ns tW(clkL) Rise time, output data 10 10 ns Corresponding figures showing timing parameters are common with other interface modes (see SD and HS SD modes). Related with the output clk maximum and minimum frequencies programmable in I/F module. The X parameter is defined as shown in Table 6-120. PO = output clk period in ns. The Y parameter is defined as shown in Table 6-121. The jitter probability density can be approximated by a Gaussian function. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-119. MMC/SD/SDIO Switching Characteristics – SD Identification Mode (continued) NO. PARAMETER 1.15 V MIN HSSD5/SD5 tdc(clk) Fall time, output data td(CLKOH-CMD) Delay time, mmc3_clk rising clock edge to mmc3_cmd transition 1.0 V MAX MIN 10 6.3 2492.7 UNIT MAX 6.3 10 ns 2492.7 ns CLKD X 1 or Even 0.5 Odd (trunk[CLKD/2]+1)/CLKD Table 6-121. Y Parameter CLKD Y 1 or Even 0.5 Odd (trunk[CLKD/2])/CLKD For details about clock division factor CLKD, see the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. 6.7.1.2 MMC/SD/SDIO in High-Speed MMC Mode Table 6-123 and Table 6-124 assume testing over the recommended operating conditions and electrical characteristic conditions (see Figure 6-63 and Figure 6-64). Table 6-122. MMC/SD/SDIO Timing Conditions – High-Speed MMC Mode TIMING CONDITION PARAMETER VALUE UNIT High-Speed MMC Mode Input Conditions tR Input signal rise time 3 ns tF Input signal fall time 3 ns Output load capacitance 30 pF Output Conditions CLOAD Table 6-123. MMC/SD/SDIO Timing Requirements – High-Speed MMC Mode (1) (2) (3) (4) NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX High-Speed MMC Mode MMC/SD/SDIO Interface 1 (1.8 V IO) MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 5.6 26 ns MMC4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 2.3 1.9 ns MMC7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk rising clock edge 5.6 26 ns MMC8 tsu(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk rising clock edge 2.3 1.9 ns MMC/SD/SDIO Interface 1 (3.0 V IO) (1) (2) (3) (4) Timing parameters are referred to output clock specified in Table 6-124. The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-124. Corresponding figures showing timing parameters are common with Standard MMC mode (See Figure 6-63 and Figure 6-64) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 237 PRODUCT PREVIEW Table 6-120. X Parameter OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-123. MMC/SD/SDIO Timing Requirements – High-Speed MMC Mode (continued) NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 5.6 26 ns MMC4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 2.3 1.9 ns MMC7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk rising clock edge 5.6 26 ns MMC8 tsu(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk rising clock edge 2.3 1.9 ns MMC3 tsu(CMDV-CLKIH) Setup time, mmc2_cmd valid before mmc2_clk rising clock edge 5.6 26 ns MMC4 tsu(CLKIH-CMDIV) Hold time, mmc2_cmd valid after mmc2_clk rising clock edge 2.3 1.9 ns MMC7 tsu(DATxV-CLKIH) Setup time, mmc2_datx valid before mmc2_clk rising clock edge 5.6 26 ns MMC8 tsu(CLKIH-DATxIV) Hold time, mmc2_datx valid after mmc2_clk rising clock edge 2.3 1.9 ns MMC3 tsu(CMDV-CLKIH) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 5.6 26 ns MMC4 tsu(CLKIH-CMDIV) Hold time, mmc3_cmd valid after mmc3_clk rising clock edge 2.3 1.9 ns MMC7 tsu(DATxV-CLKIH) Setup time, mmc3_datx valid before mmc3_clk rising clock edge 5.6 26 ns MMC8 tsu(CLKIH-DATxIV) Hold time, mmc3_datx valid after mmc3_clk rising clock edge 2.3 1.9 ns MMC/SD/SDIO Interface 2 PRODUCT PREVIEW MMC/SD/SDIO Interface 3 Table 6-124. MMC/SD/SDIO Switching Characteristics – High-Speed MMC Mode (1) N O. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX High-Speed MMC Mode MMC1 tc(clk) Cycle time (2), output clk period MMC2 tW(clkH) Typical pulse duration, output clk high MMC2 tW(clkL) Typical pulse duration, output clk low tdc(clk) Duty cycle error, output clk tj(clk) Jitter standard deviation (6), output clk 20.8 41.7 X (3)*PO (4) X (3)*PO (4) Y (5) *PO (4) (5) Y *PO ns ns (4) ns 1041.7 2083.3 ps 200 200 ps MMC/SD/SDIO Interface 1 (1.8 V IO) tc(clk) Rise time, output clk 3 3 ns tW(clkH) Fall time, output clk 3 3 ns tW(clkL) Rise time, output data 3 3 ns tdc(clk) Fall time, output data 3 ns MMC5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd transition 3.7 14.1 3 4.1 34.5 ns MMC6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx transition 3.7 14.1 4.1 34.5 ns MMC/SD/SDIO Interface 1 (3.0 V IO) (1) (2) (3) (4) (5) (6) 238 In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. Related with the output clk maximum and minimum frequencies programmable in I/F module. The X parameter is defined as shown in Table 6-125. PO = output clk period in ns. The Y parameter is defined as shown in Table 6-126. The jitter probability density can be approximated by a Gaussian function. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-124. MMC/SD/SDIO Switching Characteristics – High-Speed MMC Mode (continued) N O. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX tc(clk) Rise time, output clk 3 3 ns tW(clkH) Fall time, output clk 3 3 ns tW(clkL) Rise time, output data 3 3 ns tdc(clk) Fall time, output data 3 3 ns MMC5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd transition 3.7 14.1 4.1 34.5 ns MMC6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx transition 3.7 14.1 4.1 34.5 ns tc(clk) Rise time, output clk 3 3 ns tW(clkH) Fall time, output clk 3 3 ns tW(clkL) Rise time, output data 3 3 ns tdc(clk) Fall time, output data 3 3 ns MMC5 td(CLKOH-CMD) Delay time, mmc2_clk rising clock edge to mmc2_cmd transition 3.7 14.1 4.1 34.5 ns MMC6 td(CLKOH-DATx) Delay time, mmc2_clk rising clock edge to mmc2_datx transition 3.7 16.5 4.1 36.9 ns PRODUCT PREVIEW MMC/SD/SDIO Interface 2 MMC/SD/SDIO Interface 3 tc(clk) Rise time, output clk 3 3 ns tW(clkH) Fall time, output clk 3 3 ns tW(clkL) Rise time, output data 3 3 ns tdc(clk) Fall time, output data 3 3 ns MMC5 td(CLKOH-CMD) Delay time, mmc3_clk rising clock edge to mmc3_cmd transition 3.7 14.1 4.1 34.5 ns MMC6 td(CLKOH-DATx) Delay time, mmc3_clk rising clock edge to mmc3_datx transition 3.7 14.1 4.1 34.5 ns Table 6-125. X Parameter CLKD X 1 or Even 0.5 Odd (trunk[CLKD/2]+1)/CLKD Table 6-126. Y Parameter CLKD Y 1 or Even 0.5 Odd (trunk[CLKD/2])/CLKD For details about clock division factor CLKD, see the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. 6.7.1.3 MMC/SD/SDIO in Standard MMC Mode and MMC Identification Mode Table 6-128 and Table 6-129 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-127. MMC/SD/SDIO Timing Conditions – Standard MMC Mode and MMC Identification Mode TIMING CONDITION PARAMETER VALUE UNIT Standard MMC Mode and MMC Identification Mode Input Conditions Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 239 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-127. MMC/SD/SDIO Timing Conditions – Standard MMC Mode and MMC Identification Mode (continued) VALUE UNIT tR TIMING CONDITION PARAMETER Input signal rise time 10 ns tF Input signal fall time 10 ns Output load capacitance 30 pF Output Conditions CLOAD PRODUCT PREVIEW 240 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-128. MMC/SD/SDIO Timing Requirements – Standard MMC Mode and MMC Identification Mode (1) (2) NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX Standard MMC Mode and MMC Identification Mode MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 13.6 65.7 ns MMC4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 8.9 8.9 ns MMC7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk rising clock edge 13.6 65.7 ns MMC8 tsu(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk rising clock edge 8.9 8.9 ns PRODUCT PREVIEW MMC/SD/SDIO Interface 1 (1.8 V IO) MMC/SD/SDIO Interface 1 (3.0 V IO) MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 13.6 65.7 ns MMC4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 8.9 8.9 ns MMC7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk rising clock edge 13.6 65.7 ns MMC8 tsu(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk rising clock edge 8.9 8.9 ns MMC/SD/SDIO Interface 2 MMC3 tsu(CMDV-CLKIH) Setup time, mmc2_cmd valid before mmc2_clk rising clock edge 13.6 65.7 ns MMC4 tsu(CLKIH-CMDIV) Hold time, mmc2_cmd valid after mmc2_clk rising clock edge 8.9 8.9 ns MMC7 tsu(DATxV-CLKIH) Setup time, mmc2_datx valid before mmc2_clk rising clock edge 13.6 65.7 ns MMC8 tsu(CLKIH-DATxIV) Hold time, mmc2_datx valid after mmc2_clk rising clock edge 8.9 8.9 ns MMC/SD/SDIO Interface 3 MMC3 tsu(CMDV-CLKIH) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 13.6 65.7 ns MMC4 tsu(CLKIH-CMDIV) Hold time, mmc3_cmd valid after mmc3_clk rising clock edge 8.9 8.9 ns MMC7 tsu(DATxV-CLKIH) Setup time, mmc3_datx valid before mmc3_clk rising clock edge 13.6 65.7 ns MMC8 tsu(CLKIH-DATxIV) Hold time, mmc3_datx valid after mmc3_clk rising clock edge 8.9 8.9 ns (1) (2) Timing parameters are referred to output clock specified in Table 6-129. The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-129. Table 6-129. MMC/SD/SDIO Switching Characteristics – Standard MMC Mode and MMC Identification Mode NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX MMC Identification Mode MMC1 tc(clk) Cycle time (1), output clk period 2500 MMC2 tW(clkH) Typical pulse duration, output clk high MMC2 tW(clkL) Typical pulse duration, output clk low (1) (2) (3) X (2) *PO 2500 (3) Y*PO (3) (2) X *PO ns (3) Y*PO (3) ns ns Related with the output clk maximum and minimum frequencies programmable in I/F module. The X parameter is defined as shown in Table 6-130. PO = output clk period in ns. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 241 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-129. MMC/SD/SDIO Switching Characteristics – Standard MMC Mode and MMC Identification Mode (continued) NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX tdc(clk) Duty cycle error, output clk 125 125 ns tj(clk) Jitter standard deviation (4), output clk 200 200 ps Standard MMC Mode MMC1 tc(clk) Cycle time (1), output clk period MMC2 tW(clkH) Typical pulse duration, output clk high MMC2 tW(clkL) Typical pulse duration, output clk low tdc(clk) Duty cycle error, output clk tj(clk) Jitter standard deviation (4), output clk 52.1 104.2 ns X (2)*PO (3) X (2)*PO (3) ns Y*PO (3) Y*PO (3) ns 2604.2 5208.3 ps 200 200 ps PRODUCT PREVIEW MMC/SD/SDIO Interface 1 (1.8 V IO) tc(clk) Rise time, output clk 10 10 ns tW(clkH) Fall time, output clk 10 10 ns tW(clkL) Rise time, output data 10 10 ns tdc(clk) Fall time, output data 10 ns MMC5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd transition 4.3 47.8 10 4.3 99.9 ns MMC6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx transition 4.3 47.8 4.3 99.9 ns MMC/SD/SDIO Interface 1 (3.0 V IO) tc(clk) Rise time, output clk 10 10 ns tW(clkH) Fall time, output clk 10 10 ns tW(clkL) Rise time, output data 10 10 ns tdc(clk) Fall time, output data 10 10 ns MMC5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd transition 4.3 47.8 4.3 99.9 ns MMC6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx transition 4.3 47.8 4.3 99.9 ns MMC/SD/SDIO Interface 2 tc(clk) Rise time, output clk 10 10 ns tW(clkH) Fall time, output clk 10 10 ns tW(clkL) Rise time, output data 10 10 ns tdc(clk) Fall time, output data 10 10 ns MMC5 td(CLKOH-CMD) Delay time, mmc2_clk rising clock edge to mmc2_cmd transition 4.3 47.8 4.3 99.9 ns MMC6 td(CLKOH-DATx) Delay time, mmc2_clk rising clock edge to mmc2_datx transition 4.3 47.8 4.3 99.9 ns MMC/SD/SDIO Interface 3 tc(clk) Rise time, output clk 10 10 ns tW(clkH) Fall time, output clk 10 10 ns tW(clkL) Rise time, output data 10 10 ns tdc(clk) Fall time, output data 10 ns MMC5 td(CLKOH-CMD) Delay time, mmc3_clk rising clock edge to mmc3_cmd transition 4.3 47.8 4.3 99.9 ns MMC6 td(CLKOH-DATx) Delay time, mmc3_clk rising clock edge to mmc3_datx transition 4.3 47.8 4.3 99.9 ns (4) The jitter probability density can be approximated by a Gaussian function. 242 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 10 Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-130. X Parameter CLKD X 1 or Even 0.5 Odd (trunk[CLKD/2]+1)/CLKD Y 1 or Even 0.5 Odd (trunk[CLKD/2])/CLKD For details about clock division factor CLKD, see the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. MMC1 MMC2 mmcx_clk MMC3 MMC4 mmcx_cmd MMC7 MMC8 mmcx_dat[3:0] 030-104 In mmcx, x is equal to 1, 2, or 3. Figure 6-63. MMC/SD/SDIO – High-Speed and Standard MMC Modes – Data/Command Receive MMC1 MMC2 mmcx_clk MMC5 MMC5 mmcx_cmd MMC6 MMC6 mmcx_dat[3:0] 030-105 In mmcx, x is equal to 1, 2, or 3. Figure 6-64. MMC/SD/SDIO – High-Speed and Standard MMC Modes – Data/Command Transmit 6.7.1.4 MMC/SD/SDIO in High-Speed SD Mode Table 6-133 and Table 6-134 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-132. MMC/SD/SDIO Timing Conditions – High-Speed SD Mode TIMING CONDITION PARAMETER VALUE UNIT High-Speed SD Mode Input Conditions tR Input signal rise time 3 ns tF Input signal fall time 3 ns Output load capacitance 40 pF Output Conditions CLOAD Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 243 PRODUCT PREVIEW Table 6-131. Y Parameter CLKD OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-133. MMC/SD/SDIO Timing Requirements – High-Speed SD Mode (1) (2) (3) NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX High-Speed SD Mode MMC/SD/SDIO Interface 1 (1.8 V IO) PRODUCT PREVIEW HSSD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 5.6 26 ns HSSD4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 2.3 1.9 ns HSSD7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk rising clock edge 5.6 26 ns HSSD8 tsu(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk rising clock edge 2.3 1.9 ns MMC/SD/SDIO Interface 1 (3.0 V IO) HSSD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 5.6 26 ns HSSD4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 2.3 1.9 ns HSSD7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk rising clock edge 5.6 26 ns HSSD8 tsu(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk rising clock edge 2.3 1.9 ns MMC/SD/SDIO Interface 2 HSSD3 tsu(CMDV-CLKIH) Setup time, mmc2_cmd valid before mmc2_clk rising clock edge 5.6 26 ns HSSD4 tsu(CLKIH-CMDIV) Hold time, mmc2_cmd valid after mmc2_clk rising clock edge 2.3 1.9 ns HSSD7 tsu(DATxV-CLKIH) Setup time, mmc2_datx valid before mmc2_clk rising clock edge 5.6 26 ns HSSD8 tsu(CLKIH-DATxIV) Hold time, mmc2_datx valid after mmc2_clk rising clock edge 2.3 1.9 ns MMC/SD/SDIO Interface 3 HSSD3 tsu(CMDV-CLKIH) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 5.6 26 ns HSSD4 tsu(CLKIH-CMDIV) Hold time, mmc3_cmd valid after mmc3_clk rising clock edge 2.3 1.9 ns HSSD7 tsu(DATxV-CLKIH) Setup time, mmc3_datx valid before mmc3_clk rising clock edge 5.6 26 ns HSSD8 tsu(CLKIH-DATxIV) Hold time, mmc3_datx valid after mmc3_clk rising clock edge 2.3 1.9 ns (1) (2) (3) Timing Parameters are referred to output clock specified in Table 6-134. The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-134. In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. Table 6-134. MMC/SD/SDIO Switching Characteristics – High-Speed SD Mode NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX High-Speed SD Mode HSSD1 tc(clk) Cycle time (1), output clk period 20.8 41.7 ns HSSD2 tW(clkH) Typical pulse duration, output clk high X (2)*PO (3) X (2)*PO (3) ns HSSD2 tW(clkL) Typical pulse duration, output clk low Y (4)*PO (3) Y (4)*PO (3) ns (1) (2) (3) (4) 244 Related with the output clk maximum and minimum frequencies programmable in I/F module. The X parameter is defined as shown in Table 6-135. PO = output clk period in ns. The Y parameter is defined as shown in Table 6-136. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-134. MMC/SD/SDIO Switching Characteristics – High-Speed SD Mode (continued) NO. PARAMETER 1.15 V MIN tdc(clk) tj(clk) Duty cycle error, output clk Jitter standard deviation (5) , output clk 1.0 V MAX MIN UNIT MAX 1041.7 2083.3 ps 200 200 ps tc(clk) Rise time, output clk 3 3 ns tW(clkH) Fall time, output clk 3 3 ns tW(clkL) Rise time, output data 3 3 ns tdc(clk) Fall time, output data 3 3 ns HSSD5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd transition 3.7 14.1 4.1 34.5 ns HSSD6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx transition 3.7 14.1 4.1 34.5 ns PRODUCT PREVIEW MMC/SD/SDIO Interface 1 (1.8 V IO) MMC/SD/SDIO Interface 1 (3.0 V IO) tc(clk) Rise time, output clk 3 3 ns tW(clkH) Fall time, output clk 3 3 ns tW(clkL) Rise time, output data 3 3 ns tdc(clk) Fall time, output data 3 ns HSSD5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd transition 3.7 14.1 3 4.1 34.5 ns HSSD6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx transition 3.7 14.1 4.1 34.5 ns MMC/SD/SDIO Interface 2 tc(clk) Rise time, output clk 3 3 ns tW(clkH) Fall time, output clk 3 3 ns tW(clkL) Rise time, output data 3 3 ns tdc(clk) Fall time, output data 3 3 ns HSSD5 td(CLKOH-CMD) Delay time, mmc2_clk rising clock edge to mmc2_cmd transition 3.7 14.1 4.1 34.5 ns HSSD6 td(CLKOH-DATx) Delay time, mmc2_clk rising clock edge to mmc2_datx transition 3.7 14.1 4.1 34.5 ns MMC/SD/SDIO Interface 3 tc(clk) Rise time, output clk 3 3 ns tW(clkH) Fall time, output clk 3 3 ns tW(clkL) Rise time, output data 3 3 ns tdc(clk) Fall time, output data 3 3 ns HSSD5 td(CLKOH-CMD) Delay time, mmc3_clk rising clock edge to mmc3_cmd transition 3.7 14.1 4.1 34.5 ns HSSD6 td(CLKOH-DATx) Delay time, mmc3_clk rising clock edge to mmc3_datx transition 3.7 14.1 4.1 34.5 ns (5) The jitter probability density can be approximated by a Gaussian function. Table 6-135. X Parameters CLKD X 1 or Even 0.5 Odd (trunk[CLKD/2]+1)/CLKD Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 245 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-136. Y Parameters CLKD Y 1 or Even 0.5 Odd (trunk[CLKD/2])/CLKD For details about clock division factor CLKD, see the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. HSSD1 HSSD2 mmcx_clk HSSD3 HSSD4 mmcx_cmd PRODUCT PREVIEW HSSD7 HSSD8 mmcx_dat[3:0] 030-106 In mmcx, x is equal to 1, 2, or 3. Figure 6-65. MMC/SD/SDIO – High-Speed SD Mode – Data/Command Receive HSSD1 HSSD2 mmcx_clk HSSD5 HSSD5 mmcx_cmd HSSD6 HSSD6 mmcx_dat[3:0] 030-107 In mmcx, x is equal to 1, 2, or 3. Figure 6-66. MMC/SD/SDIO – High-Speed SD Mode – Data/Command Transmit 6.7.1.5 MMC/SD/SDIO in Standard SD Mode Table 6-138 and Table 6-139 assume testing over the recommended operating conditions and electrical characteristic conditions (see Figure 6-67). Table 6-137. MMC/SD/SDIO Timing Conditions – Standard SD Mode TIMING CONDITION PARAMETER VALUE UNIT Standard SD Mode Input Conditions tR Input signal rise time 10 ns tF Input signal fall time 10 ns Output load capacitance 40 pF Output Conditions CLOAD 246 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-138. MMC/SD/SDIO Timing Requirements – Standard SD Mode (1) (2) (3) NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX Standard SD Mode MMC/SD/SDIO Interface 1 (1.8 V IO) SD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 6.2 47.7 ns SD4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 19.4 19.2 ns SD7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk rising clock edge 6.2 47.7 ns SD8 tsu(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk rising clock edge 19.4 19.2 ns SD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 6.2 47.7 ns SD4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 19.4 19.2 ns SD7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk rising clock edge 6.2 47.7 ns SD8 tsu(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk rising clock edge 19.4 19.2 ns PRODUCT PREVIEW MMC/SD/SDIO Interface 1 (3.0 V IO) MMC/SD/SDIO Interface 2 SD3 tsu(CMDV-CLKIH) Setup time, mmc2_cmd valid before mmc2_clk rising clock edge 6.2 47.7 ns SD4 tsu(CLKIH-CMDIV) Hold time, mmc2_cmd valid after mmc2_clk rising clock edge 19.4 19.2 ns SD7 tsu(DATxV-CLKIH) Setup time, mmc2_datx valid before mmc2_clk rising clock edge 6.2 47.7 ns SD8 tsu(CLKIH-DATxIV) Hold time, mmc2_datx valid after mmc2_clk rising clock edge 19.4 19.2 ns MMC/SD/SDIO Interface 3 SD3 tsu(CMDV-CLKIH) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 6.2 47.7 ns SD4 tsu(CLKIH-CMDIV) Hold time, mmc3_cmd valid after mmc3_clk rising clock edge 19.4 19.2 ns SD7 tsu(DATxV-CLKIH) Setup time, mmc3_datx valid before mmc3_clk rising clock edge 6.2 47.7 ns SD8 tsu(CLKIH-DATxIV) Hold time, mmc3_datx valid after mmc3_clk rising clock edge 19.4 19.2 ns (1) (2) (3) Timing parameters are referred to output clock specified in Table 6-139. The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-139. In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. Table 6-139. MMC/SD/SDIO Switching Characteristics – Standard SD Mode NO. PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX Standard SD Mode SD1 tc(clk) Cycle time (1), output clk period 41.7 83.3 ns SD2 tW(clkH) Typical pulse duration, output clk high X (2)*PO (3) X (2)*PO (3) ns SD2 tW(clkL) Typical pulse duration, output clk low Y (4)*PO (3) Y (4)*PO (3) tdc(clk) Duty cycle error, output clk (1) (2) (3) (4) 2083.3 ns 4166.7 ps Related with the output clk maximum and minimum frequencies programmable in I/F module. The X parameter is defined as shown in Table 6-140. PO = output clk period in ns. The Y parameter is defined as shown in Table 6-141. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 247 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-139. MMC/SD/SDIO Switching Characteristics – Standard SD Mode (continued) NO. PARAMETER 1.15 V MIN tj(clk) Jitter standard deviation (5), output clk 1.0 V MAX MIN UNIT MAX 200 200 ps MMC/SD/SDIO Interface 1 (1.8 V IO) tc(clk) Rise time, output clk 10 10 ns tW(clkH) Fall time, output clk 10 10 ns tW(clkL) Rise time, output data 10 10 ns tdc(clk) Fall time, output data 10 10 ns SD5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd transition 6.1 35.5 6.3 77 ns SD6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx transition 6.1 35.5 6.3 77 ns PRODUCT PREVIEW MMC/SD/SDIO Interface 1 (3.0 V IO) tc(clk) Rise time, output clk 10 10 ns tW(clkH) Fall time, output clk 10 10 ns tW(clkL) Rise time, output data 10 10 ns tdc(clk) Fall time, output data 10 10 ns SD5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd transition 6.1 35.5 6.3 77 ns SD6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx transition 6.1 35.5 6.3 77 ns MMC/SD/SDIO Interface 2 tc(clk) Rise time, output clk 10 10 ns tW(clkH) Fall time, output clk 10 10 ns tW(clkL) Rise time, output data 10 10 ns tdc(clk) Fall time, output data 10 10 ns SD5 td(CLKOH-CMD) Delay time, mmc2_clk rising clock edge to mmc2_cmd transition 6.1 35.5 6.3 77 ns SD6 td(CLKOH-DATx) Delay time, mmc2_clk rising clock edge to mmc2_datx transition 6.1 35.5 6.3 77 ns MMC/SD/SDIO Interface 3 tc(clk) Rise time, output clk 10 10 ns tW(clkH) Fall time, output clk 10 10 ns tW(clkL) Rise time, output data 10 10 ns tdc(clk) Fall time, output data 10 ns SD5 td(CLKOH-CMD) Delay time, mmc3_clk rising clock edge to mmc3_cmd transition 6.1 35.5 6.3 77 ns SD6 td(CLKOH-DATx) Delay time, mmc3_clk rising clock edge to mmc3_datx transition 6.1 35.5 6.3 77 ns (5) 10 The jitter probability density can be approximated by a Gaussian function. Table 6-140. X Parameter CLKD X 1 or Even 0.5 Odd (trunk[CLKD/2]+1)/CLKD Table 6-141. Y Parameter CLKD Y 1 or Even 0.5 Odd (trunk[CLKD/2])/CLKD 248 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 For details about clock division factor CLKD, see the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. SD1 SD2 mmcx_clk SD3 SD4 mmcx_cmd SD7 SD8 mmcx_dat[3:0] 030-108 Figure 6-67. MMC/SD/SDIO – Standard SD Mode – Data/Command Receive SD1 SD2 mmcx_clk SD5 SD5 mmcx_cmd SD6 SD6 mmcx_dat[3:0] 030-109 In mmcx, x is equal to 1, 2, or 3. Figure 6-68. MMC/SD/SDIO – Standard SD Mode – Data/Command Transmit Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 249 PRODUCT PREVIEW In mmcx, x is equal to 1, 2, or 3. OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 6.8 Test Interfaces The emulation and trace interfaces allow tracing activities of the following CPUs: • ARM1136JF-STM through an Embedded Trace Macro-cell (ETM11) dedicated to enable real-time trace of the ARM subsystem operations and a Serial Debug Trace Interface (SDTI) All processors can be emulated via JTAG ports. 6.8.1 Embedded Trace Macro Interface (ETM) Table 6-142 assumes testing over the recommended operating conditions (see Figure 6-69). Table 6-142. Embedded Trace Macro Interface Switching Characteristics (1) NO. PARAMETER 1.15 V MIN PRODUCT PREVIEW f 1/tc(CLK) Frequency, etk_clk UNIT MAX 166 (2) ETM0 tc(CLK) Cycle time ETM1 tW(CLK) Clock pulse width, etk_clk 2.7 ETM2 td(CLK-CTL) Delay time, etk_clk clock edge to etk_ctl transition –0.5 0.5 ns ETM3 td(CLK-D) Delay time, etk_clk clock high to etk_d[15:0] transition –0.5 0.5 ns (1) (2) , etk_clk MHz 6 ns ns The capacitive load is equivalent to 25 pF. Cycle time is given by considering a jitter of 5%. ETM0 ETM1 etk_clk ETM2 ETM2 etk_ctl ETM3 ETM3 etk_d[15:0] 030-110 Figure 6-69. Embedded Trace Macro Interface 6.8.2 System Debug Trace Interface (SDTI) The system debug trace interface (SDTI) module provides real-time software tracing functionality to the OMAP3515/03 device. The trace interface has four trace data pins and a trace clock pin. This interface is a dual-edge interface: the data are available on rising and falling edges of sdti_clk but can be also configured in single edge mode where data are available on falling edge of sdti_clk. Serial interface operates in clock stop regime: serial clock is not free running, when there is no trace data there is no trace clock. 6.8.2.1 System Debug Trace Interface in Dual-Edge Mode Table 6-144 assumes testing over the recommended operating conditions and electrical characteristic conditions (see Figure 6-70). Table 6-143. System Debug Trace Interface Timing Conditions – Dual-Edge Mode TIMING CONDITION PARAMETER VALUE UNIT 25 pF Output Conditions CLOAD 250 Output load capacitance TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-144. System Debug Trace Interface Switching Characteristics – Dual-Edge Mode PARAMETER 1.15 V MIN SD1 tc(CLK) Cycle time, sdti_clk period SD2 tw(CLK) Typical pulse duration, sdti_clk high or low tdc(CLK) Duty cycle error, sdti_clk tR(CLK) Rise time, sdti_clk tF(CLK) Fall time, sdti_clk td(CLK-TxD) Delay time, sdti_clk transition to sdti_txd[3:0] transition SD3 (1) 1.0 V MAX MIN 29 UNIT MAX 29 0.5*P (1) –1.2 ns 0.5*P (1) 1.2 –1.2 ns 1.2 ns 5 5 ns 5 5 ns ns Multiplexing mode on etk pins 2.3 10.9 2.3 10.9 Multiplexing mode on jtag_emu pins 2.3 13.9 2.3 13.9 tR(CLK) Rise time, sdti_txd[3:0] 5 5 ns tF(CLK) Fall time, sdti_txd[3:0] 5 5 ns P = sdti_clk clock period SD1 SD2 sdti_clk SD3 sdti_txd[3:0] Header SD3 Header Ad[7:4] Ad[3:0] Da[15:12] Da[11:8] Da[7:4] Da[3:0] 030-111 Figure 6-70. System Debug Trace Interface – Dual-Edge Mode 6.8.2.2 System Debug Trace Interface in Single-Edge Mode Table 6-146 assumes testing over the recommended operating conditions and electrical characteristic conditions (see Figure 6-71). Table 6-145. System Debug Trace Interface Timing Conditions – Single-Edge Mode TIMING CONDITION PARAMETER VALUE UNIT 25 pF Output Conditions CLOAD Output load capacitance Table 6-146. System Debug Trace Interface Switching Characteristics – Single-Edge Mode NO. PARAMETER 1.15 V MIN SD1 SD2 SD3 (1) tc(CLK) Cycle time, sdti_clk period 1.0 V MAX 29 tw(CLK) Typical pulse duration, sdti_clk high or low tdc(CLK) Duty cycle error, sdti_clk tR(CLK) Rise time, sdti_clk tF(CLK) Fall time, sdti_clk td(CLK-TxD) Delay time, sdti_clk transition to sdti_txd[3:0] transition MIN UNIT MAX 29 0.5*P –1.2 (1) ns 0.5*P 1.2 –1.2 5 5 (1) ns 1.2 ns 5 ns 5 ns Multiplexing mode on etk pins 2.3 26.5 2.3 26.5 ns Multiplexing mode on jtag_emu pins 2.3 33.2 2.3 33.2 tR(CLK) Rise time, sdti_txd[3:0] 5 5 ns tF(CLK) Fall time, sdti_txd[3:0] 5 5 ns P = sdti_clk clock period. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 251 PRODUCT PREVIEW NO. OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com SD1 SD2 sdti_clk SD3 sdti_txd[3:0] Header SD3 Header Ad[7:4] Ad[3:0] Da[15:12] Da[11:8] Da[7:4] Da[3:0] 030-112 Figure 6-71. System Debug Trace Interface – Single-Edge Mode 6.8.3 JTAG Interfaces PRODUCT PREVIEW OMAP3515/03 JTAG TAP controller handles standard IEEE JTAG interfaces. The following sections define the timing requirements for several tools used to test the OMAP3515/03 processors as: • Free running clock tool, like XDS560 and XDS510 tools • Adaptive clock tool, like RealView® ICE tool and Lauterbach™ tool 6.8.3.1 JTAG – Free Running Clock Mode Table 6-148 and Table 6-149 assume testing over the recommended operating conditions and electrical characteristic conditions (see Figure 6-72). Table 6-147. JTAG Timing Conditions – Free Running Clock Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 5 ns tF Input signal fall time 5 ns Output load capacitance 30 pF Output Conditions CLOAD Table 6-148. JTAG Timing Requirements – Free Running Clock Mode (1) NO. PARAMETER 1.15 V 1.0 V MIN JT4 tc(tck) Cycle time (2), jtag_tck period MAX 25 tw(tckL) Typical pulse duration, jtag_tck low 0.5*P JT6 tw(tckH) Typical pulse duration, jtag_tck high 0.5*P (3) tdc(tck) Duty cycle error, jtag_tck , jtag_tck UNIT MAX 33 (3) JT5 (4) MIN ns 0.5*P (3) ns 0.5*P (3) ns –1250 1250 –1667 1667 ps –1250 1250 –1667 1667 ps tj(tck) Cycle jitter JT7 tsu(tdiV-rtckH) Setup time, jtag_tdi valid before jtag_rtck high 1.8 1.8 ns JT8 th(tdiV-rtckH) Hold time, jtag_tdi valid after jtag_rtck high 0.7 1 ns JT9 tsu(tmsV-rtckH) Setup time, jtag_tms valid before jtag_rtck high 1.8 1.8 ns JT10 th(tmsV-rtckH) Hold time, jtag_tms valid after jtag_rtck high 0.7 1 ns JT12 tsu(emuxV-rtckH) Setup time, jtag_emux (5) valid before jtag_rtck high 14.6 19.8 ns JT13 th(emuxV-rtckH) Hold time,jtag_emux (5) valid after jtag_rtck high 2 2.7 ns (1) (2) (3) (4) (5) 252 The timing requirements are assured for the cycle jitter and duty cycle error conditions specified. Related with the input maximum frequency supported by the JTAG module. P = jtag _tck period in ns. Maximum cycle jitter supported by jtag _tck input clock. x = 0 to 1 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Table 6-149. JTAG Switching Characteristics – Free Running Clock Mode PARAMETER 1.15 V MIN 1.0 V MAX MIN UNIT MAX JT1 tc(rtck) Cycle time (1), jtag_rtck period JT2 tw(rtckL) Typical pulse duration, jtag_rtck low 0.5*PO (2) 0.5*PO (2) ns JT3 tw(rtckH) Typical pulse duration, jtag_rtck high 0.5*PO (2) 0.5*PO (2) ns tdc(rtck) Duty cycle error, jtag_rtck tj(rtck) Jitter standard deviation (3), jtag_rtck tR(rtck) tF(rtck) JT11 td(rtckL-tdoV) 33 –1250 1667 ps 33.3 33.3 ps Rise time, jtag_rtck 4 4 ns Fall time, jtag_rtck 4 4 ns Delay time, jtag_rtck low to jtag_tdo valid –1667 7.9 ns Rise time, jtag_tdo 4 4 ns tF(tdo) Fall time, jtag_tdo 4 4 ns Delay time, jtag_rtck high to ,jtag_emux (4) –5.8 1250 ns tR(tdo) JT14 td(rtckH-emuxV) (1) (2) (3) (4) 25 valid 2.7 5.8 –7.9 20.4 ns tR(emux) Rise time, jtag_emux (4) 15.1 6 2.7 6 ns tF(emux) Fall time, jtag_emux (4) 6 6 ns PRODUCT PREVIEW NO. Related with the jtag_rtck maximum frequency. PO = jtag _rtck period in ns. The jitter probability density can be approximated by a Gaussian function. x = 0 to 1 JT4 JT5 JT6 jtag_tck JT1 JT2 JT3 jtag_rtck JT7 JT8 JT9 JT10 jtag_tdi jtag_tms JT12 JT13 jtag_emux(IN) JT11 jtag_tdo JT14 jtag_emux(OUT) 030-113 In jtag_emux, x is equal to 0 to 1. Figure 6-72. JTAG Interface Timing – Free Running Clock Mode 6.8.3.2 JTAG – Adaptive Clock Mode Table 6-151 and Table 6-152 assume testing over the recommended operating conditions and electrical characteristic conditions (see Figure 6-73): Table 6-150. JTAG Timing Conditions – Adaptive Clock Mode TIMING CONDITION PARAMETER VALUE UNIT 5 ns Input Conditions tR Submit Documentation Feedback Input signal rise time TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 253 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com Table 6-150. JTAG Timing Conditions – Adaptive Clock Mode (continued) TIMING CONDITION PARAMETER tF VALUE UNIT Input signal fall time 5 ns Output load capacitance 30 pF Output Conditions CLOAD Table 6-151. JTAG Timing Requirements – Adaptive Clock Mode (1) NO. PARAMETER 1.15 V MIN JA4 tc(tck) Cycle time (2), jtag_tck period JA5 tw(tckL) Typical pulse duration, jtag_tck low JA6 1.0 V MAX 50 MIN UNIT MAX 50 ns 0.5*P (3) 0.5*P (3) ns (3) (3) ns PRODUCT PREVIEW tw(tckH) Typical pulse duration, jtag_tck high tdc(lclk) Duty cycle error, jtag_tck –2500 2500 –2500 2500 ps tj(lclk) Cycle jitter (4), jtag_tck –1500 1500 –1500 1500 ps JA7 tsu(tdiV-tckH) Setup time, jtag_tdi valid before jtag_tck high 13.8 13.8 ns JA8 th(tdiV-tckH) Hold time, jtag_tdi valid after jtag_tck high 13.8 13.8 ns JA9 tsu(tmsV-tckH) Setup time, jtag_tms valid before jtag_tck high 13.8 13.8 ns JA10 th(tmsV-tckH) Hold time, jtag_tms valid after jtag_tck high 13.8 13.8 ns (1) (2) (3) (4) 0.5*P 0.5*P The timing requirements are assured for the cycle jitter and duty cycle error conditions specified. Related with the input maximum frequency supported by the JTAG module. P = jtag _tck period in ns. Maximum cycle jitter supported by jtag _tck input clock. Table 6-152. JTAG Switching Characteristics – Adaptive Clock Mode NO. PARAMETER 1.15 V MIN JA1 tc(rtck) Cycle time (1), jtag_rtck period 1.0 V MAX 50 UNIT MAX 50 (2) JA2 tw(rtckL) Typical pulse duration, jtag_rtck low 0.5*PO JA3 tw(rtckH) Typical pulse duration, jtag_rtck high 0.5*PO (2) tdc(rtck) Duty cycle error, jtag_rtck JA11 MIN –2500 (3) , jtag_rtck ns (2) ns 0.5*PO (2) ns 0.5*PO 2500 –2500 2500 ps tj(rtck) Jitter standard deviation 33.3 33.3 ps tR(rtck) Rise time, jtag_rtck 4 4 ns tF(rtck) Fall time, jtag_rtck 4 4 ns td(rtckL-tdoV) Delay time, jtag_rtck low to jtag_tdo valid 14.6 ns tR(tdo) Rise time, jtag_tdo, 4 4 ns tF(tdo) Fall time, jtag_tdo 4 4 ns (1) (2) (3) Related with the jtag _rtck maximum frequency programmable. PO = jtag _rtck period in ns. The jitter probability density can be approximated by a Gaussian function. 254 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS –14.6 14.6 –14.6 Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 JA4 JA5 JA6 jtag_tck JA7 JA8 JA9 JA10 jtag_tdi jtag_tms JA1 JA2 JA3 jtag_rtck JA11 jtag_tdo PRODUCT PREVIEW 030-114 Figure 6-73. JTAG Interface Timing – Adaptive Clock Mode Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 255 OMAP3515/03 Applications Processor SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 www.ti.com 7 PACKAGE CHARACTERISTICS 7.1 Package Thermal Resistance Table 7-1 provides the thermal resistance characteristics for the recommended package types used on the OMAP3515/03 Applications Processor. Table 7-1. OMAP3515/03 Thermal Resistance Characteristics (1) (2) PRODUCT PREVIEW Package Power (W) RθJA(°C/W) RθJB(°C/W) RθJC(°C/W) Board Type OMAP3515/03 (CBB Pkg.) TBD 24.46 10.94 0.01 2S2P (3) OMAP35 15/03 (CBC Pkg.) TBD TBD TBD TBD TBD OMAP35 15/03 (CUS Pkg.) TBD TBD TBD TBD TBD (1) (2) (3) Not applicable since the POP package has a memory package on top, no heat sink can be used. (TBD) RθJA (Theta-JA) = Thermal Resistance Junction-to-Ambient, °C/W RθJB (Theta-JB) = Thermal Resistance Junction-to-Board, °C/W RθJC (Theta-JC) = Thermal Resistance Junction-to-Case, °C/W The board types are defined by JEDEC (reference JEDEC standard JESD51-9, Test Board for Area Array Surface Mount Package Thermal Measurements). 7.2 Device Support 7.2.1 Development Support (TBD) TBD 7.2.2 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all OMAP™ processors and support tools. Each OMAP device has one of three prefixes: X, P, or null (no prefix). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through fully qualified production devices/tools (TMDS). Device development evolutionary flow: X Experimental device that is not necessarily representative of the final device’s electrical specifications and may not use production assembly flow. (TMX definition) P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. (TMP definition) null Production version of the silicon die that is fully qualified. (TMS definition) Support tool development evolutionary flow: TMDX Development support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development support product. TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. 256 PACKAGE CHARACTERISTICS Submit Documentation Feedback OMAP3515/03 Applications Processor www.ti.com SPRS505B – FEBRUARY 2008 – REVISED JULY 2008 Predictions show that prototype devices (X or P), have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. For additional description of the device nomenclature markings, see the OMAP35x Applications Processor Silicon Errata (literature number SPRZ278). OMAP3530 B CBB ( ) 600 = 600 MHz Cortex - A8 PREFIX X = Experimental Device P = Prototype Device blank= Production Device DEVICE SILICON REVISION 600 blank = 0° C to 90° C (commercial temperature) A = -40° C to 105° C (extended temperature) PACKAGE TYPE CBB = 515 pin PBGA CBC = 515 pin S-PBGA CUS = 423 pin PBGA Figure 7-1. Device Nomenclature 7.2.3 Documentation Support 7.2.3.1 Related Documentation from Texas Instruments The following documents describe the OMAP3515/03 Applications Processor. Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com. The current documentation that describes the OMAP3515/03 Applications Processor, related peripherals, and other technical collateral, is available in the product folder at: www.ti.com. SPRUF98 OMAP35x Technical Reference Manual. Collection of documents providing detailed information on the OMAP3 architecture including power, reset, and clock control, interrupts, memory map, and switch fabric interconnect. Detailed information on the microprocessor unit (MPU) subsystem, the image, video, and audio (IVA2.2) subsystem, as well a functional description of the peripherals supported on OMAP35x devices is also included. SPRU889 High-Speed DSP Systems Design Reference Guide. Provides recommendations for meeting the many challenges of high-speed DSP system design. These recommendations include information about DSP audio, video, and communications systems for the C5000 and C6000 DSP platforms. 7.2.3.2 Related Documentation from Other Sources The following documents are related to the OMAP3515/03 Applications Processor. Copies of these documents can be obtained directly from the internet or from your Texas Instruments representative. Cortex™-A8 Technical Reference Manual. This is the technical reference manual for the Cortex-A8 processor. A copy of this document can be obtained via the internet at http://infocenter.arm.com. Please see the OMAP35x Applications Processor Silicon Errata (literature number SPRZ278) to determine the revision of the Cortex-A8 core used on your device. ARM Core CortexTM-A8 (AT400/AT401) Errata Notice. Provides a list of advisories for the different revisions of the Cortex-A8 processor. Contact your TI representative for a copy of this document. Please see the OMAP35x Applications Processor Silicon Errata (literature number SPRZ278) to determine the revision of the Cortex-A8 core used on your device. Submit Documentation Feedback PACKAGE CHARACTERISTICS 257 PRODUCT PREVIEW X PACKAGE OPTION ADDENDUM www.ti.com 8-Aug-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) XOMAP3503BCBB ACTIVE FCBGA CBB 515 168 TBD Call TI Call TI XOMAP3503BCUS ACTIVE FCBGA CUS 423 90 TBD Call TI Call TI XOMAP3515BCBB ACTIVE FCBGA CBB 515 168 TBD Call TI Call TI XOMAP3515BCUS ACTIVE FCBGA CUS 423 90 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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