SN74CBTLV16800 LOW-VOLTAGE 20-BIT FET BUS SWITCH WITH PRECHARGED OUTPUTS SCDS045F – DECEMBER 1997 – REVISED MAY 1999 D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) 5-Ω Switch Connection Between Two Ports Isolation Under Power-Off Conditions B-Port Outputs Are Precharged by Bias Voltage to Minimize Signal Distortion During Live Insertion ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Plastic Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV), and 300-mil Shrink Small-Outline (DL) Packages BIASV 1A1 1A2 1A3 1A4 1A5 1A6 GND 1A7 1A8 1A9 1A10 2A1 2A2 VCC 2A3 GND 2A4 2A5 2A6 2A7 2A8 2A9 2A10 NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR. description The SN74CBTLV16800 provides 20 bits of high-speed bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device also precharges the B port to a user-selectable bias voltage (BIASV) to minimize live-insertion noise. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 2OE 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1B9 1B10 2B1 2B2 2B3 GND 2B4 2B5 2B6 2B7 2B8 2B9 2B10 The device is organized as dual 10-bit bus switches with separate output-enable (OE) inputs. It can be used as two 10-bit bus switches or one 20-bit bus switch. When OE is low, the associated 10-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, the high-impedance state exists between the two ports, and port B is precharged to BIASV through the equivalent of a 10-kΩ resistor. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74CBTLV16800 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each 10-bit bus switch) INPUT OE FUNCTION L A port = B port H A port = Z B port = BIASV Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74CBTLV16800 LOW-VOLTAGE 20-BIT FET BUS SWITCH WITH PRECHARGED OUTPUTS SCDS045F – DECEMBER 1997 – REVISED MAY 1999 logic diagram (positive logic) 1 BIASV 46 2 SW 1A1 12 1B1 36 SW 1A10 1B10 48 1OE 35 13 SW 2A1 24 2B1 25 SW 2A10 2B10 47 2OE simplified schematic, each FET switch A B (OE) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBTLV16800 LOW-VOLTAGE 20-BIT FET BUS SWITCH WITH PRECHARGED OUTPUTS SCDS045F – DECEMBER 1997 – REVISED MAY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Bias voltage range, BIASV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) VCC BIASV Supply voltage Bias voltage VIH High level control input voltage High-level VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL Low level control input voltage Low-level VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 2.3 3.6 V 1.3 VCC V 1.7 UNIT V 2 0.7 0.8 V TA Operating free-air temperature –40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II Ioff IO A port ICC ∆ICC§ Control inputs Ci Control inputs Cio(OFF) TEST CONDITIONS VCC = 3 V, VCC = 3.6 V, II = –18 mA VI = VCC or GND VCC = 0, VCC = 3 V, VI or VO= 0 to 3.6 V BIASV = 2.4 V, VO= 0, OE = VCC IO = 0, VI = VCC or GND VCC = 3.6 V, VCC = 3.6 V, One input at 3 V, VI = 3 V or 0 VO = 3 V or 0, VCC = 3 V TYP‡ MAX V ±1 µA 10 0.25 Other inputs at VCC or GND UNIT –1.2 µA mA 10 µA 300 µA 4.5 VCC = 2.3 23V V, TYP at VCC = 2.5 V ron¶ MIN pF Switch off, BIASV = Open VI = 0 II = 64 mA II = 24 mA 6.5 5 pF 5 9 VI = 1.7 V, II = 15 mA 25 35 VI = 0 II = 64 mA II = 24 mA 5 7 5 7 9 Ω VI = 2.4 V, II = 15 mA 8 15 ‡ All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. § This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. ¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74CBTLV16800 LOW-VOLTAGE 20-BIT FET BUS SWITCH WITH PRECHARGED OUTPUTS SCDS045F – DECEMBER 1997 – REVISED MAY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 and 2) TEST CONDITIONS PARAMETER tpd† tPZH BIASV = GND tPZL BIASV = 3 V tPHZ BIASV = GND tPLZ BIASV = 3 V FROM (INPUT) TO (OUTPUT) A or B B or A OE A or B OE A or B VCC = 2.5 V ± 0.2 V MIN VCC = 3.3 V ± 0.3 V MAX MIN UNIT MAX 0.35 0.25 2.9 7.7 2.2 5.5 2.8 6.4 2.1 5.3 1.4 6.8 2.6 7.6 1.3 4.2 1.5 5.1 ns ns ns † The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND Output Control (low-level enabling) LOAD CIRCUIT VCC VCC/2 VCC/2 0V tPLZ tPZL VCC VCC/2 Input VCC/2 0V tPLH VCC/2 VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.15 V VOL tPHZ tPZH tPHL VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBTLV16800 LOW-VOLTAGE 20-BIT FET BUS SWITCH WITH PRECHARGED OUTPUTS SCDS045F – DECEMBER 1997 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND 3V Output Control (low-level enabling) LOAD CIRCUIT 1.5 V 0V tPZL 3V Input 1.5 V 1.5 V 0V tPLH VOH Output 1.5 V Output Waveform 1 S1 at 6 V (see Note B) tPLZ 3V 1.5 V 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.3 V VOL tPZH tPHL 1.5 V tPHZ 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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