SN74CBTLV3245 LOW-VOLTAGE OCTAL FET BUS SWITCH SCDS034F – JULY 1997 – REVISED MAY 1998 D D D D D DB, DGV, DW, OR PW PACKAGE (TOP VIEW) Standard ’245-Type Pinout 5-Ω Switch Connection Between Two Ports Isolation Under Power-Off Conditions ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Small-Outline (DW), and Thin Shrink Small-Outline (PW) Packages NC A1 A2 A3 A4 A5 A6 A7 A8 GND description The SN74CBTLV3245 provides eight bits of high-speed bus switching in a standard ’245 device pinout. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE B1 B2 B3 B4 B5 B6 B7 B8 NC – No internal connection The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on and port A is connected to port B. When OE is high, the switch is open and a high-impedance state exists between the two ports. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74CBTLV3245 is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUT OE FUNCTION L A port = B port H Disconnect logic diagram (positive logic) 2 A1 18 B1 SW 9 A8 11 SW B8 19 OE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74CBTLV3245 LOW-VOLTAGE OCTAL FET BUS SWITCH SCDS034F – JULY 1997 – REVISED MAY 1998 simplified schematic, each FET switch A B (OE) absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) VCC Supply voltage VIH High level control input voltage High-level VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL Low level control input voltage Low-level VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 2.3 3.6 1.7 UNIT V V 2 0.7 0.8 V TA Operating free-air temperature –40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBTLV3245 LOW-VOLTAGE OCTAL FET BUS SWITCH SCDS034F – JULY 1997 – REVISED MAY 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK II VCC = 3 V, VCC = 3.6 V, II = –18 mA VI = VCC or GND Ioff ICC VCC = 0, VCC = 3.6 V, VI or VO = 0 to 3.6 V IO = 0, VCC = 3.6 V, VI = 3 V or 0 One input at 3 V, VO = 3 V or 0, OE = VCC ∆ICC‡ Control inputs Ci Control inputs Cio(OFF) MIN TYP† VI = VCC or GND Other inputs at VCC or GND MAX UNIT –0.8 V ±50 µA 30 µA 20 µA 750 µA 3.5 VI = 0 VCC = 2.3 2 3 V, V TYP at VCC = 2 2.5 5V VI = 1.7 V, ron§ VI = 0 VCC = 3 V II = 64 mA II = 24 mA II = 15 mA II = 64 mA II = 24 mA II = 15 mA pF 8 ¶ ¶ pF ¶ ¶ ¶ ¶ 5 7 5 7 Ω VI = 2.4 V, 10 15 † All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡ This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. § Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. ¶ This information was not available at the time of publication. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 and 2) PARAMETER tpd# ten tdis FROM (INPUT) TO (OUTPUT) A or B B or A VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V MIN MAX ¶ MIN ¶ ¶ OE A or B ¶ OE A or B ¶ UNIT MAX 0.25 ns 1 5.6 ns 1 6.5 ns ¶ This information was not available at the time of publication. # The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74CBTLV3245 LOW-VOLTAGE OCTAL FET BUS SWITCH SCDS034F – JULY 1997 – REVISED MAY 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC 500 Ω From Output Under Test S1 Open GND CL = 30 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω Output Control (low-level enabling) LOAD CIRCUIT VCC VCC/2 0V tPLZ tPZL VCC VCC/2 Input VCC/2 0V tPLH VCC/2 VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.15 V VOL tPHZ tPZH VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBTLV3245 LOW-VOLTAGE OCTAL FET BUS SWITCH SCDS034F – JULY 1997 – REVISED MAY 1998 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND VCC Output Control LOAD CIRCUIT VCC/2 0V tPLZ tPZL VCC VCC/2 Input VCC/2 0V tPLH VCC/2 VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.3 V VOL tPHZ tPZH VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC/2 VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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