SN74CBTLV3257 LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999 D D D D D D D, DBQ, DGV, OR PW PACKAGE (TOP VIEW) Functionally Equivalent to QS3257 5-Ω Switch Connection Between Two Ports Isolation Under Power-Off Conditions ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Thin Very Small-Outline (DGV), Small-Outline (D), Shrink Small-Outline (DBQ), and Thin Shrink Small-Outline (PW) Packages S 1B1 1B2 1A 2B1 2B2 2A GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC OE 4B1 4B2 4A 3B1 3B2 3A description The SN74CBTLV3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The select (S) input controls the data flow. The FET multiplexers/demultiplexers are disabled when the output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74CBTLV3257 is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS FUNCTION OE S L L A port = B1 port L H A port = B2 port H X Disconnect Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74CBTLV3257 LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999 logic diagram (positive logic) 2 4 1A 1B1 SW 3 1B2 SW 7 5 2A 2B1 SW 6 2B2 SW 3A 11 9 SW 3B1 10 3B2 SW 14 12 4A 4B1 SW 13 4B2 SW 1 S 15 OE simplified schematic, each FET switch A B (OE) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBTLV3257 LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) VCC Supply voltage VIH High level control input voltage High-level VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL Low level control input voltage Low-level VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 2.3 3.6 1.7 UNIT V V 2 0.7 0.8 V TA Operating free-air temperature –40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK II VCC = 3 V, VCC = 3.6 V, II = –18 mA VI = VCC or GND Ioff ICC VCC = 0, VCC = 3.6 V, VI or VO= 0 to 4.5 V IO = 0, VI = VCC or GND One input at 3 V, Other inputs at VCC or GND ∆ICC§ Ci Ciio(OFF) (OFF) Control inputs Control inputs VCC = 3.6 V, VI = 3 V or 0 TYP‡ MAX V ±1 µA 10 µA 10 µA 300 µA pF 5.5 VO = 3 V or 0, 0 OE = VCC VCC = 2.3 2 3 V, V TYP at VCC = 2.5 25V VI = 0 ron¶ VCC = 3 V VI = 1.7 V, VI = 0 UNIT –1.2 3 A port B port MIN pF 10.5 II = 64 mA II = 24 mA 5 5 8 8 II = 15 mA II = 64 mA 27 40 5 7 Ω II = 24 mA 5 7 VI = 2.4 V, II = 15 mA 10 15 ‡ All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. § This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. ¶ Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74CBTLV3257 LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 and 2) VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V FROM (INPUT) TO (OUTPUT) A or B† B or A S A or B 1.8 6.1 1.8 5.3 ten S A or B 1.7 6.1 1.7 5.3 ns tdis S A or B 1 4.8 1 4.5 ns ten OE A or B 1.9 5.6 2 5 ns tdis OE A or B 1 5.5 1.6 5.5 ns PARAMETER tpd MIN MAX MIN UNIT MAX 0.35 0.25 ns † The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω VCC Output Control LOAD CIRCUIT VCC/2 0V tPZL VCC VCC/2 Input VCC/2 0V tPLH VCC/2 tPLZ VCC VCC/2 tPZH VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VOL VCC/2 Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBTLV3257 LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND VCC Output Control LOAD CIRCUIT VCC/2 0V tPZL VCC VCC/2 Input VCC/2 0V tPLH VCC/2 tPLZ VCC VCC/2 tPZH VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VOL VCC/2 Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ VCC/2 VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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