SN74ALVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS419D – JANUARY 1993 – REVISED AUGUST 1995 D D D D D D EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Member of the Texas Instruments Widebus Family ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Bus Hold on Data Inputs Eliminates the Need for External Pullup / Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages DGG OR DL PACKAGE (TOP VIEW) 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR description The SN74ALVC16245 16-bit (dual-octal) noninverting bus transceiver is designed for 2.3-V to 3.6-V VCC operation; it is tested at 2.5-V, 2.7-V, and 3.3-V VCC. The SN74ALVC16245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVC16245 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN74ALVC16245 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE (each 8-bit section) INPUTS OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS419D – JANUARY 1993 – REVISED AUGUST 1995 logic symbol† 48 1OE 1DIR 1 logic diagram (positive logic) G3 1DIR 1 3 EN1 [BA] 3 EN2 [AB] 25 2OE 2DIR 24 48 G6 6 EN4 [BA] 6 EN5 [AB] 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 47 1A1 2 1 2 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4 47 1B1 2 1B3 1B4 1B5 To Seven Other Channels 1B6 1B7 1B8 2DIR 24 2B1 25 2A3 2A4 2A5 2A6 2A7 2A8 35 14 33 16 32 17 30 19 29 20 27 22 26 23 2OE 2B2 2B3 2B4 2A1 36 2B5 13 2B6 2B7 2B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 1B1 1B2 5 2A2 1OE POST OFFICE BOX 655303 To Seven Other Channels • DALLAS, TEXAS 75265 2B1 SN74ALVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS419D – JANUARY 1993 – REVISED AUGUST 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 4.6 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . 0.85 W DL package . . . . . . . . . . . . . . . . . . 1.2 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 4) VCC Supply voltage MIN MAX 2.3 3.6 VIH High level input voltage High-level VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL Low level input voltage Low-level VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VI VO Input voltage 0 Output voltage 0 IOH High-level output current IOL ∆t / ∆v Low-level output current 0.7 0.8 VCC VCC – 12 VCC = 3 V VCC = 2.3 V – 24 VCC = 2.7 V VCC = 3 V 12 Input transition rise or fall rate • DALLAS, TEXAS 75265 V V 2 VCC = 2.3 V VCC = 2.7 V TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 1.7 UNIT – 12 V V V mA 12 mA 24 0 10 ns/ V – 40 85 °C 3 SN74ALVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS419D – JANUARY 1993 – REVISED AUGUST 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = – 100 µA IOH = – 6 mA, VOH VOL MIN to MAX VIH = 1.7 V VIH = 1.7 V 2.3 V VCC – 0.2 2.0 2.3 V 1.7 IOH = – 12 mA VIH = 2 V VIH = 2 V 2.7 V 2.2 3V 2.4 IOH = – 24 mA, IOL = 100 µA VIH = 2 V 3V 2 MIN to MAX 0.2 IOL = 6 mA, VIL = 0.7 V VIL = 0.7 V 2.3 V 0.4 2.3 V 0.7 VIL = 0.8 V VIL = 0.8 V 2.7 V 0.4 3V 0.55 IOL = 12 mA IOL = 24 mA, VI = VCC or GND II Ihold h ld 23V 2.3 VI = 0.8 V VI = 2 V 3V VO = VCC or GND VI = VCC or GND, nICC VCC = 3 V to 3.6 V, Other inputs at VCC or GND Control inputs IO = 0 One input at VCC – 0.6 V, VI = VCC or GND VO = VCC or GND UNIT V ±5 3.6 V VI = 0.7 V VI = 1.7 V IOZ§ ICC Ci TA = – 40°C to 85°C MIN TYP‡ MAX VCC† TEST CONDITIONS V µA 45 –45 µA 75 –75 3.6 V ±10 µA 3.6 V 40 µA 750 µA 3.3 V Cio A or B ports 3.3 V † For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. ‡ All typical values are at VCC = 3.3 V. § For I/O ports, the parameter IOZ includes the input leakage current. 4 pF 9 pF switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figures 1 and 2) FROM (INPUT) TO (OUTPUT) tpd A or B ten tdis PARAMETER VCC = 2.5 V ± 0.2 V MIN MAX B or A 1 5 OE B or A 1 OE B or A 1 VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX 4 1 3.6 ns 6.8 6 1 5 ns 6 5.2 1 5 ns operating characteristics, TA = 25° C PARAMETER Cpd d 4 Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled pF CL = 50 pF, POST OFFICE BOX 655303 f = 10 MHz • DALLAS, TEXAS 75265 VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V TYP TYP 22 29 4 5 UNIT pF SN74ALVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS419D – JANUARY 1993 – REVISED AUGUST 1995 " PARAMETER MEASUREMENT INFORMATION 0.2 V VCC = 2.5 V 4.6 V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 4.6 V GND tw LOAD CIRCUIT 2.3 V 2.3 V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.3 V Data Input 1.2 V 1.2 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.2 V 1.2 V 0V tPLH tPHL VOH 1.2 V 2.3 V Output Control (low-level enabling) 1.2 V 1.2 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ 2.3 V Output Waveform 1 S1 at 4.6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.2 V 0V tPZL 2.3 V Output 1.2 V 1.2 V tsu Input Input 1.2 V 1.2 V VOL + 0.3 V VOL tPHZ tPZH 1.2 V VOH – 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. v v v Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS419D – JANUARY 1993 – REVISED AUGUST 1995 " PARAMETER MEASUREMENT INFORMATION 0.3 V VCC = 2.7 V AND 3.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH tPHL VOH 1.5 V 2.7 V Output Control (low-level enabling) 1.5 V 1.5 V VOL tPLZ 3V Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V 0V tPZL 2.7 V Output 1.5 V 1.5 V tsu Input Input 1.5 V 1.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH – 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. v Figure 2. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 v v IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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