Silan Semiconductors SC88E43 EXTENDED VOLTAGE CALLING NUMBER IDENTIFICATION CIRCUIT 2 DESCRIPTION The SC88E43 Calling Number Identification Circuit 2(ECNIC2) is a low power CMOS integrated circuit intended for receiving physical DIP-24 layer signals transmitted according to BT (British Telecom) SIN227 & SIN242, the U.K.’s CCA (Cable Communications Association) TW/P&E/312 and Bellcore GR-30-CORE & SR-TSV-002476 specifications. The SC88E43 is suitable for applications using a fixed voltage power source between 3 and 5V ±10%. FEATURES SOP-24 * Compatible with: -- British Telecom (BT) SIN227 & SIN242 APPLICATIONS -- U.K.’s Cable Communications Association (CCA) specification TW/P&E/312 * BT Calling Line Identity Presentation -- Bellcore GR-30-CORE (formerly known as TR-NWT-000030) (CLIP), CCA CLIP, and Bellcore Calling & SR-TSV-002476 Identity Delivery (CID) systems * Bellcore “CPE” Alerting Signal” (CAS) and BT “Idle State * Feature phones, including Analog Tone Alert Signal” detection Display Services Interface (ADSI) * Ring and line reversal detection phones * 1200 baud Bell 202 and CCITT V.23 Frequency Shift Keying * Phone set adjunct boxes (FSK) demodulation * 3 or 5V ±10% supply voltage * FAX and answering machines * High input sensitivity (-40dBv Tone and FSK Detection) * Database query and Computer * Selectable 3-wire FSK data interface Telephony Integration (CTI) systems (microcontroller or SC88E43 controlled) * Low power CMOS with powerdown mode ORDERING INFORMATION * Input gain adjustable amplifier * Carrier detect status output SC88E43 SC88E43S * Uses 3.58 MHz crystal 24 Pin DIP 24 Pin SOIC RECOMMENDED OPERATING CONDITIONS(Ta=25°C ; Voltages are with respect to VSS) Symbol Min Typ Max Power Supplies Parameter VDD 2.7 -- 5.5 Unit V Clock Frequency fOSC -- 3.579545 -- MHz Tolerance on Clock Frequency ∆fC -0.1 -- +0.1 % Operating Temperature TOP -40 -- 85 °C HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 1 2000.12.31 Silan Semiconductors SC88E43 PIN CONFIGURATION IN+ 1 24 VDD IN- 2 23 St/GT GS 3 22 ESt VRef 4 21 StD CAP 5 20 INT TRIGin 6 19 CD TRIGRC 7 18 DR TRIGout 8 17 DATA MODE 9 16 DCLK OSCI 10 15 FSKen SC88E43 OSCO 11 14 PWDN Vss 12 13 IC BLOCK DIAGRAM IN+ 1 + IN- 2 - GS 3 VRef 4 Anti-alias Filter FSK Bandpass Filter FSKen MODE 15 9 FSK Demodulator To internal cct. Bias Generator Carrier Detector CAP 5 16 DCLK Data Timing Recovery 17 DATA 18 DR 19 CD Interrupt Generator 20 INT PWDN 14 Alert Signal High Tone Filter To internal cct. Tone Detection Algorithm Alert Signal Low Tone Filter Oscillator Guard Time 21 StD 23 St/GT 22 ESt 24 VDD 12 VSS 10 11 OSCin OSCout 6 7 8 TRIGin TRIGRC TRIGout HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 2 2000.12.31 Silan Semiconductors SC88E43 ABSOLUTE MAXIMUM RATINGS (Voltages are with respect to VSS, unless otherwise stated). Symbol Value Unit Supply Voltage Characteristic VDD -0.3 ~ 6.0 V Voltage on any pin other than supplies* VPIN Vss-0.3V ~ VDD+0.3V V Current at any pin other than supplies IPIN 10 mA Storage Temperature Tstg -65 ~ +150 °C * Under normal operating conditions voltage on any pin except supplies can be minimum VSS -1V to maximum VDD +1V for an input current limited to less than 200mA. DC ELECTRICAL CHARACTERISTICS Parameter Symbol Test conditions Min Typ Max Unit -- 0.5 15 µA -- 4.7 8 mA -- 2.5 4.5 mA -- -- 44 mW -- 0.68VDD V All input are VDD/VSS except for oscillator pins. Stand-by Supply Current IDDQ No analog input. Outputs unloaded. PWDN = VDD. All input are VDD/VSS VDD=5V±10% Operating except for oscillator pins. IDD Supply Current VDD=3V±10% No analog input. Outputs unloaded. PWDN = VSS; FSKen = VDD. Power Consumption PO Schmitt Input High Threshold VT+ Schmitt Input Low Threshold VT- Schmitt Hysteresis VHYS -TRIGin, TRIGRC ,PWDN Pins 0.48VDD TRIGin, TRIGRC ,PWDN Pins 0.28VDD TRIGin, TRIGRC ,PWDN Pins 0.2 -- 0.48VDD V -- -- V CMOS Input High Voltage VIH DCLK,MODE,FSKen Pins 0.7VDD -- VDD V CMOS Input Low Voltage VIL DCLK,MODE,FSKen Pins VSS -- 0.3VDD V Output High Sourcing Current IOH VOH = 0.9VDD TRIGout ,DCLK,DADA, DR , CD ,StD,Est,St/GT Pins 0.8 -- -- mA 2 -- -- mA -- -- 1 µA -- -- 10 µA Output Low Sinking Current IOL VOL = 0.1VDD TRIGout ,DCLK,DATA, DR , CD , StD, Est,St/GT, TRIGRC INT Pins IIN1 VIN = VDD to VSS IN+,IN-,TRIGin Pins Input Current IIN2 VIN = VDD to VSS PWDN,DCLK,MODE,FSKen (To be continued) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 3 2000.12.31 Silan Semiconductors SC88E43 (continued) Parameter Symbol Output High-Impedance Current Min Typ Max Unit IOZ1 VOUT = VDD to VSS, TRIGRC Pin. -- -- 1 µA IOZ2 VOUT = VDD to VSS, INT Pin. -- -- 10 µA -- -- 5 µA IOZ3 Output Voltage VREF Output Resistance RREF Comparator Threshold Voltage VTGt Test conditions VOUT = VDD to VSS, St/GT Pin. No load. 0.5VDD Vref Pin -0.05 Vref Pin 0.5VDD --- 0.5VDD - St/GT Pin 0.05 V +0.05 kΩ 2 0.5VDD -- V +0.05 AC ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Min Typ Max Unit Notes Dual Tone Alert Signal Detection Low Tone Frequency fL -- 2130 -- Hz High Tone Frequency fH -- 2750 -- Hz Frequency Deviation accept 1.1% -- -- -- 4 Frequency Deviation Reject 3.5% -- -- -- 5 -40 -- -2 dBV a -37.78 -- 0.22 dBm b Accept Signal Level Per Tone Rejet Signal Level Per Tone Positive And Negtive Twist Accept Signal to Noise Ratio SNRTONE -- -- -46 dBV -- -- -43.78 dBm 7 -- -- dB c 20 -- -- dB 3 3 1,2 Timming Parameter Measurement Voltage Levels CMOS Threshold Voltage VCT -- 0.5VDD -- V Rise/Fall Threshold Voltage High VHM -- 0.7VDD -- V Rise/Fall Threshold Voltage Low VLM -- 0.3VDD -- V Gain Setting Amplifier Input Leakage Current IIN VSS ≤ VIN ≤ VDD -- -- 1 µA Input Resistance RIN -- 10 -- -- MΩ -- -- -- 25 mV 1kHz ripple on VDD 40 -- -- Input Offset Voltage Power Supply Rejection Ratio VOS PSRR dB (To be continued) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 4 2000.12.31 Silan Semiconductors SC88E43 (continued) Parameter Common Mode Rejection DC Open Loop Voltage Gain Symbol Conditions CMRR VCMmin ≤ VIN ≤ VCMmax Min Typ Max Unit 40 -- -- dB AVOL -- 30 -- -- dB Unity Gain Bandwidth fC -- 0.3 -- -- MHz Output Voltage Swing VO Load ≥ 50kΩ 0.5 -- VDD-0.5 VPP Maximum Capacitive Load (GS) CL -- -- -- 100 pF Maximum Resistive Load (GS) RL -- 50 -- -- kΩ Common Mode Range Voltage VCM -- 1.0 -- VDD-0.1 V -- -40 -- -8 dBV a -- -37.78 -- -5.78 dBm b Notes FSK Detection Input Detection Level Transmission Rate Input Frequency Detection Signal to Noise Ratio 6,8 -- 10 -- 398.1 mVrms -- 1188 1200 1212 baud Bell 202 1 (Mark) 1188 1200 1212 Hz Bell 202 0 (Space) 2178 2200 2222 Hz CCITT V.23 1 (Mark) 1280.5 1300 1319.5 Hz CCITT V.23 0 (Space) 2068.5 2100 2131.5 Hz 20 -- -- dB 6,7 SNRFSK -- Dual Tone Alert Signal Timing Alert Signal Present Detect Time tDP -- 0.5 -- 10 ms 9 Alert Signal Absent Detect Time tDA -- 0.1 -- 8 ms 9 3-Wire Interface Timming Power-up Time tPU Power-down Time tPD Input FSK to CD Low Delay tCP Input FSK to CD High Delay tCA PWDN, OSC1 Pins CD Pin Hysteresis -- -- 50 ms -- -- 1 ms -- -- 25 ms 8 -- -- ms 8 -- -- ms 3-Wire Interface Timming (Mode 0) RiseTime tRR DR Pin -- -- 200 ns 10 Fall Time tRF DR Pin -- -- 200 ns 10 Low Time tRL Rate Input FSK to DATA delay DR Pin 415 416 417 µs 12 -- DATA Pin 1188 1200 1212 baud 11 tIDD DATA Pin -- 1 5 ms (To be continued) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 5 2000.12.31 Silan Semiconductors SC88E43 (continued) Min Typ Max Unit Notes Rise time Parameter Symbol tR -- -- 200 ns 10 Fall Time tF -- -- 200 ns 10 6 416 -- µs 11,12, -- µs 11,12, 1204 Hz 12 DATA to DCLK delay tDCD DCLK to DATA delay tCDD Frequency fDCLK0 High Time tCH Low Time DCLK to DR delay Conditions DATA, DCLK Pins 6 1201.6 1202.8 DCLK Pin 13 415 416 417 µs 12 415 416 417 µs 12 DCLK , DR Pin 415 416 417 µs 12 -- -- 1 MHz DCLK Pin 30 -- 70 % -- -- 20 ns 500 -- -- ns 500 -- -- ns tCL tCRD 416 13 3-Wire Interface Timming (Mode 1) Frequency fDCLK1 Duty Cycle RiseTime tR1 Rate tDDS Input FSK to DATA delay tDDH DCLK , DR Pin a. dBV= decibels above or below a reference voltage of 1Vrms. Signal level is per tone. b. dBm = decibels above or below a reference power of 1mW into 600 ohms. 0dBm = 0.7746Vrms. Signal level is per tone. c. Twist = 20 log (fH amplitude / fL amplitude). Notes: 1. Both tones have the same amplitude. 2. 3. 4. 5. 6. 7. Band limited random noise 300-3400Hz. Measurement valid only when tone is present. With gain setting as shown in Figure 10. Production tested at VDD =3V±10%, 5V±10%. Range within which tones are accepted. Ranges outside of which tones are rejected. Both mark and space have the same amplitude. Band limited random noise (200-3400Hz). Present when FSK signal is present. Note that the BT band is 300-3400Hz, the Bellcore band is 0-4kHz. 8. Production tested at VDD =5V±10%, 3V±10%. 9. Refer to Figure 16 and 19. 10. into 50pF load. 11. FSK input data at 1200±12 baud. 12. OSCI at 3.579545 MHz±0.1%. 13. Function of signal condition. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 6 2000.12.31 Silan Semiconductors SC88E43 PIN DESCRIPTION Pin No. Symbol I/O 1 IN+ Input 2 IN- Input Function Non-inverting Input of the internal opamp. Inverting Input of the internal opamp. Gain Select of internal opamp. The opamp’s gain should be set 3 GS Output according to the nominal Vdd of the application using the information in Figure 10. 4 VRef Output 5 CAP -- 6 TRIGin Trigger Input 7 TRIGRC Open Drain Output / Schmitt Input 8 TRIGout CMOS Output Reference Voltage. Nominally VDD/2. It is used to bias the input opamp. Capacitor. A 0.1mF decoupling capacitor should be connected across this pin and VSS. Trigger Input. Schmitt trigger buffer input. Used for line reversal and ring detection. Trigger RC. Used to set the (RC) time interval from TRIGin going low to TRIGout going high. An external resistor connected to VDD and capacitor connected to VSS determine the duration of the (RC) time interval. Trigger Out. Schmitt trigger buffer output. Used to indicate detection of line reversal and/or ringing. 3-wire interface: Mode Select. When low, selects FSK data interface 9 MODE CMOS Input mode 0. When high, selects FSK data interface mode 1. See pin 16 (DCLK) description to understand how MODE affects the DCLK pin. Oscillator Input. A 3.579545MHz crystal should be connected between 10 OSCI Input this pin and OSCO. It may also be driven directly from an external clock source. Oscillator Output. A 3.579545MHz crystal should be connected 11 OSCO Output between this pin and OSCI. When OSCI is driven by an external clock, 12 Vss -- Power Supply Ground. 13 IC -- Internal Connection. Must be connected to VSS for normal operation. this pin should be left open. Power Down. Active high. When high, the device consumes minimal 14 PWDN Schmitt Input power by disabling all functionality except TRIGin, TRIGRC and. TRIGout Must be pulled low for device operation. (To be continued) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 7 2000.12.31 Silan Semiconductors SC88E43 (continued) Pin No. Symbol I/O Function FSK Enable. Must be high for FSK demodulation. This pin should be 15 FSKen CMOS Input set low to prevent the FSK demodulator from reacting to extraneous signals (such as speech, alert signal and DTMF which are all in the same frequency band as FSK). 16 DCLK 17 DATA CMOS Input/Output 3-wire Interface: Data Clock. In mode 0 (MODE pin low), this pin is an output. In mode 1 (MODE pin high), this pin is an input. 3-wire Interface: Data. In mode 0 the FSK data appears at the pin CMOS Output once demodulated. In mode 1 the FSK data is shifted out on the rising edge of the microcontroller supplied DCLK. 3-wire Interface: Data Ready. Active low. In mode 0 this output goes low after the last DCLK pulse of each data word. This identifies the 8- 18 DR CMOS Output bit word boundary on the serial output stream. Typically, DR is used to latch 8-bit words from a serial-to-parallel converter into a microcontroller. In mode 1 this pin will signal the availability of data. 19 CD 20 INT CMOS Output Open Drain Output 21 StD CMOS Output 22 ESt CMOS Output Carrier Detect. Active low. A logic low indicates the presence of inband signal at the output of the FSK bandpass filter. Interrupt. Active low. It is active when TRIGout or DR is low, or StD is high. This output stays low until all three signals have become inactive. Dual Tone Alert Signal Delayed Steering Output. When high, it indicates that a guard time qualified alert signal has been detected. Dual Tone Alert Signal Early Steering Output. Alert signal detection output. Used in conjunction with St/GT and external circuitry to implement the detect and non-detect guard times. Dual Tone Alert Signal Steering Input/Guard Time. A voltage greater 23 St/GT 24 VDD Analog Input / than VTGt (see figure 4) at the St/GT pin causes the device to indicate CMOS Output that a dual tone has been detected by asserting StD high. A voltage less than VTGt frees the device to accept a new dual tone. -- Positive Power Supply. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 8 2000.12.31 Silan Semiconductors SC88E43 FUNCTIONAL DESCRIPTION Detection of CLIP/CID Call Arrival Indicators The cricuit in Figure 3 illustrates the relationship between the TRIGRC and TRIGout sig nals.Tpically,the three pin combination is used to detect an event indicated by an increase of the TRIGin voltage from Vss to above the Schmitt trigger high going threshold VT+ (see DC electrical characteristics). Figure 3 shows a circuit to detect any one of three CLIP/CID call arrival indicators:line reversal,ring burst and ringing. VDD SC88E43 C1=100nF R1=499kΩ V3 Tip/A V1 V4 To determine values for C3 and R5: TRIGRC R5C3=-t/ln(1-VTRIGRC /VDD) C3=220nF Notes: The application circuit must ensure rhat, VTRIGin>max VT+ Where max VT+=3.74V @VDD=5.5V. Tolerance to noise between A/B and VSS is: max Vnoise=(min VT+)/[email protected] Suggested R5C3 component values: R5 from 10kΩ to 500kΩ; C3 from 47nF to 0.68µF An example is C3=220nF, R5=150kΩ; TRIGout low from 21.6ms to 37.6ms after TRIGin Signal stops triggering the circuit. R5=150kΩ R2=499kΩ R4=310kΩ C2=100nF Ring/B max VT+=0.68 VDD min VT+=0.48 VDD TRIGin R3=200kΩ TRIGout To Microcontroller Figure 3 Circuit to Detect Line Reversal, Ring Burst and Ringing 1.Line Reversal Detection Line reversal,or polarity reversal on the A and B wires indicates the arrival of an inconming CDScall,as soecified in SIN227.When the event (line reversal) occurs,TRIGin rises past the high going Schmitt threshold VT+ and TRIGou t ,which is normally high,is pulled low going Schmitt threshold VT- and TRIGout returns high.The components R5 and C3 (see Figure 3) at TRIGout low interval. In a TE designed for CLIP,the TRIGout high to low transition may be used to interrupt or wake-up the microcontroller.The controller can thus be put into power-down mode to conserve power in a battery operater TE. 2.Ring Buost Detection CCA doesnot support the dual tone alert signal (refer to Dual Tone Alert single burst og ringing (duration 200450ms) that precedes CLIPFSK data.The ring burst may vary fron 30 to 75Vrms and is approximately 25Hz. Again in aTEdesigned for CCA CLIP ,the TRIGou t high to low reansition may be used to interrupt or wake-up the microcontroller.The controller can thus be put into power-down mode to conserve powerin a battery operated TE. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 9 2000.12.31 Silan Semiconductors SC88E43 3.Ring Detection In Bellcore’s CND/CNAM scheme, the CID FSK data is transmitted between the first and second ringing cycles. The circuit in Figure 3 will generate a ring envelope signal (active low) at TRIGout for a ring voltage of at least 40Vrms. R5 and C3 filter the ring signal to provide an envelope output. The diode bridge shown in Figure 3 works for both single ended and balanced ringing. A fraction of the ring voltage is applied to the TRIGin input. When the voltage at TRIGin is above the Schmitt trigger high going threshold VT+ , TRIGRC is pulled low as C3 discharges. TRIGout stays low as long as the C3 voltage stays below the minimum VT+ . In a CPE designed for CND/CNAM, the TRIGout high to low transition may be used to interrupt or wake up the microcontroller. The controller can thus be put into power down mode to conserve power. If precise ring duration determination is critical, capacitor C3 in Figure 3 may be removed. The microcontroller will now be able to time the ring duration directly. The result will be that TRIGout will be low only as long as the ringing signal is present.Previously the RC time constant would cause only one interrupt. Dual Tone Alert Signal Detection The BT on hook (idle state) caller ID scheme uses a dual tone alert signal whose characteristics are shown in Table 1. Bellcore specifications for a similar dual tone signal called CPE Alerting Signal (CAS) for use in off-hook data transmission. For the CIDCW service, the CAS must be detected in the presence of near end speech. The CAS detector must also be immune to imitation from near and farend speech. Item BT Bellcore Low tone frequency 2130Hz ± 1.1% 2130Hz ± 0.5% High tone frequency 2750Hz ± 1.1% 2750Hz ± 0.5% -2dBV to –40dBV per tone on- -14dBm b to –32dBm per tone hook a (0.22dBm b to –37.78dBm) on-hook Received signal level Signal reject level Signal level differntial (twist) Unwanted signals Duration Speech present -46dBV (-43.78dBm) -45dBm Up to 7dB Up to 6dB ≤-20dB(300-3400Hz) ≤–7dBm ASL c near end speech 88ms to 110ms d 75ms to 85ms No Yes Table 1 Dual Tone Alert Signal Characteristics a. In the future BT may specify the off-hook signal level as –15dBm to –34dBm per tone for BT CIDcw. b. The signal power is expressed in dBm referenced to 600 ohm at the CPE A/B (tip/ring) interface. c. ASL = active speech level expressed in dBm referenced to 600 ohm at the CPE tip/ring interface. The level is measured according to method B of Recommendation P.56 "Objective Measurement of Active Speech Level" published in the CCITT Blue Book, volume V "Telephone Transmission Quality" 1989. EPL (Equivalent Peak Level) = ASL+11.7dB. d. SIN227 suggests that the recognition time should be not less than 20ms if both tones are detected. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 10 2000.12.31 Silan Semiconductors SC88E43 In the SC88E43 the dual tone signal is separated into a high and a low tone by two bandpass filters. A detection algorithm examines the two filter outputs to determine the presence of a dual tone alert signal. The ESt pin goes high when both tones are present. Note that ESt is only a preliminary indication. The indication must be sustained over the tone present guard time to be considered valid. Tone present and tone absent guard times can be implemented with external RC components. The tone present guard time rejects signals of insufficient duration. The tone absent guard time masks momentary detection dropout once the tone present guard time has been satisfied. StD is the guard time qualified detector output. Dual Tone Detection Guard Time When the dual tone signal is detected by the SC88E43, ESt goes high. When the signal ceases to be detected, ESt goes low. The ESt pin indicates raw detection of the dual tone signal. Since the BT application requires a minimum signal duration and the Bellcore application requires protection from imitation by speech, Est detection must be guard time qualified. The StD pin provides guard time qualified signal detection. When the SC88E43 is used in a caller identity system, StD indicates correct CAS/Tone Alert Signal detection. SC88E43 Figure 4 : Guard Time Circuit Operation VDD Tone detected P Q1 From detector C Figure 4 shows the relationship between the + - St/GT, ESt and StD pins. It also shows the St/GT VTGt operation of the guard time circuit. Comparator R SW1 N Q2 A =VSS B ESt VSS StD The total recognition time is tREC = tGP + tDP , where tGP is the tone present guard time and tDP is the tone present detect time (refer to timing between ESt, St/GT and StD in Figures 17 and 20). The total tone absent time is tABS = tGA + tDA , where tGA is the tone absent guard time and tDA is the tone absent detect time (refer to timing between ESt, St/GT and StD in Figures 17 and 20). Bellcore states that it is desirable to be able to turn off CAS detection for an off-hook capable CPE. The disable switch allows the subscriber who disconnects a service that relies on CAS detection (e.g., CIDCW) but retains the CPE, to turn off the detector and not be bothered by false detection. When SW1 in Figure 4 is in the B position the guard time circuit is disabled. The detector will still process CAS/Alerting tones but the SC88E43 will not signal their presence by ensuring that StD is low. BT specifies that the idle state tone alert signal recognition time should not be less than 20ms when both tones are used for detection. That is, both tones must be detected together for at least 20ms before the signal can be declared valid. This requirement can be met by setting the tGP (refer to Figure 5) to at least 20ms. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 11 2000.12.31 Silan Semiconductors SC88E43 BT also specifies that the TE is required to apply a DC wetting pulse and an AC load 15-25ms after the end of the alerting signal. If tABS =tDA +tGA is 15 to 25ms, the DC current wetting pulse and the AC load can both be applied at the falling edge of StD. The maximum tDA is 8ms so tGA should be 15-17ms. Therefore, tGP must be greater than tGA . Figure 5(a) shows a possible implementation. The values in Figures 9 and 11 (R2=R3=422K, C=0.1mF) will meet the BT timing requirements. SC88E43 VDD SC88E43 VDD 24 24 C St/GT C VD=diode forward voltage 23 St/GT VD=diode forward voltage 23 R1 R1 R2 R2 ESt 22 ESt 22 (a) t GP > tGA tGP=R1Cln[VDD/(VDD-VTG)] tGA=RpCln[(VDD-VD(Rp/R2))/(VTGt-VD(Rp/R2))] Rp=R1R2/(R1+R2) (b) t GP < tGA tGP=RpCln[(VDD-VD(Rp/R2))/(VDD-VTGt-VD(Rp/R2))] tGA=R1Cln[VDD/VTG)] Rp=R1R2/(R1+R2) Figure 5 Guard Time Circuits With Unequal Times Input Configuration The SC88E43 provides an input arrangement comprised of an operational amplifier, and a bias source (Vref ) which is used to bias the opamp inputs at VDD/2. The feedback resistor at the opamp output (GS) can be used to adjust the gain. In a single-ended configuration, the opamp is connected as shown in Figure 6. For a differential input configuration, Figure 7 shows the necessary connections. 1 2 C C IN+ 1 2 INC RIN GS R3 RF 4 Figure 6 Single Ended Input Configuration IN- 3 GS R2 Differental Input Amplifler C1=C2 R1R4 (For unity gain R5=R4) R3=(R2R5)/(R2+R5) Voltage Gain (AVdiff)=R5/R1 (see Figure 9,10,11) Input Impedance (ZINdiff)=2R12+(1/C)2 VRef IN+ R4 R5 3 Voltage Gain (AV) = RF/RIN R1 4 VRef Figure 7 Differential Input Configuration HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 12 2000.12.31 Silan Semiconductors SC88E43 FSK Demodulation The SC88E43 first bandpass filters and then demodulates the FSK signal. The carrier detector provides an indication of the presence of signal at the bandpass filter output. The SC88E43’s dual mode 3-wire interface allows convenient extraction of the 8-bit data words in the demodulated FSK bit stream. Note that signals such as CAS/Tone Alert Signal, speech and DTMF tones lie in the same frequency band as FSK. They will, therefore, be demodulated and as a result, false data will be generated. To avoid demodulation of false data, an FSKen pin is provided so that the FSK demodulator may be disabled when FSK signal is not expected. There are two events that if either is true, should be used to disable FSKen. The events are CD returning high or receiving all the data indicated by the message length word. Item Mark frequency (logic 1) Space frequency (logic 0) Received signal level-mark BT Bellcore 1300Hz ± 1.5% 1200Hz ± 1% 2100Hz ± 1.5% 2200Hz ± 1% -8dBV to –40dBV -12dBm a to –32dBm (-5.78dBm to –37.78dBm) Received signal level-space -8dBV to –40dBV -12dBm to –36dBm Signal level differntial (twist) Up to 6dB Up to 10dB b ≤-20dB (300-3400Hz) ≤–25dBm (0-4kHz) c Unwanted signals 1200baud ± 1% 1200baud ± 1% 1 start bit (logic 0), 8 bit word (LNB 1 start bit (logic 0), 8 bit word first), 1 to 10 stop bits (logic 1) (LNB first), 1 stop bits (logic 1) Transmission rate Word formate Table 2 FSK Charateristics a.The signal power is expressed in aBm referenced to 600Ω at the CPE tip/ring (A/B) interface. b.SR-3004, Issue 2, January 1995. c.The frequency range is specified in GR-30-CORE. d.Up to 20 marks may be inserted in specific places in a single or multiple data message. The FSK characteristics described in Table 2 shows the BT and Bellcore specifications. The BT frequencies correspond to CCITT v.23. The Bellcore frequencies correspond to Bell 202. The U.K.’s CCA requires that the TE be able to receive both CCITT v.23 and Bell 202 formats. The SC88E43 is compatible with both formats without any adjustment. 3-wire FSK Data Interface The SC88E43 provides a powerful dual mode 3-wire interface so that the 8-bit data words in the demodulated FSK bit stream can be extracted without the need either for an external UART or for the TE/CPE’s microcontroller to perform the UART function in software. The interface is specifically designed for the 1200 baud rate and is comprised of the DATA, DCLK (data clock) and DR (data ready) pins. Two modes (modes 0 and 1) are selectable via control of the device’s MODE pin: in mode 0, data transfer is initiated by the SC88E43; in mode 1, data transfer is initiated by the external microcontroller. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 13 2000.12.31 Silan Semiconductors Mode 0 SC88E43 This mode is selected when the MODE pin is low. In this mode, The SC88E43 receives the FSK signal, demodulates it, and outputs the data directly to the DATA pin (refer to Figure 14). For each received stop and start bit sequence, the SC88E43 outputs a fixed frequency clock string of 8 pulses at the DCLK pin. Each clock rising edge occurs in the centre of each DATA bit cell. DCLK is not generated for the stop and start bits. Consequently, DCLK will clock only valid data into a peripheral device such as a serial to parallel shift register or a micro-controller. The SC88E43 also outputs an end of word pulse (data ready) on the DR pin. The data ready signal indicates the reception of every 10-bit word (including start and stop bits) sent from the network to the TE/CPE. This DR signal can be used to interrupt a micro-controller. DR can also cause a serial to parallel converter to parallel load its data into a microcontroller. The mode 0 data pin can also be connected to a personal computer’s serial communication port after converting from CMOS to RS-232 voltage levels. Mode 1 This mode is selected when the MODE pin is high. In this mode, the microcontroller supplies read pulses (DCLK) to shift the 8-bit data words out of the SC88E43, onto the DATA pin. The SC88E43 asserts DR to denote the word boundary and indicate to the microprocessor that a new word has become available (refer to Figure 16). Internal to the SC88E43, the demodulated data bits are sampled and stored. After the 8th bit, the word is parallel loaded into an 8 bit shift register and DR goes low. The shift register’s contents are shifted out to the DATA pin on the supplied DCLK’s rising edge in the order they were received. If DCLK begins while DR is low, DR will return to high upon the first DCLK. This feature allows the associated interrupt (see section on "Interrupt") to be cleared by the first read pulse. Otherwise DR is low for half a nominal bit time (1/2400 sec). After the last bit has been read, additional DCLKs are ignored. Carrier Detector The carrier detector provides an indication of the presence of a signal in the FSK frequency band. It detects the presence of a signal of sufficient amplitude at the output of the FSK bandpass filter. The signal is qualified by a digital algorithm before the CD output is set low to indicate carrier detection. An 8ms hysteresis is provided to allow for momentary signal drop out once CD has been activated. CD is released when there is no activity at the FSK bandpass filter output for 8 ms. When CD is inactive (high), the raw output of the demodulator is ignored by the data timing recovery circuit (refer to Figure 1). In mode 0, the DATA pin is forced high. No DCLK or DR signal is generated. In mode 1, the internal shift register is not updated. No DR is generated. If the mode 1 DCLK is clocked, DATA is undefined. Note that signals such as CAS/Tone Alert Signal, speech and DTMF tones also lie in the FSK frequency band and the carrier detector may be activated by these signals. The signals will be demodulated and presented as data. To avoid false data detection, the FSKen pin should be used to disable the FSK demodulator when no FSK signal is expected. Ringing, on the other hand, does not pose a problem as it is ignored by the carrier detector. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 14 2000.12.31 Interrupt Silan Semiconductors SC88E43 To facilitate interfacing with microcontrollers running interrupt driven firmware, an open drain interrupt output INT is provided. INT is asserted when TRIGout is low, StD is high, or DR is low. When INT is asserted, these signals should be read (into an input port of the microcontroller) to determine the cause of the interrupt ( TRIGout , StD or DR ) so that the appropriate response can be made. When system power is first applied, TRIGout will be low because capacitor C3 at TRIGRC (see Figure 3) has no initial charge. This will result in an interrupt upon power up. Also when system power is first applied and the PWDN pin is low, an interrupt will occur due to StD. Since there is no charge across the capacitor at the St/GT pin in Figure 4, StD will be high triggering an interrupt. The interrupts will not clear until both capacitors are charged. The microcontroller should ignore interrupt from these msources on initial power up until there is sufficient time to charge the capacitors. It is possible to clear StD and its interrupt by asserting PWDN immediately after system power up. When PWDN is high, StD is low. PWDN will also force both ESt and the comparator output low, Q2 will turn on so that the capacitor at the St/GT pin charges up quickly (refer to Figure 4). Power Down Mode For applications requiring reduced power consumption, the SC88E43 can be powered up only when it is required, that is, upon detection of one of three CLIP/CID call arrival indicators: line reversal, ring burst and ringing. The SC88E43 is powered down by setting the PWDN pin to logic high. In power down mode, the oscillator, input opamp and all internal circuitry are disabled except for TRIGin, TRIGRC and TRIGou t pins. These three pins are not affected by power down, such that, the SC88E43 can still react to call arrival indicators. The SC88E43 can be powered up by setting the PWDN pin to logic low. Crystal Oscillator The SC88E43 requires a 3.579545MHz crystal oscillator as the master timing source. The crystal specification is as follows : SC88E43 OSCI OSCO 10 11 SC88E43 OSCI OSCO 10 11 3.579545 MHz SC88E43 OSCI OSCO 10 11 to the next SC88E43 Figure 8 Common Crystal Connection Frequency: Frequency tolerance: 3.579545 MHz ±0.1%(-40 o C+85 o C) Resonance mode: Parallel Load capacitance: 18 pF Maximum series resistance: 150 ohms Maximum drive level (mW): 2 mW Any number of SC88E43 devices can be connected as shown in Figure 8 such that only one crystal is required. The connection between OSC2 and OSC1 can be DC coupled as shown, or the OSC1 input on all devices can be driven from a CMOS buffer (dc coupled) with the OSC2 outputs left unconnected. To meet BT and Bellcore requirements for proper tone detection the crystal must have a frequency tolerance of 0.1%. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 15 2000.12.31 Silan Semiconductors SC88E43 VRef and CAP Inputs VRef is the output of a low impedance voltage source equal to VDD/2 and is used to bias the input opamp. A 0.1mF capacitor is required between CAP and VSS to eliminate noise on VRef. VDD VDD 1N4003 TIP /A R1 100nF R4 1 IN+ 22nF 5% 53K6 VDD 1N4003 R1 R4 1N4003 464K 22nF 5% RING / B VDD 499K 5% 100nF 5% 200K 5% 150K 5% VDD 1N914 x 4 2 IN- St/GT 23 3 GS ESt 22 4 Vref StD 21 5 CAP INT 20 6 TRIGin CD 19 7 TRIGRC DR 18 8 TRIGout DATA 17 9 MODE DCLK 16 10 OSCin FSKen 15 11 OSCout PWDN 14 VDD R3 464K 60K4 TISP 4180 VDD 24 C 1N4003 100K 20% R2 1N914 499K 5% 301K 5% 220nF 100nF 100nF 5% 12 VSS IC 13 SC88E43 Note:Resistors must have 1% tolerance and capacitors have 20% tolerance unless otherwise specified. Crystal is 3.579545MHz, 0.1% frequency tolerance. For BT Application C=0.1F5%, R3=422k1%, R2=422k1%. For Applications where CAS speech immunity is required(e.g.CIDCW), C=0.1F5%, R3=825k1%, R2=226k 1%. R1=430k, R4=34k for VDD=5V10% (See Figure 10) R1=620k, R4=63k4 for VDD=3V10% (See Figure 10) Figure 9- Application Circuit Application Circuits The circuits shown in Figures 9 and 11 are application circuits for the SC88E43. As supply voltage (VDD ) is decreased, the threshold of the device’s tone and FSK detectors will be reduced. Therefore, to meet the BT or Bellcore tone reject level requirements the gain of the input opamp should be reduced according to the graph in HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 16 2000.12.31 Silan Semiconductors SC88E43 Figure 10. For example when VDD =5V (+/- 10%), R 1 should equal 430kW and R4 should equal 34kW; and if VDD =3V (+/- 10%) R1 should equal 620kW and R 4 should equal 63.4kW. Resistors R1 and R4 are shown in Figures 9 and 11. The circuit shown in Figure 9 illustrates the use of the SC88E43 in a proprietary system that doesn’t need to meet FCC, DOC, and UL approvals. It should be noted that if glitches on the Tip/Ring interface are of sufficient amplitude, the circuit will falsely detect these signals as ringing or line reversal. The circuit shown in Figure 11 will provide common mode rejection of signals received by the ringing circuit. This circuit should pass safety related tests specified by FCC Part 68, DOC CS-03, UL 1459, and CSA C22.2. These safety tests will simulate high voltage faults that may occur on the line. The circuit provides isolation from these high voltage faults via R1 and the 12.1kWresistors as well as the 22nF & 330nF capacitors. IRC manufactures a resistor (part number GS3) that should be used for R1. This resistor is a 3W, 5%, 1kV power resistor. The 12k1 resistor is manufactured by IRC (part number FA8425F). This resistor is a 1.5W, 5%, fuseable type resistor. The 22nF and 330nF capacitors have a 400V rating. 1 0.95 0.9 Gain Ratio 0.85 0.8 0.75 0.7 0.678 0.65 0.6 2 2.5 3 3.5 4 4.5 5 5.5 6 Nominal VDD (Volts) Figure 10: Gain Ratio as a function of Nominal VDD Note: In the application circuits shown in Figure9 and 11, the Gain ratio of SC88E43 opamp is: Gain Ratio=464k/(R1+R4) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 17 2000.12.31 Silan Semiconductors SC88E43 VDD VDD 1N4003 TIP /A R1 R4 100nF 1 IN+ 22nF 5% C 53K6 VDD 1N4003 R1 22nF 5% R4 1N4003 2 IN- St/GT 23 3 GS ESt 22 4 Vref StD 21 5 CAP INT 20 6 TRIGin CD 19 7 TRIGRC DR 18 8 TRIGout DATA 17 VDD R3 464K VDD 100K 20% R2 1N914 1N914 X 4 100nF 10% 1N5231B 330nF 10% 12K1 5% 4N25 VDD 150K 5% RING / B 60K4 1N4003 TISP 4180 VDD 24 200K 5% 10nF 100nF 464K 5% 220nF VDD 9 MODE DCLK 16 10 OSCin FSKen 15 11 OSCout PWDN 14 12 VSS IC 13 SC88E43 Note: Please use 0.068µF, 1500pF Mylar Capacitors. Note:Resistors must have 1% tolerance and capacitors have 20% tolerance unless otherwise specified. Crystal is 3.579545MHz, 0.1% frequency tolerance. For BT Application C=0.1F5%, R3=422k1%, R2=422k1%. For Applications where CAS speech immunity is required(e.g.CIDCW), C=0.1F5%, R3=825k1%, R2=226k 1%. R1=430k, R4=34k for VDD=5V10% (See Figure 10) R1=620k, R4=63k4 for VDD=3V10% (See Figure 10) Figure 11:Application Circuit with Improved Common Mode Noise Immunity and Isolation in Line Interface Approvals Fcc Part 68,DOC CS-03,UL1459,and CAN/CSA-22.2 No.225-M90 are all system(i.e. connectors,power supply,cabinet,ect.) requirements. Since the SC88E43 is a component and not a system, the application circuit (Figure 11) has been designed to meet the CO Trunk interface requirments of FCC,DOC,UL, and CSA; thus enabling the complete system to be approved by these standards bodies. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 18 2000.12.31 Silan Semiconductors SC88E43 tDCD tCDD VHM VCT VLM DATA tR tF VHM VCT VLM DCLK tCL tCH tR tF Figure 12: DATA and DCLK Mode 0 Output Timing tRF tRR VHM VCT VLM DR tRL Figure 13: DR Output Timing TIP/RING (A/B) WIRES start stop b7 1 start stop 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 b2 tIDD start DATA start stop b7 start start b0 b1 b2 b3 b4 b5 b6 b7 stop b0 b1 b2 b3 b4 b5 b6 b7 stop 1/fDCLC0 b0 b1 b2 stop DCLK tRL tCRD DR Figure 14: Serial Data Interface Timing (MODE 0) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 19 2000.12.31 Silan Semiconductors SC88E43 VHM VCT VLM DCLK tR1 Figure 15: DCLK Mode 1 Input Timing word N Demodulated internal bit stream 7 word N+1 stop start 0 1 2 3 4 5 6 7 stop tRL DR 1 2 tDDS tDDH 1/fDCLK1 DCLK DATA 6 7 0 1 2 3 4 5 6 7 word N-1 0 word N 1 DCLK clears DR 2 DCLK does not clear DR , so DR is low for maximum time (1/2 bit width) Figure 16: Serial Data Interface Timing (MODE 1) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 20 2000.12.31 Silan Semiconductors SC88E43 Alerting Signal Line Reversal A/B Wires A B Ch.seizure Mark Data Packet D E F C Ring G TRIGout PWDN ESt Note 6 Note 1 Note 2 tDP tDA tGP tGA VTGt tREC tABS St/GT 50--150mS Note 3 STD 15+/-1mS TE DC load <0.5mA (optional) <120uA Current wetting pulse (see SIN227) 20+/-5mS TE AC load Zss (Refer to SIN227) Note 4 FSKen Note 5 tCP tCA CD DR DCLK DATA tPU 101010 Data tPD OSCout A>=100mS B=88--110mS C>=45mS (up to 5sec) D=80--262mS E=45--75mS F<=2.5S (typ.500mS) G>200mS Note: All values obtained from SIN227 Issue 1 Figure 17: Input and Output Timing for BT Caller Display Service(CDS), e.g.,CLIP Note: 1) The total recognition time is tREC=tGP+tDR,where TGP is the tone present guard time and tDP is the tone present detect time (refer to section “Dual Tone Detection Time” on page 11 for details). VTGt is the comparator threshold (refer to Figure 4). 2) The total tone absent time is tABS=tGA+tDA, where tGA is the tone absent guard time and tDA is the tone absent detect time (refer to section ” Dual Tone Detection Time” on page 11 for details). VTGt is the comparator threshold (refer to Figure 4). 3) By choosing tGA=15mS, tABS will be 15—25 mS so that the current wetting pulse and AC load can be applied right after the StD falling edge. 4) SIN227 spedifies that the AC and DC loads should be removed between 50—150 mS after the end of the FSK signal, indicated by CD returning to high. The SC88E43 may also be powered down at this time. 5) FSKen should be set low when FSK is not expected to prevent the FSK demodulator from reacting to other in-band signals such as speech, tone alert signal and DTMF tones. 6) TRIGou t is the ring envelope during ringing. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 21 2000.12.31 Silan Semiconductors Line Reversal Ring Burst First Ring Cycle A/B Wires A TRIGout SC88E43 B Ch.seizure Mark Data Packet C D E Note 3 F Note 3 50--150mS PWDN TE DC load 250--400mS TE AC load Note 1 FSKen Note 2 tCP tCA CD A=200-450mS B>=500mS C=80--262mS D=45--262mS E<=2.5S (type. 500mS) F>200mS DR DCLK DATA tPU 101010 Data tPD OSCout Note: Parameter F from " CCA Exceptions Document Issue 3" Figure 18: Input and Output Timing for CCA Caller Display Service(CDS), e.g.,CLIP Note: 1. TW/P&E/312 specifies that the AC and DC loads should be removed between 50 to 150 mS after the end of the FSK signal, indicated by The CD returning to high. The SC88E43 may also be powered down at this time. 2. FSKen should be set low when FSK is not expected to prevent the FSK demodulator from reacting to other in-band signals such as speech,and DTMF tones. 3. TRIGou t represents the ring envelop during ringing. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 22 2000.12.31 Silan Semiconductors A/B Wires 1st Ring A B SC88E43 Ch.seizure Mark Data Packet C D E 2nd Ring F TRIGout Note 4 PWDN Note 1 Note 3 tPU Note 1 tPD OSCout FSKen Note 2 tCP tCA CD DR DCLK DATA 101010 Data A=2 sec typical B=250--500mS C=250mS D=150mS E=feature specific Max C+D+E=2.9 to 3.7 sec F>=200mS Figure 19: Input and Output Timing for Bellcore On-hook Data Transmission Associated with Ringing,e.g.,CID Note: This on-hook case application is included because a CIDCW (off-hook) CPE should also be capable of receiving on-hook data transmission (with ringring) from the end office. TR-NWT-000575 specifies that CIDCW will be offered only to lines which subscribe to CID 1. The CPE designer may choose to enable the SC88E43 only after the end of ringing to conserve power in a battery operated CPE. CD is not activated by ringing. 2. The CPE designer may choose to set FSKen always high while the CPE is on-hook. Setting FSKen low prevents the FSK demodulator from reacting to other in-band signals such as speech,CAS or DTMF tones. 3. The microcontroller in the CPE powers down the SC88E43 after CD has become inactive. 4. The microcontroller times out if CD is not activated. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 23 2000.12.31 Silan Semiconductors CPE goes off-hook A/B Wires CPE sends ACK A B C PWDN FSKen OSCout CPE unmutes handset and enables keypad CPE mutes hangset & disables keypad CAS Note 1 SC88E43 Note 2 D Note 5 Mark Data Packet E F Note 3 G Note 4 tPU tCP ESt St/GT tDP tDA tGP tGA VTGt tREC tABS Note 7 Note 8 STD (Note 6) tCP tCA CD DR DCLK DATA Data A=75--85mS B=0--100mS C=55--65mS D=0-500mS E=58--75mS F=feature specific G<50mS Figure 20: Input and Output Timing for Bellcore off-hook Data Transmission,e.g., CIDCW Note: 1. In a CPE where AC power is not available, the designer may choose to switch over to line power when the CPE goes off-hook and use battery power while on-hook. The CPE should also be CID (on-hook) capable because TR-NWT-000575 specifies that CIDCW will be offered only to lines which subscribe to CID. 2. Non-FSK signals such as CAS, speech and DTMF tones are in the same frequency band as FSK. They will be demodulated and give false data. The FSKen pin should be set low to disable the FSK demodulator when FSK is not expected. 3. FSKen may be set high as soon as the CPE has finished sending the acknowledgment signal ACK. TR-NWT-000575 specifies that ACK=DTMF D for non-ADSI CPE, A for ADSI CPE. 4. FSKen should be set low when CD has become inactive. 5. In an unsuccessful attempt where the end office does not send the FSK signal, the CPE should unmute the handset and enable the keypad after this interval. 6. SR-TSV-002476 states that it is desirable that the CPE have an on/off switch for the CAS detector. See SW1 in Figure 4. 7. The total recognition time is tREC=tGP+tDR,where TGP is the tone present guard time and tDP is the tone present detect time (refer to section “Dual Tone Detection Time” on page 11 for details). VTGt is the comparator threshold (refer to Figure 4). 8. The total tone absent time is tABS=tGA+tDA, where tGA is the tone absent guard time and tDA is the tone absent detect time (refer to section ” Dual Tone Detection Time” on page 11 for details). VTGt is the comparator threshold (refer to Figure 4). HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 24 2000.12.31 Silan Semiconductors SC88E43 PACKAGE OUTLINE DIP-24-600-2.54 UNIT:mm 15.24 13.60 0.25 2.54 1.50 15 degree 3.30 5.08 3.85 32.04 0.46 1.27 9.53 7.70 UNIT:mm 10.45 SOP-24-375-1.27 0.41 15.74 1.95 15.34 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.0 25 2000.12.31