CMOS MT8843 Calling Number Identification Circuit 2 Preliminary Information Features ISSUE 1 • Compatible with British Telecom (BT) SIN227 & SIN242, Cable Television Association (CTA) TW/P&E/312, and Bellcore TR-NWT-000030 & SR-TSV-002476 • Ring and line reversal detection • Bellcore "CPE Alerting Signal (CAS)" and BT "Idle State Tone Alert Signal" detection • 1200 baud BELL 202 and CCITT V.23 Frequency Shift Keying (FSK) demodulation • High input sensitivity • Dual mode 3-wire data interface • Low power CMOS with powerdown mode • Input gain adjustable amplifier • Carrier detect status output • Uses 3.58 MHz crystal or ceramic resonator Applications • BT Calling Line Identity Presentation (CLIP), CTA CLIP, and Bellcore Calling Identity Delivery (CID) systems • Feature phones, including Analog Display Services Interface (ADSI) phones • Phone set adjunct boxes • FAX and answering machines • Database query and Computer Telephony Integration (CTI) systems Ordering Information MT8843AE 24 Pin Plastic DIP MT8843AS 24 Pin SOIC -40 °C to +85 °C Description The MT8843 Calling Number Identification Circuit 2 (CNIC2) is a low power CMOS integrated circuit intended for receiving physical layer signals transmitted according to BT (British Telecom) SIN227 & SIN242, CTA (Cable TV Association) TW/ P&E/312 and Bellcore TR-NWT-000030 & SR-TSV002476 specifications. The CNIC2 provides all the features and functions offered by Mitel’s MT8841 (CNIC), including 1200 baud BELL 202 and CCITT V.23 FSK demodulation. The 3-wire serial FSK interface provided by CNIC has been enhanced to operate in two modes. The first mode is the CNIC compatible mode whereby data transfer is initiated by the device. The new, second mode allows a microcontroller to extract 8-bit data words from the device. Furthermore, CNIC2 offers Idle State Tone Alert Signal and line reversal detection capability for BT’s CLIP, ring burst detection for CTA’s CLIP, and ring detection for Bellcore’s CID. MODE FSKen IN+ INGS VRef + - Anti-alias Filter FSK Bandpass Filter FSK Demodulator Data Timing Recovery To internal cct. Interrupt Generator Alert Signal High Tone Filter Tone Detection Algorithm To internal cct. Alert Signal Low Tone Filter DCLK DATA DR CD Carrier Detector Bias Generator CAP PWDN February 1995 Guard Time INT StD St/GT ESt VDD VSS Oscillator OSCin OSCout TRIGin TRIGRC TRIGout Figure 1 - Functional Block Diagram 5-21 MT8843 Preliminary Information Pin Description Pin # Name Description 18 DR 3-wire FSK Interface Data Ready (CMOS Output). Active low.This output goes low after the last DCLK pulse of each word. This identifies the data (8-bit word) boundary on the serial output stream. Typically, DR is used to latch 8-bit words from the serial-to-parallel converter into a microcontroller. 19 CD Carrier Detect (CMOS Output). Active low. A logic low indicates the presence of in-band signal at the output of the FSK bandpass filter. 20 INT Interrupt (Open Drain Output). Active low. It is active when TRIGout or DR is low, or StD is high. This output stays low until all three signals have become inactive. 21 StD Dual Tone Alert Signal Delayed Steering Output. When high, it indicates that a guard time qualified alert signal has been detected. 22 ESt Dual Tone Alert Signal Early Steering Output. Alert signal detection output. Used in conjunction with St/GT and external circuitry to implement detect and non-detect guard times. 23 St/GT 24 V DD Dual Tone Alert Signal Steering Input/Guard Time (Analog Input/CMOS Output). A voltage greater than V TGt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than V TGt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. Positive Power Supply. Functional Overview The MT8843 Calling Number Identification Circuit 2 (CNIC2) is a device compatible with BT, CTA and Bellcore specifications. As shown in Figure 1, CNIC2 provides an FSK demodulator as well as a 3-wire serial interface similar to that of it’s predecessor, the MT8841 (CNIC). The 3-wire interface has been enhanced to provide two modes of operation - a mode whereby data transfer is initiated by the device and a mode whereby data transfer is initiated by an external microcontroller. In addition to supporting all the features and functions offered by MT8841, CNIC2 provides line reversal detection, ring detection and dual tone alert signal detection capability. These new functions eliminate some external application circuitry previously required with the MT8841 (CNIC). SIN227 and SIN242 specify the signalling mechanism between a network and a Terminal Equipment (TE) providing Caller Display Service (CDS). CDS provides Calling Line Identity Presentation (CLIP), that is, delivery of the identity of the caller when a telephone call arrives, before the start of ringing (in the Idle State). An incoming CDS call is indicated by a polarity reversal on the A and B wires (line reversal), followed by an Idle State Tone Alert Signal. CNIC2 has the capability to detect both the reversal and alert signal as well as to receive and demodulate the incoming CCITT V.23 FSK signals. TW/P&E/312 proposes an alternate CDS TE interface available for use in the CTA network. According to TW/P&E/312, data is transmitted after a single burst of ringing rather than before the first ringing cycle (as specified in SIN227). The Idle State Tone Alert Signal is not required as it is replaced with a single ring burst. CNIC2 has the capability to detect the ring burst. It is also able to demodulate either Bell-202 or CCITT V.23 FSK data following the ring burst, as specified by the CTA. TR-NWT-000030 specifies generic requirements for transmitting asynchronous voiceband data to Customer Premises Equipment (CPE). SR-TSV002476 describes the same requirements from the CPE’s perspective. The data transmission technique specified in both documents is applicable in a variety of services like Calling Number Delivery (CND), Calling Name Delivery (CNAM) and Calling Identity Delivery on Call Waiting (CIDCW) - services promoted by Bellcore. In CND/CNAM service, information about a calling party is embedded in the silent interval between the first and second ring. CNIC2 detects the first ring and can then be setup to receive and demodulate the incoming Bell-202 FSK data. The device will output the demodulated data onto a 3-wire serial interface. 5-23 MT8843 Preliminary Information The diode bridge shown in Figure 3 half wave rectifies a single ended ring signal. Full wave rectification is achieved if the ringing is balanced. A fraction of the ring voltage is applied to the TRIGin input. When the voltage at TRIGin is above the Schmitt trigger high going threshold V T+, TRIGRC is pulled low as C3 discharges. TRIGout stays low as long as the C3 voltage stays below the minimum VT+. In a CPE designed for CND/CNAM, TRIGout high to low transition may be used to interrupt or wake up the microcontroller. The controller can thus be put into sleep mode to conserve power. Dual Tone Alert Signal Detection According to SIN227 the Idle State Tone Alert Signal allows more reliable detection of Caller Display Service signals. The Idle State Tone Alert Signal follows the line reversal and a silence period. The characteristics of the BT’s idle state alerting tone is shown in Table 1. Item BT Bellcore Low tone frequency 2130Hz ±1.1% 2130Hz± 0.5% High tone frequency 2750Hz±1.1% 2750Hz±0.5% Received signal level -2dBV to -40dBV -14dBm to -32dBm per tone on-hooka per tone off-hook (0.22dBmb to -37.78dBm) Signal reject level -46dBV (-43.78dBm) -45dBm Signal level differential (twist) up to 7dB up to 6dB Unwanted signals Bellcore specifies a similar dual tone alert signal called CPE Alerting Signal (CAS) for use in off-hook data transmission. Bellcore states that the CPE should be able to detect, in the presence of voice, the CPE Alerting Signal. The dual tone alert signal is separated into the high and low tones with two bandpass filters. A detection algorithm examines the two filter outputs to determine the presence of a dual tone alert signal. The ESt pin goes high when both tones are present. Detect and non-detect guard times can be implemented with external RC components. The guard times improve detection performance by rejecting signals of insufficient duration and masking momentary detection dropout. StD is the guard time qualified detector output. • Dual Tone Detection Guard Time When the dual tone alert signal is detected by the CNIC2, ESt is pulled high. When the alerting signal ceases to be detected, ESt goes low. Figure 4 shows the relationship between the St/GT, ESt and StD pins. It also shows the operation of a guard time circuit. The guard time circuit improves detection performance by rejecting detections of insufficient duration and by allowing momentary ESt dropouts once the duration criterion has been met. The total recognition time is t REC = tGP + t DP, where tGP is the tone present guard time and tDP is the tone present detect time (refer to timing between ESt, St/ GT and StD in Figures 15 and 18). The total tone absent time is tABS = tGA + tDA, where tGA is the tone absent guard time and tDA is the tone absent detect time (refer to timing between ESt, St/ GT and StD in Figures 15 and 18). c <= -20dB (300-3400Hz) <= -7dBm ASL near end speech Duration 88ms to 110msd 75ms to 85ms Speech present No Yes Table 1. Dual Tone Alert Signal Characteristics a. The off-hook signal level is -15dBm to -34dBm per tone to be specified in the BT CIDCW specification in the future. b. The signal power is expressed in dBm referenced to 600 ohm at the CPE A/B (tip/ring) interface. c. ASL = active speech level expressed in dBm referenced to 600 ohm at the CPE tip/ring interface. The level is measured according to method B of Recommendation P.56 "Objective Measurement of Active Speech Level" published in the CCITT Blue Book, volume V "Telephone Transmission Quality" 1989. EPL (Equivalent Peak Level) = ASL+11.7dB d. SIN227 suggests that the recognition time should be not less than 20ms if both tones are detected. Bellcore states that it is desirable for an off-hook capable CPE to have a CAS detector on/off switch. The switch was conceived so that a subscriber who disconnects a service that relies on CAS detection (e.g., CIDCW), but retains the CPE, can turn off the detector and not be bothered by false detection. SW1 in Figure 4 performs the above function. In the B position, the comparator input, hence StD, is always low. The CAS detector will not be enabled and its output will not cause interrupts (except for the system power up condition described in section “Interrupt” on page 28’). BT states that the idle state tone alert signal recognition time should be no less than 20ms when 5-25 MT8843 Preliminary Information Note that signals such as dual tone alert signal, speech and DTMF tones lie in the same frequency band as FSK. They will, therefore, be demodulated and as a result, false data will be generated. To avoid demodulation of false data, an FSKen pin is provided so that the FSK demodulator may be disabled when FSK signal is not expected. The FSK characteristics described in Table 2 have been specified in BT and Bellcore specifications. The BT signal frequencies correspond to CCITT V.23. The Bellcore frequencies correspond to Bell 202. CTA requires that the TE be able to receive both CCITT V.23 and Bell 202, as specified in the BT and Bellcore specifications. CNIC2 is compatible with both formats with no external intervention. Item BT Bellcore Mark frequency (logic 1) 1300Hz ± 1.5% 1200Hz ± 1% Space frequency (logic 0) 2100Hz ± 1.5% 2200Hz ± 1% Received signal level mark -8dBV to -40dBV (-5.78dBm to -37.78dBm) -12dBma to -32dBm Received signal level space -8dBV to -40dBV -12dBm to -36dBm Signal level differential (twist) up to 6dB up to 10dBb <= -20dB (300-3400Hz) <= -25dB (200-3200Hz)c Transmission rate 1200 baud ± 1% 1200 baud ± 1% Word format 1 start bit (logic 0), 8 bit word (LSB first), 1 to 10 stop bits (logic 1) 1 start bit (logic 0), 8 bit word (LSB first), 1 stop bit (logic 1)d Unwanted signals Table 2. FSK Characteristics a. The signal power is expressed in dBm referenced to 600 ohm at the CPE tip/ring (A/B) interface. b. TR-NWT-000030, Bulletin No. 1 c. The frequency range is specified in TR-NWT-000030. d. Up to 20 marks may be inserted in specific places in a single or multiple data message. CNIC2 will meet these characteristics with its input op-amp at unity gain. • 3-wire User Interface The MT8843 provides a powerful dual mode 3-wire interface so that the 8-bit data words in the demodulated FSK bit stream can be extracted without the need either for an external UART (Universal Asynchronous Receiver Transmitter) or for the TE/CPE’s microcontroller to perform the UART function in software (asynchronous serial data reception). The interface is specifically designed for the 1200 baud rate and is comprised of the DATA, DCLK (data clock) and DR (data ready) pins. Two modes (modes 0 and 1) are selectable via control of the device’s MODE pin: in mode 0, data transfer is initiated by the CNIC2; in mode 1, data transfer is initiated by the external microcontroller. Mode 0 This mode is selected when the MODE pin is low. It is the CNIC (MT8841) compatible mode where data transfer is initiated by the device. In this mode, CNIC2 receives the FSK signal, demodulates it, and outputs the extracted data to the DATA pin (refer to Figure 12). For each received stop and start bit sequence, the CNIC2 outputs a fixed frequency clock string of 8 pulses at the DCLK pin. Each clock rising edge occurs in the centre of each DATA bit cell. DCLK is not generated for the stop and start bits. Consequently, DCLK will clock only valid data into a peripheral device such as a serial to parallel shift register or a micro-controller. CNIC2 also outputs an end of word pulse (data ready) at the DR pin. The data ready signal indicates the reception of every 10-bit word sent from the network to the TE/ CPE. This DR signal is typically used to interrupt a micro-controller. Mode 1 This mode is selected when the MODE pin is high. In this mode, the microcontroller supplies read pulses (DCLK) to shift the 8-bit data words out of the MT8843, onto the DATA pin. CNIC2 asserts DR to denote the word boundary and indicate to the microprocessor that a new word has become available (refer to Figure 14). Internally, the MT8843’s demodulated data bits are sampled and stored. After the 8th bit, the word is parallel loaded into an 8 bit shift register and DR goes low. The shift register’s contents are shifted out to the DATA pin on DCLK’s rising edge in the order they were received. If DCLK begins while DR is low, DR will return to high upon the first DCLK. This feature allows the associated interrupt (see section on "Interrupt") to be 5-27 MT8843 Preliminary Information The crystal specification is as follows: Applications Frequency: Frequency tolerance: Resonance mode : Load capacitance: Maximum series resistance : Maximum drive level (mW): e.g., CTS MP036S The circuit shown in Figure 9 illustrates the use of the MT8843 (CNIC2) device in a typical CID or CLIP system. Network protection will differ depending on the market for which the product is designed. 3.579545 MHz ±0.1%(-40°C+85°C) Parallel 18 pF 150 ohms 2 mW Notes: CNIC2 has not been fully characterized for talkoff and talkdown performance as specified in SR-TSV002476. Any number of MT8843 devices can be connected as shown in Figure 8 such that only one crystal is required. The connection between OSC2 and OSC1 can be D.C. coupled as shown, or the OSC1 inputs on all devices can be driven from a CMOS buffer (dc coupled) with the OSC2 outputs left unconnected. For CIDCW, speech immunity improves if near end audio is cancelled from the incoming signal. One possible implementation is to connect the signal input to the 2 wire side when the CPE is on-hook and the 4 wire side when the CPE is off-hook. VRef and CAP Inputs VRef is the output of a low impedance voltage source equal to VDD/2 and is used to bias the input op-amp. A 0.1µF capacitor is required between CAP and VSS to suppress noise on VRef. +5V +5V MT8843 CNIC2 0.01µF 430K RING / B 34K 60K4 +5V +5V 0.01µF 500K 0.1µF 200K C R 300K 0.1µF 0.1µF 0.33µF 500K 500K 464K 0.1µF For BT network protection: TISP4180, TISP5180, TPA150A12 or TPB150B12 34K 53K6 Notes 430K IN+ VDD IN- St/GT GS ESt VRef StD CAP INT TRIGin CD TRIGRC DR TRIGout DATA MODE DCLK OSCin FSKen OSCout PWDN VSS 420K 0.1µF TIP / A +5V 100K 420K IC = To microcontroller Note: For CTA applications where there is a requirement to determine the ring burst duration, the value of R and C may have to be optimized. = From microcontroller (FSK Interface Mode 0 selected) Figure 9 - Application Circuit 5-29 MT8843 Preliminary Information DC Electrical Characteristics† Characteristics 8 TRIGout, DCLK, DATA, DR, CD, StD, ESt , St/GT TRIGRC, INT 9 IN+, IN-, TRIGin Sym Min Output Low Sinking Current IOL 2.5 Input Current Iin1 PWDN, DCLK, MODE, FSKen 10 TRIGRC 11 INT 12 St/GT 13 VRef 14 St/GT Output High-Impedance Current Max Units Test Conditions mA VOL=0.1*VDD 1 µA Vin=VDD or VSS See Note 1 Iin2 10 µA Vin=VDD or VSS See Note 1 Ioz1 1 µA Ioz2 10 µA Vout =VDD or VSS See Note 1 Ioz3 5 µA Output Voltage VRef 0.5VDD 0.05 0.5VDD+ 0.05 V Comparator Threshold Voltage VTGt 0.5VDD0.05 0.5VDD+ 0.05 V No Load † DC Electrical Characteristics are over recommended operating conditions unless otherwise stated. Note 1 - Magnitude measurement, ignore signs. 5-31 MT8843 Preliminary Information Electrical Characteristics† - Gain Setting Amplifier Characteristics Sym Min Typ‡ Max Units 1 µA Test Conditions VSS ≤ VIN ≤ VDD 1 Input Leakage Current IIN 2 Input Resistance Rin 3 Input Offset Voltage VOS 4 Power Supply Rejection Ratio PSRR 40 dB 1kHz ripple on VDD 5 Common Mode Rejection CMRR 40 dB VCMmin ≤ VIN ≤ VCMmax 6 DC Open Loop Voltage Gain AVOL 32 dB 7 Unity Gain Bandwidth fC 0.3 MHz 8 Output Voltage Swing VO 9 Maximum Capacitive Load (GS) CL 10 MΩ 25 0.5 10 Maximum Resistive Load (GS) RL 50 11 Common Mode Range Voltage VCM 1.0 mV VDD-0.5 Vpp 100 pF Load ≥ 50kΩ kΩ VDD-1.0 V † Electrical characteristics are over recommended operating conditions, unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. AC Electrical Characteristics† - FSK Detection Characteristics Sym 1 Input Detection Level Min Typ‡ Max Units -8 dBVa 1 -5.78 dBmb 398.1 mVrms -40 -37.78 10.0 2 Transmission Rate 1188 1200 1212 baud 3 Input Frequency Detection Bell 202 1 (Mark) Bell 202 0 (Space) 1188 2178 1200 2200 1212 2222 Hz Hz CCITT V.23 1 (Mark) CCITT V.23 0 (Space) 4 Input Noise Tolerance SNRFSK Notes* 1280.5 1300 1319.5 2068.5 2100 2131.5 Hz Hz 20 dB 1,2 a. dBV = decibels above or below a reference voltage of 1Vrms. b. dBm = decibels above or below a reference power of 1mW into 600 ohms. 0dBm = 0.7746Vrms. *Notes 1. Both mark and space have the same amplitude. 2. Band limited random noise (200-3400Hz). Present when FSK signal is present. Note that the BT band is 300-3400Hz, the Bellcore band is 200-3200Hz. † AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 5-33 MT8843 Preliminary Information tCDD tDCD tDH, tDL tR tF DATA VHM VCT VLM DCLK VHM VCT VLM tCL tCH tR tF Figure 10 - DATA and DCLK Mode 0 Output Timing* * VHM=0.7*VDD, VLM=0.3*VDD, VCT =0.5*VDD tRR tRF VHM VCT VLM DR tRL Figure 11 - DR Output Timing* * VHM=0.7*VDD, VLM=0.3*VDD, VCT =0.5*VDD start stop A/B WIRES b7 1 0 start stop b0 b1 b2 b3 b4 b5 b6 b7 1 start stop b0 b1 b2 b3 b4 b5 b6 b7 0 1 0 b0 b1 b2 tIDD start DATA start b0 b1 b2 b3 b4 b5 b6 b7 b7 stop start b0 b1 b2 b3 b4 b5 b6 b7 stop b0 b1 b2 stop 1/fDCLK0 DCLK tRL tCRD DR Figure 12 - Serial Data Interface Timing (MODE 0) 5-35 MT8843 Preliminary Information Alerting Signal Line Reversal Ch. seizure A/B Wires A B C D Mark E Ring Data Packet F G TRIGout Note 4 PWDN tDA tDP ESt Note 6 Note 5 tGP tGA VTGt St/GT tREC tABS StD TE DC load (Note 1) 15±1ms <120µA < 0.5mA (optional) 20±5ms TE AC load 50-150ms Current wetting pulse (see SIN227) Note 2 Zss (Refer to SIN227) FSKen Note 3 tCP tCA CD DR DCLK DATA OSCout ..101010.. Data A ≥ 100ms B = 88-110ms C ≥ 45ms (up to 5sec) D = 80-262ms E = 45-75ms F ≤ 2.5sec (typ. 500ms) G > 200ms Note: All values obtained from SIN227 Issue 1 Figure 15 - Input and Output Timing for BT Caller Display Service (CDS), e.g., CLIP Notes: 1) By choosing tGA=15ms, tABS will be 15-25ms so that the current wetting pulse and AC load can be applied right after the StD falling edge. 2) SIN227 specifies that the AC and DC loads should be removed between 50-150ms after the end of the FSK signal, indicated by CD returning to high. The CNIC2 may also be powered down at this time. 3) FSKen should be set low when FSK is not expected to prevent the FSK demodulator from reacting to other in-band signals such as speech, tone alert signal and DTMF tones. 4) TRIGout is the ring envelope during ringing. 5) The total recognition time is tREC = tGP + tDP, where tGP is the tone present guard time and tDP is the tone present detect time (refer to section “Dual Tone Detection Guard Time” on page 25 for details). 6) The total tone absent time is tABS = tGA + tDA, where tGA is the tone absent guard time and tDA is the tone absent detect time (refer to section “Dual Tone Detection Guard Time” on page 25 for details). V TGt is the comparator threshold (refer to Figure 4). 5-37 MT8843 Preliminary Information TIP/RING 1st Ring A Ch. seizure B C Mark D 2nd Ring Data Packet E F TRIGout Note 4 PWDN Note 1 Note 3 Note 1 OSCout FSKen Note 2 t CP tCA CD A = 2sec typical B = 250-500ms C = 250ms D = 150ms E = feature specific Max C+D+E = 2.9 to 3.7sec F ≥ 200ms DR DCLK DATA ..101010.. Data Figure 17 - Input and Output Timing for Bellcore On-hook Data Transmission Associated with Ringing, e.g., CID Notes: This on-hook case application is included because a CIDCW (off-hook) CPE should also be capable of receiving on-hook data transmission (with ringing) from the end office. TR-NWT-000575 specifies that CIDCW will be offered only to lines which subscribe to CID. 1) The CPE designer may choose to enable the CNIC2 only after the end of ringing to conserve power in a battery operated CPE. CD is not activated by ringing. 2) The CPE designer may choose to set FSKen always high while the CPE is on-hook. Setting FSKen low prevents the FSK demodulator from reacting to other in-band signals such as speech, CAS or DTMF tones. 3) The microcontroller in the CPE powers down the CNIC2 after CD has become inactive. 4) The microcontroller times out if CD is not activated. 5-39