TI SN74GTL2107PWRG4

SN74GTL2107
12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR
www.ti.com
SCLS699 – JULY 2006
FEATURES
•
•
•
•
PW PACKAGE
(TOP VIEW)
Operates as a GTL–/GTL/GTL+ to LVTTL or
LVTTL to GTL–/GTL/GTL+ Translator
Series Termination on TTL Output of 30 Ω
Latch-Up Testing Done to JEDEC Standard
JESD 78
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
VREF
1AO
2AO
5A
6A
EN1
11BI
11A
9BI
3AO
4AO
10AI1
10AI2
GND
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
1BI
2BI
7BO1
7BO2
EN2
11BO
5BI
6BI
3BI
4BI
10BO1
10BO2
9AO
DESCRIPTION/ORDERING INFORMATION
The SN74GTL2107 is a 12-bit translator that interfaces between the 3.3-V LVTTL chip set I/O and the Xeon™
processor GTL–/GTL/GTL+ I/O. The device is designed for platform health management in dual-processor
applications.
PIN DESCRIPTION
PIN NO.
SYMBOL
1
VREF
GTL reference voltage
NAME AND FUNCTION
2–6, 8, 10–13,
15, 23
ENn
nAn
Data and enable inputs/outputs (LVTTL)
on all inputs and pin 15 output.
Remaining outputs are open drain.
7, 9, 16, 17–22,
24–27
nBn
Data inputs/outputs (GTL–/GTL/GTL+)
14
GND
Ground (0 V)
28
VCC
Positive supply voltage
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
TSSOP – PW
ORDERABLE PART NUMBER
Tube
SN74GTL2107PW
Tape and reel
SN74GTL2107PWR
TOP-SIDE MARKING
GK2107
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Xeon is a trademark of Intel Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
SN74GTL2107
12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR
www.ti.com
SCLS699 – JULY 2006
FUNCTION TABLES (1)
INPUTS
(1)
EN1
1BI/2BI
OUTPUT
1AO/2AO
(OPEN DRAIN)
H
L
L
H
H
H
L
X
H
H = High voltage level, L = Low voltage level
EN2
INPUTS
3BI/4BI
OUTPUT
3AO/4AO
(OPEN DRAIN)
H
L
L
H
H
H
L
X
H
INPUT
9BI
OUTPUT
9AO
L
L
H
H
INPUTS
9BI
OUTPUT
10BO1/10BO2
L
L
L
L
H
L
10AI1/10AI2
H
L
L
H
H
H
INPUTS
(1)
(2)
(1)
2
EN2
5BI/6BI
INPUT/OUTPUT
5A/6A
(OPEN DRAIN)
H
L
L
H (1)
H
H
L (2)
L
H
H
H
H
L
H
L (2)
L
L
H
H
H
L
L
H
H
L
L
L (2)
H
OUTPUT
7BO1/7BO2
The enable on 7BO1/7BO2 includes a delay that prevents a
transient condition (where 5BI/6BI goes from low to high, and the
low to high on 5A/6A lags up to 100 ns) from causing a low glitch
on the 7BO1/7BO2 outputs.
Open-drain input/output terminal is driven to a logic-low state by an
external driver.
INPUT
11BI
INPUT/OUTPUT
11A
(OPEN DRAIN)
OUTPUT
11BO
L
H
L
L
L (1)
H
H
L
H
Open-drain input/output terminal is driven to a logic-low state by an
external driver.
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SN74GTL2107
12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR
www.ti.com
SCLS699 – JULY 2006
LOGIC SYMBOL
SN74GTL2107
GTL V REF
1
1AO
2
2AO
3
5A (OPEN DRAIN)
4
25
5
24
LVTTL INPUT EN1
6
23
GTL INPUT 11BI
7
22
LVTTL I/O 11A (OPEN DRAIN)
8
27
LVTTL OD OUTPUTS
26
1BI
2BI
7BO1
LVTTL I/O
6A (OPEN DRAIN)
GTL INPUT 9BI
21
10
18
11
17
12
LVTTL INPUTS
16
10AI2
13
15
(1)
EN2 LVTTL INPUT
11BO GTL OUTPUT
5BI
DELAY1
LVTTL OD OUTPUTS
10AI1
7BO2
9
19
4AO
GTL
OUTPUTS
DELAY1
20
3AO
GTL
INPUTS
6BI
GTL
INPUTS
3BI
4BI
10BO1
GTL
OUTPUTS
10BO2
9AO LVTTL OUTPUT
The enable on 7BO1/7BO2 includes a delay that prevents a transient condition (where 5BI/6BI go from low to high,
and the low to high on 5A/6A lags up to 100 ns) from causing a low glitch on the 7BO1/7BO2 outputs.
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3
SN74GTL2107
12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR
www.ti.com
SCLS699 – JULY 2006
Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
–0.5
4.6
A port (LVTTL)
–0.5
4.6
B port (GTL)
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
Supply voltage range
UNIT
V
VI
Input voltage range (3)
VO
Output voltage range (output in OFF or HIGH state) (3)
IIK
Input diode current
VI < 0
–50
mA
IOK
Output diode current
VO < 0
–50
mA
A port
32
B port
30
A port
–32
mA
62
°C/W
150
°C
Current into any output in the LOW state
Current into any output in the HIGH state
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
–60
V
V
mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltages are referenced to GND (ground = 0 V).
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
The performance capability of a high-performance integrated circuit, in conjunction with its thermal environment, can create junction
temperatures that are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
Recommended Operating Conditions
VCC
VTT
MIN
NOM
MAX
3
3.3
3.6
GTL–
0.85
0.9
0.95
GTL
1.14
1.2
1.26
GTL+
1.35
1.5
1.65
0.5
2/3 VTT
1.8
GTL–
0.5
0.6
0.63
GTL
0.76
0.8
0.84
GTL+
0.87
1
1.1
A port
0
3.3
3.6
B port
0
VTT
3.6
Supply voltage
Termination voltage
Overall
VREF Reference voltage
4
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
A port
2
B port
VREF + 50 mV
0.8
B port
VREF – 50 mV
A port
–16
A port
16
B port
15
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V
V
V
V
V
A port
–40
UNIT
85
V
mA
mA
°C
SN74GTL2107
12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR
www.ti.com
SCLS699 – JULY 2006
Electrical Characteristics
over recommended operating conditions
PARAMETER
VOH (2)
–40°C to 85°C
TEST CONDITIONS
VCC = 3 V to 3.6 V, IOH = –100 µA
A port
TYP (1)
MIN
VCC – 0.2
VCC = 3 V, IOH = –16 mA
V
2.1
A port
VCC = 3 V, IOL = 16 mA
0.8
B port
VCC = 3 V, IOL = 15 mA
0.4
VCC = 3.6 V, VI = VCC
±1
VCC = 3.6, VI = 0 V
±1
B port
VCC = 3.6 V, VI = VTT or GND
±1
ICC
A or B port
VCC = 3.6 V, VI = VCC or GND, IO = 0
∆ICC (3)
A port or control inputs
VCC = 3.6 V, VI = VCC – 0.6 V
A port
VO = 3 V or 0
5
B port
VO = VTT or 0
4
VOL (2)
A port
II
CIO
(1)
(2)
(3)
UNIT
MAX
V
µA
12
mA
500
µA
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
This is the increase in supply current for each input that is at the specified LVTTL voltage, rather than VCC or GND.
Switching Characteristics
over recommended operating free-air temperature range
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL (2)
tPLH
tPHL
tPLZ
tPZL
tPLZ
tPZL
tPLZ
tPZL
tPLZ
tPZL
(1)
(2)
WAVEFORM
An to Bn
1
9BI to 9AO
2
9BI to 10BOn
3
11BI to 11BO
3
Bn to Bn
3
ENn to An
5
Bn to An (I/O)
4
Bn to An
4
EN2 to An (I/O)
5
GTL–
GTL
GTL+
VCC = 3.3 V ± 0.3 V
VREF = 0.6 V
VCC = 3.3 V ± 0.3 V
VREF = 0.8 V
VCC = 3.3 V ± 0.3 V
VREF = 1 V
UNIT
MIN
TYP (1)
MAX
MIN
TYP (1)
MAX
MIN
TYP (1) MAX
2
4
8
2
4
8
2
4
8
2
5.5
10
2
5.5
10
2
5.5
10
2
5.5
10
2
5.5
10
2
5.5
10
2
5.5
10
2
5.5
10
2
5.5
10
2
6
11
2
6
11
2
6
11
2
6
11
2
6
11
2
6
11
2
8
13
2
8
13
2
8
13
2
14
21
2
14
21
2
14
21
4
7
11
4
7
11
4
7
11
120
205
350
120
205
350
120
205
350
1
3
7
1
3
7
1
3
7
1
3
7
1
3
7
1
3
7
2
5
10
2
5
10
2
5
10
2
5
10
2
5
10
2
5
10
2
5
10
2
5
10
2
5
10
2
5
10
2
5
10
2
5
10
1
3
7
1
3
7
1
3
7
1
3
7
1
3
7
1
3
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
All typical values are measured at VCC = 3.3 V and TA = 25°C.
Includes –7.6-ns RC rise time of test-load pullup on 11 A, 1.5-kΩ pullup, and 21-pF load on 11 A has approximately 23-ns RC rise time.
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5
SN74GTL2107
12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR
www.ti.com
SCLS699 – JULY 2006
PARAMETER MEASUREMENT INFORMATION
VTT = 1.2 V, VREF = 0.8 V for GTL and VTT = 1.5 V, VREF = 1 V for GTL+
VTT
2 VCC
S1
500 Ω
From Output
Under Test
Open
50 Ω
TEST
tPLH/tPHL
tPLZ/tPZL
GND
CL = 50 pF
(see Note A)
500 Ω
S1
Open
2 VCC
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
3V
Input
(see Note B)
1.5 V
Test
Point
Input
(see Note B)
1.5 V
VTT
VREF
VREF
0V
0V
tPHL
tPLH
tPHL
tPLH
VTT
Output
VREF
VOH
Output
VREF
1.5 V
1.5 V
VOL
VOL
VOLTAGE WAVEFORM 2
PROPAGATION DELAY TIMES
(B port to A port)†
VOLTAGE WAVEFORM 1
PROPAGATION DELAY TIMES
(A port to B port)†
VTT
Input
(see Note B)
VREF
VREF
0V
tPHL
tPLH
VTT
Output
VREF
VREF
VOL
VOLTAGE WAVEFORM 3
PROPAGATION DELAY TIMES
(B port to B port)†
VTT
Input
(see Note B)
VREF
VREF
3V
Input
(see Note B)
1.5 V
1.5 V
0V
tPZL
Output
S1 at 2 VCC
0V
VCC
tPZL
tPLZ
VCC
1.5 V
Output
S1 at 2 VCC
tPLZ
1.5 V
VOL + 0.3 V
VOL + 0.3 V
VOL
VOLTAGE WAVEFORM 4
PROPAGATION DELAY TIMES
(B port to A (I/O) port)†
VOL
VOLTAGE WAVEFORM 5
ENABLE AND DISABLE TIMES
(EN2 to A(I/O) and ENn to An port)†
†
All control inputs are LVTTL levels.
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
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SN74GTL2107
12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR
www.ti.com
SCLS699 – JULY 2006
APPLICATION INFORMATION
VTT
VTT
56 R
56 VCC
1.5 k to 1.2 k
1.5 k
2R
Platform
Health
Management
VCC
CPU1
VREF
VCC
CPU1 1ERR_L
1AO
1BI
1ERR_L
CPU1 THRMTRIP L
2AO
2BI
CPU1 PROCHOT L
5A
7BO1
THRMTRIP L
FORCEPR_L
6A
7BO2
CPU2 PROCHOT L
VCC
NMI_L
1.5 k
EN1
EN2
11BI
11B0
11A
5BI
6BI
3AO
CPU2 THRMTRIP L
4AO
CPU1 SMI L
CPU2 SMI L
NMI
CPU1 SMI L
9BI
CPU2 1ERR_L
PROCHOT L
FORCEPR_L
PROCHOT L
3BI
4BI
1ERR_L
THRMTRIP L
10AI1
10BO1
NMI
10AI2
10BO2
CPU2 SMI L
GND
9AO
CPU2
SMI_BUFF_L
SN74GTL2107
Southbridge NMI
Southbridge SMI_L
PWR GD
Power Supervisor
Frequently Asked Questions
Question 1: On the SN74GTL2107 LVTTL input, specifically 10AI1 and 10AI2, when the SN74GTL2107 is
powered down, these inputs may be pulled up to 3.3 V, and we want to ensure that there is no leakage path
to the power rail under this condition. Are the LVTTL inputs high impedance when the device is powered
down, and will there be any leakage?
Answer 1: When the device is powered down, the LVTTL inputs are in a high-impedance state and do not
leak to VDD if they are pulled high while the device is powered down.
Question 2: Do all the LVTTL inputs have the same powered-down characteristic?
Answer 2: Yes
Question 3: What is the condition of the other GTL I/O and LVTTL output pins when the device is powered
down?
Answer 3: The open-drain outputs, both GTL and LVTTL, do not leak to the power supply if they are pulled
high while the device is powered down. The GTL inputs also do not leak to the power supply under the
same conditions. The LVTTL totem-pole outputs, however, are not open-drain type outputs, and there is
current flow on these pins if they are pulled high when VDD is at ground.
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7
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74GTL2107PW
ACTIVE
TSSOP
PW
28
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74GTL2107PWG4
ACTIVE
TSSOP
PW
28
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74GTL2107PWR
ACTIVE
TSSOP
PW
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74GTL2107PWRG4
ACTIVE
TSSOP
PW
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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