www.ti.com FEATURES • • • • • • • • • • Member of the Texas Instruments Widebus™ Family OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference D-Type Flip-Flops With Qualified Storage Enable Translates Between GTL/GTL+ Signal Levels and LVTTL Logic Levels Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltages With 3.3-V VCC) Ioff Supports Partial-Power-Down Mode Operation Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DESCRIPTION/ORDERING INFORMATION The SN74GTL16923 is an 18-bit registered bus transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. This device is partitioned as two 9-bit transceivers with individual output-enable controls and contains D-type flip-flops for temporary storage of data flowing in either direction. This device provides an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC™ circuitry. SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS674G – AUGUST 1996 – REVISED APRIL 2005 DGG PACKAGE (TOP VIEW) CEAB 1A1 GND 1A2 1A3 GND VCC 1A4 GND 1A5 1A6 GND 1A7 1A8 GND 1A9 2A1 GND 2A2 2A3 GND 2A4 2A5 GND 2A6 VCC GND 2A7 2A8 GND 2A9 CEBA 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 CLKAB 1OEAB 1OEBA 1B1 GND 1B2 1B3 VCC 1B4 1B5 1B6 GND 1B7 1B8 GND 1B9 2B1 GND 2B2 2B3 GND 2B4 2B5 2B6 VREF 2B7 2B8 GND 2B9 2OEBA 2OEAB CLKBA <br/> The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels. All inputs can be driven from either 3.3-V or 5-V devices, which allows use in a mixed 3.3-V/5-V system environment. VREF is the reference input voltage for the B port. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, OEC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1996–2005, Texas Instruments Incorporated SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER www.ti.com SCBS674G – AUGUST 1996 – REVISED APRIL 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) Data flow in each direction is controlled by the output-enable (OEAB and OEBA) and clock (CLKAB and CLKBA) inputs. The clock-enable (CEAB and CEBA) inputs enable or disable the clock for all 18 bits at a time. However, OEAB and OEBA are designed to control each 9-bit transceiver independently, which makes the device more versatile. For A-to-B data flow, the device operates on the low-to-high transition of CLKAB if CEAB is low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, CLKBA, and CEBA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) TSSOP – DGG ORDERABLE PART NUMBER Tape and reel TOP-SIDE MARKING SN74GTL16923DGGR GTL16923 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (1) INPUTS (1) (2) 2 CEAB OEAB CLKAB A OUTPUT B MODE Isolation X H X X Z H L X X B0 (2) X L H or L X B0 (2) L L ↑ L L L L ↑ H H Latched storage of A data Clocked storage of A data A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, CLKBA, and CEBA. Output level before the indicated steady-state input conditions were established SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER www.ti.com SCBS674G – AUGUST 1996 – REVISED APRIL 2005 LOGIC DIAGRAM (POSITIVE LOGIC) 40 VREF 63 1OEAB 1 CEAB 64 CLKAB 33 CLKBA 32 CEBA 62 1OEBA CE 2 1A1 61 1B1 1D CLK CE 1D CLK To Eight Other Channels 34 2OEAB 35 2OEBA 2A1 CE 17 1D 48 2B1 CLK CE 1D CLK To Eight Other Channels 3 SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER www.ti.com SCBS674G – AUGUST 1996 – REVISED APRIL 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 7 V 7 V VO Voltage range applied to any output in the high or power-off IO Current into any output in the low state IO Current into any A-port output in the high state (3) state (2) –0.5 A port 48 B port 100 Continuous current through each VCC or GND UNIT mA 48 mA ±100 mA mA IIK Input clamp current VI < 0 –50 IOK Output clamp current VO < 0 –50 mA θJA Package thermal impedance (4) 55 °C/W Tstg Storage temperature range 150 °C (1) (2) (3) (4) –65 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) (2) (3) (4) VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK Input clamp current IOH High-level output current IOL Low-level output current TA Operating free-air temperature (1) (2) (3) (4) 4 MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTL+ 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTL+ 0.87 1 1.1 B port 0 VTT Except B port 0 5.5 B port Except B port VREF + 50 mV VREF – 50 mV Except B port V V V 2 B port V 0.8 V –18 mA A port –24 mA A port 24 B port 50 –40 85 mA °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Normal connection sequence is GND first, VCC = 3.3 V, I/O, control inputs, VTT, VREF (any order) last. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER www.ti.com SCBS674G – AUGUST 1996 – REVISED APRIL 2005 Electrical Characteristics over recommended operating free-air temperature range for GTL/GTL+ (unless otherwise noted) PARAMETER VIK TEST CONDITIONS MIN TYP (1) MAX VCC = 3.15 V, II = –18 mA VCC = 3.15 V to 3.45 V, VOH A port VCC = 3.15 V VCC = 3.15 V to 3.45 V, A port VOL VCC = 3.15 V VCC = 3.15 V to 3.45 V, B port II VCC = 3.15 V B port VCC = 3.45 V, A-port and control inputs VCC = 3.45 V Ioff IOH = –100 µA VCC – 0.2 IOH = –12 mA 2.4 IOH = –24 mA 2 A port VCC = 3.15 V IOL = 100 µA 0.2 IOL = 12 mA 0.4 IOL = 24 mA 0.5 IOL = 100 µA 0.2 IOL = 10 mA 0.2 IOL = 40 mA 0.4 IOL = 50 mA 0.55 VI = 5.5 V or GND ±5 VI = 5.5 V or GND µA ±20 ±100 VI = 2 V V ±5 VI = VCC or GND VI = 0.8 V V V VCC = 0, VI or VO = 0 to 5.5 V II(hold) UNIT –1.2 µA 75 µA –75 VCC = 3.45 V (2), VI = 0.8 V to 2 V ±500 IOZ (3) A port VCC = 3.45 V, VO = VCC or GND ±10 µA IOZH B port VCC = 3.45 V, VO = 1.5 V 10 µA Outputs high 60 Outputs low 60 Outputs disabled 60 ICC A or B port VCC = 3.45 V, A-port or control inputs at VCC or GND, One input at VCC – 0.6 V ∆ICC (4) Ci Cio (1) (2) (3) (4) VCC = 3.45 V, IO = 0, VI = VCC or GND mA 500 µA pF Control inputs VI = 3.15 V or 0 2.5 3 A port VO = 3.15 V or 0 6 8.5 B port VO = 3.15 V or 0 7 9.5 pF All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. 5 SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER www.ti.com SCBS674G – AUGUST 1996 – REVISED APRIL 2005 Timing Requirements over recommended ranges of supply voltage and operating free-air temperature for GTL (unless otherwise noted) MIN fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time th Hold time MAX UNIT 200 MHz 2.5 Data before CLK↑ 2.6 CE before CLK↑ 3.3 Data after CLK↑ 0.1 CE after CLK↑ ns ns ns 0 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature for GTL (see Figure 1) PARAMETER MIN TYP (1) MAX fmax 200 2.2 5.8 2.1 6.3 1.7 5.3 2 5 tdis ten CLKAB B OEAB B UNIT MHz ns Both transitions tr Transition time, B outputs (0.6 V to 1 V) 0.3 2.9 ns tf Transition time, B outputs (1 V to 0.6 V) 0.1 3.9 ns 1.8 5 1.7 4.8 1.3 4.8 2 4.8 tPHL ten tdis 0.5 ns Slew rate tPLH 6 TO (OUTPUT) tPLH tPHL (1) FROM (INPUT) CLKBA A OEBA A All typical values are at VCC = 3.3 V, TA = 25°C. V/ns ns ns SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER www.ti.com SCBS674G – AUGUST 1996 – REVISED APRIL 2005 Timing Requirements over recommended ranges of supply voltage and operating free-air temperature for GTL+ (unless otherwise noted) MIN fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time th Hold time MAX UNIT 200 MHz 2.5 Data before CLK↑ 2.3 CE before CLK↑ 3.3 Data after CLK↑ 0.1 CE after CLK↑ ns ns ns 0 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature for GTL+ (see Figure 1) PARAMETER TO (OUTPUT) MIN TYP (1) MAX fmax 200 tPLH 2.2 4 5.9 2.1 4 6.1 1.9 3.4 5.2 1.7 3.1 5.1 tPHL tPLH tPHL CLKAB B OEAB B UNIT MHz ns Both transitions tr Transition time, B outputs (0.6 V to 1.3 V) 0.6 1.3 2.6 ns tf Transition time, B outputs (1.3 V to 0.6 V) 0.4 1.3 3 ns 1.8 3.5 5.1 1.7 3.3 4.9 1.3 2.9 4.8 2 3.2 5 tPHL ten tdis 0.5 ns Slew rate tPLH (1) FROM (INPUT) CLKBA A OEBA A V/ns ns ns All typical values are at VCC = 3.3 V, TA = 25°C. 7 SN74GTL16923 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER www.ti.com SCBS674G – AUGUST 1996 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VTT = 1.5 V, VREF = 1 V VTT 6V 500 Ω From Output Under Test S1 Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND CL = 50 pF (see Note A) 500 Ω 25 Ω From Output Under Test CL = 30 pF (see Note A) S1 Open 6V GND LOAD CIRCUIT FOR A OUTPUTS Test Point LOAD CIRCUIT FOR B OUTPUTS 3V Timing Input tw 1.5 V 0V 3V 1.5 V Input 1.5 V tsu 0V VOLTAGE WAVEFORMS PULSE DURATION 3V Input 1.5 V 1.5 V th 3V Data Input A port 1.5 V Data Input B port VREF 1.5 V 0V VTT VREF 0V 0V tPLH VOLTAGE WAVEFORMS SETUP AND HOLD TIMES tPHL VOH Output VREF VREF VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (CLKAB to B port) 1.5 V tPZL 1.5 V 0V tPLH Output Waveform 1 S1 at 6 V (see Note B) 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (CLKBA to A port) 1.5 V tPLZ 3V 1.5 V tPZH tPHL VOH Output 1.5 V 0V 3V Input 3V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ VOH 1.5 V VOH − 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 8 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74GTL16923DGGRE4 ACTIVE TSSOP DGG 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTL16923DGGR ACTIVE TSSOP DGG 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Apr-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device SN74GTL16923DGGR 26-Apr-2007 Package Pins DGG 64 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) MLA 330 24 8.4 17.3 1.7 12 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74GTL16923DGGR DGG 64 MLA 333.2 333.2 31.75 Pack Materials-Page 2 W Pin1 (mm) Quadrant 24 Q1 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. 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