TI SN74LVCH16245ADGGR

SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
FEATURES
•
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•
•
•
•
•
•
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Member of the Texas Instruments Widebus™
Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4 ns at 3.3 V
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2 V at
VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
3.3-V VCC)
Ioff Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
SCES495B – OCTOBER 2003 – REVISED AUGUST 2006
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
DESCRIPTION/ORDERING
INFORMATION
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
This 16-bit (dual-octal) noninverting bus transceiver
is designed for 1.65-V to 3.6-V VCC operation.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
The SN74LVCH16245A is designed for asynchronous communication between data buses. The logic levels of
the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port
outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to
the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level
applied to prevent excess ICC and ICCZ.
Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is
not disabled by OE or DIR.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2006, Texas Instruments Incorporated
SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES495B – OCTOBER 2003 – REVISED AUGUST 2006
ORDERING INFORMATION
PACKAGE (1)
TA
FBGA – GRD
FBGA – ZRD (Pb-free)
ORDERABLE PART NUMBER
Tape and reel
Tube
SSOP – DL
–40°C to 85°C
TSSOP – DGG
Tape and reel
TVSOP – DGV
Tape and reel
VFBGA – GQL
VFBGA – ZQL (Pb-free)
(1)
Tape and reel
Tape and reel
TOP-SIDE MARKING
SN74LVCH16245AGRDR
LDH245A
SN74LVCH16245AZRDR
SN74LVCH16245ADL
SN74LVCH16245ADLR
LVCH16245A
74LVCH16245ADLRG4
SN74LVCH16245ADGGR
LVCH16245A
74LVCH16245ADGGRG4
SN74LVCH16245ADGVR
LDH245A
74LVCH16245ADGVRE4
SN74LVCH16245AGQLR
LDH245A
SN74LVCH16245AZQLR
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
GQL OR ZQL PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS (1)
(56-Ball GQL/ZQL Package)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
1
2
3
4
5
6
A
1DIR
NC
NC
NC
NC
1OE
B
1B2
1B1
GND
GND
1A1
1A2
C
1B4
1B3
VCC
VCC
1A3
1A4
D
1B6
1B5
GND
GND
1A5
1A6
E
1B8
1B7
1A7
1A8
F
2B1
2B2
2A2
2A1
G
2B3
2B4
GND
GND
2A4
2A3
H
2B5
2B6
VCC
VCC
2A6
2A5
J
2B7
2B8
GND
GND
2A8
2A7
K
2DIR
NC
NC
NC
NC
2OE
abc
(1)
abc
NC – No internal connection
GRD OR ZRD PACKAGE
(TOP VIEW)
1
2
3
4
5
6
TERMINAL ASSIGNMENTS (1)
(54-Ball GRD/ZRD Package)
1
A
B
C
2
3
4
6
A
1B1
NC
1DIR
1OE
NC
1A1
B
1B3
1B2
NC
NC
1A2
1A3
C
1B5
1B4
VCC
VCC
1A4
1A5
D
1B7
1B6
GND
GND
1A6
1A7
D
E
2B1
1B8
GND
GND
1A8
2A1
E
F
2B3
2B2
GND
GND
2A2
2A3
G
2B5
2B4
VCC
VCC
2A4
2A5
H
2B7
2B6
NC
NC
2A6
2A7
J
2B8
NC
2DIR
2OE
NC
2A8
F
G
H
J
(1)
2
5
NC – No internal connection
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SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES495B – OCTOBER 2003 – REVISED AUGUST 2006
FUNCTION TABLE (1)
(EACH 8-BIT SECTION)
CONTROL INPUTS
(1)
OUTPUT CIRCUITS
OPERATION
OE
DIR
A PORT
B PORT
L
L
Enabled
Hi-Z
B data to A bus
L
H
Hi-Z
Enabled
A data to B bus
H
X
Hi-Z
Hi-Z
Isolation
Input circuits of the data I/Os always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
1DIR
1
2DIR
48
1A1
25
1OE
47
2A1
2
24
2OE
36
13
1B1
2B1
To Seven Other Channels
To Seven Other Channels
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
–0.5
VCC + 0.5
state (2) (3)
VO
Voltage range applied to any output in the high or low
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through each VCC or GND
θJA
Tstg
(1)
(2)
(3)
(4)
Package thermal
impedance (4)
DGG package
70
DGV package
58
DL package
63
GQL/ZQL package
42
GRD/ZRD package
36
Storage temperature range
–65
150
V
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES495B – OCTOBER 2003 – REVISED AUGUST 2006
Recommended Operating Conditions (1)
VCC
Supply voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
3.6
1.5
Low-level input voltage
VI
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
VO
Output voltage
IOH
High-level output current
0.35 × VCC
0.7
VCC = 2.7 V to 3.6 V
0.8
0
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 1.65 V
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 1.65 V
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
4
V
VCC = 2.3 V to 2.7 V
Input voltage
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
V
V
V
mA
4
VCC = 2.3 V
8
VCC = 2.7 V
12
VCC = 3 V
24
–40
mA
5
ns/V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES495B – OCTOBER 2003 – REVISED AUGUST 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VOH
1.65 V to 3.6 V
1.65 V
1.2
IOH = –8 mA
2.3 V
1.7
2.7 V
2.2
3V
2.4
IOH = –24 mA
3V
2.2
IOL = 100 µA
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
3V
0.55
IOL = 24 mA
II
Control inputs
VI = 0 to 5.5 V
VI = 0.7 V
A or B port
VI = 0.8 V
VI or VO = 5.5 V
IOZ (3)
VO = 0 V or (VCC to 5.5 V)
VI = VCC or GND
ICC
µA
–45
75
–75
±500
0
±10
µA
2.3 V to 3.6 V
±5
µA
IO = 0
3.6 V ≤ VI ≤ 5.5 V (4)
∆ICC
45
3.6 V
V (2)
Ioff
20
3.6 V
One input at VCC – 0.6 V, Other inputs at VCC or GND
µA
15
3V
VI = 2 V
V
–15
2.3 V
VI = 1.7 V
VI = 0 to 3.6
±5
1.65 V
VI = 1.07 V
UNIT
V
3.6 V
VI = 0.58 V
II(hold)
MAX
VCC – 0.2
IOH = –4 mA
IOH = –12 mA
VOL
MIN TYP (1)
VCC
20
2.7 V to 3.6 V
500
µA
µA
Ci
Control inputs
VI = VCC or GND
3.3 V
5
pF
Cio
A or B port
VO = VCC or GND
3.3 V
7.5
pF
(1)
(2)
(3)
(4)
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current required to switch the input from one state to another.
For the total leakage current in an I/O port, consult the II(hold) specification for the input voltage condition 0 V < VI < VCC, and the IOZ
specification for the input voltage conditions VI = 0 V or VI = VCC to 5.5 V. The bus-hold current, at input voltage greater than VCC, is
negligible.
This applies in the disabled state only.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
ten
OE
tdis
OE
PARAMETER
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
B or A
1.5
7.1
1
A or B
1.5
8.9
1
A or B
1.5
11.9
1
tsk(o)
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VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MIN
MAX
MAX
4.5
1
4.7
1
4
ns
5.6
1.5
6.7
1.5
5.5
ns
6.8
1.5
7.1
1.5
6.6
ns
1
ns
5
SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES495B – OCTOBER 2003 – REVISED AUGUST 2006
Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
6
Power dissipation capacitance
per transceiver
Outputs enabled
Outputs disabled
f = 10 MHz
Submit Documentation Feedback
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
36
36
40
3
3
4
UNIT
pF
SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES495B – OCTOBER 2003 – REVISED AUGUST 2006
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VM
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VOH
Output
VI
Output
Control
VM
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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7
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74LVCH16245ADGGRG4
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74LVCH16245ADGVRE4
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74LVCH16245ADLRG4
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCH16245ADGGR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCH16245ADGVR
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCH16245ADL
ACTIVE
SSOP
DL
48
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCH16245ADLG4
ACTIVE
SSOP
DL
48
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCH16245ADLR
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVCH16245AGQLR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
GQL
56
1000
TBD
SNPB
Level-1-240C-UNLIM
SN74LVCH16245AGRDR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
GRD
54
1000
TBD
SNPB
Level-1-240C-UNLIM
SN74LVCH16245AZQLR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQL
56
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
SN74LVCH16245AZRDR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZRD
54
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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