V370PDC Rev. A0 High Performance PCI SDRAM Controller with Integrated Peripheral Control Unit • Fully compliant with PCI 2.2 specification target interface • Multiplexed or Non-multiplexed 8-, 16-, or 32-bit generic peripheral bus interface • Support up to 1 Gbyte of SDRAM • Support up to 2 single banks or 1 dual bank industrial standard 168-pin PC SDRAM DIMM • Support up to 1Kbyte of burst access from PCI • Up to 5 programmable chip select for peripheral strobe generation • Large On-Chip FIFOs using V3’s unique DYNAMIC BANDWIDTH ALLOCATION™ architecture • Buffered PCI clock output • Hot Swap Ready (PICMG™ Hot Swap Specification) • Implementation of PCI Bus Power Management Interface Specification Version 1.0 • Initialization through PCI or serial EEPROM • Programmable PCI and local interrupt management • Two 32-bit General Purpose Timers • Up to 66 MHz local bus clock with asynchronous PCI clock up to 33MHz • 3.3V operation with 5V tolerant inputs • Industrial Temperature Range (-40C to +85C) • Low cost 160-pin PQFP package The V370PDC PCI SDRAM Controller simplifies the design of PCI based memory sub-systems. System designers can replace many lower integration support components with this single, high-integration device saving design time, board area, and manufacturing cost. The V370PDC from V3 Semiconductor is a high performance PCI SDRAM Controller with integrated peripheral control unit operating at up to 66 MHz local bus speed. It features multiple address translation units from PCI which allow designers the freedom to customize their local address space. Access latency of slower peripherals are absorbed through the large OnChip FIFOs. The peripheral bus provides low latency access to SDRAM. The peripheral control unit on the V370PDC also performs address decoding and chip-select strobes generation for SRAM, PROM and other slow peripherals. The peripheral bus can also be tri-stated through a simple hand-shaking protocol to allow other local bus masters control of the bus. The SDRAM Controller connects the PCI bus through on-chip FIFOs to SDRAM arrays of up to 1 Gbytes in size. The fully programmable SDRAM controller also supports the use of Enhanced SDRAM to achieve even greater performance. Burst accesses of up to 1 Kbyte from PCI is supported. The two general purpose 32-bit timers can be individually configured as a pulse width modulator, or used in other modes such as retriggerable or oneshot. Interrupts for a real time OS can be easily generated by the system heartbeat timer. A watchdog timer is also provided for graceful recovery from catastrophic program failures. Interrupt requests for all on-chip peripherals are managed by the Interrupt Control Unit. Additionally, off-chip interrupts can be routed to the Interrupt Control Unit. The V370PDC is packaged in a low-cost 160-pin EIJA Plastic Quad Flat Pack (PQFP), and is available in 66MHz speed grade. TYPICAL APPLICATION PCI Target Only Application PCI-to-ISA Conversion Application ISA Conversion Logic SRAM/ FLASH V370PDC V370PDC Copyright © 1999, V3 Semiconductor Corp. SDRAM and PROM SDRAM V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 V3 Semiconductor reserves the right to change the specifications of this product without notice. V370PDC is a trademark of V3 Semiconductor Inc. All other trademarks are the property of their respective owners. 1 V370PDC This document contains the product codes, pinout, package mechanical information, DC characteristics, and AC characteristics for the V370PDC. Detailed functional information is contained in the User’s Manual. V3 Semiconductor retains the rights to change documentation, specifications, or device functionality at any time without notice. Please verify that you have the latest copy of all documents before finalizing a design. 1.0 Product Codes Table 1: Product Codes Product Code Package Frequency V370PDC-66 REV A0 160-pin EIAJ PQFP 66MHz 2.0 Pin Description Table 2 below lists the pin types found on the V370PDC. Table 3 describes the function of each pin on the V370PDC. Table 2: Pin Types Pin Type PCI I PCI input only pin. PCI O PCI output only pin. PCI I/O PCI tri-state I/O pin. PCI I/OD PCI input with open drain output. I/O8 TTL I/O pin with 8mA output drive. I/OD TTL input with open drain output. I 2 Description TTL input only pin. O2 TTL output pin with 2mA output drive. O8 TTL output pin with 8mA output drive. O12 TTL output pin with 12mA output drive. V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 Copyright © 1999, V3 Semiconductor Inc. V370PDC Table 3: Signal Descriptions PCI Bus Interface Signal Type Ra AD[31:0] PCI I/O Z C/BE[3:0] PCI I PAR PCI I/O FRAME PCI I Cycle Frame indicates the beginning and burst length of an access. IRDY PCI I Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data phase of the transaction. TRDY PCI O Z Target Ready indicates the target agent’s (selected device’s) ability to complete the current data phase of the transaction. STOP PCI O Z Stop indicates the current target is requesting the master to stop the current transaction (retry or disconnect). DEVSEL PCI O Z Device Select, when actively driven by a target, indicates the driving device has decoded its address as the target of the current access. IDSEL PCI I PERR PCI I/O Z Parity Error is used to report data parity errors during all PCI transactions except a Special Cycle. SERR PCI I/OD Z System Error is used to report address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. PCLK PCI I Description Address and data, multiplexed on the same pins. Bus Command and Byte Enables, multiplexed on the same pins. Z Parity represents even parity across AD[31:0] and C/BE[3:0]. Initialization Device Select is used as a chip select during configuration read and write transactions. It must be driven high in order to access the chip’s internal configuration space. PCLK provides timing for all transactions on the PCI bus. SDRAM and Peripheral Bus Interface Signal Type R CLKIN I CLKOUT O12 X Buffered PCI clock output DCS[3:0] O8 Z SDRAM Chip Select MA[14:0] O12 Z SDRAM Memory Address (also, A[16:2] for peripheral access). MA[14:13] are typically used for BA[1:0] RAS O12 Z SDRAM Row Address Strobe Copyright © 1999, V3 Semiconductor Corp. Description Local clock input V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 3 V370PDC Table 3: Signal Descriptions (cont’d) CAS O12 Z SDRAM Column Address Strobe MWE O12 Z SDRAM Memory Write Enable MAD[31:0] I/O8 Z SDRAM and peripheral bus data DQM[3:0] O8 Z SDRAM Data Mask (these act as MBE[3:0], A[1:0] for peripheral access) MARB_IN I MARB_OUT O8 0 Peripheral bus arbitration output: Treated as bus grant output when V370PDC is the primary bus master. When V370PDC is the secondary bus master, this output acts bus request. ALE O8 Z Address Latch Enable: used to latch the address on MAD[31:0] during the address phase of a peripheral bus access. ADS O8 Z Asserted low to indicate the beginning of a bus cycle. BLAST O8 Z Burst last. READY I WNR O8 Z Write/Read. SDA I/OD Z Serial EEPROM Data SCL O2 Z Serial EEPROM Clock IOC[11:0] I/O8 Z Multi-purpose I/O that can be configured for many functions INT[3:0] I/O8 Z General purpose interrupt inputs/outputs: may be used for either PCI or local processor interrupts Peripheral bus arbitration input: Treated as bus request input when V370PDC is the primary bus master. When V370PDC is the secondary bus master, this input acts as bus grant. Data ready. Mode and Reset 4 Signal Type RSTIN I RSTOUT O8 CH I R Description Reset Input: Active low reset input used to initialize all internal functions of the chip. 0 Reset Output: Driven active when the input reset is driven active. Driven inactive when the RSTOUT bit in the system register is set. The RSTOUT signal is synchronous to the rising edge of CLKIN. PCI Precharge Bias: This signal is driven low to activate the onchip precharge bias for use in PICMG Hot Swap applications. Non-Hot Swap applications should pull this signal high. V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 Copyright © 1999, V3 Semiconductor Inc. V370PDC Table 3: Signal Descriptions (cont’d) MODE Input: selects mastership of V370PDC: MODE I 0 = Secondary master 1 = Primary master Power and Ground Signals Signal Type R Description VCC - POWER leads for external connection to a 3.3V VCC board plane. GND - GROUND leads for external connection to a GND board plane. NC - No connect. a. R indicates state during reset. 2.1 Pinout Table 4 lists the pins by pin number. Figure 1 shows the pinout for the 160-pin EIAJ PQFP package and Figure 2 shows the mechanical dimensions of the package Copyright © 1999, V3 Semiconductor Corp. V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 5 V370PDC Table 4: Pin Assignments 6 PIN # 1 2 3 Signal RSTIN PCLK GND PIN # 41 42 43 Signal Vcc AD14 AD13 PIN # 81 82 83 Signal Vcc MAD9 MA13 PIN # 121 122 123 Signal Vcc MA5 MAD27 4 5 6 7 8 Vcc NC CH AD31 AD30 44 45 46 47 48 AD12 AD11 AD10 AD9 AD8 9 10 AD29 AD28 49 50 C_BE0 MODE 84 85 86 87 88 89 90 MAD10 MA12 MAD11 MA11 MAD12 MA10 GND 124 125 126 127 128 129 130 MA4 MAD28 MA3 MAD29 MAD30 MAD31 GND 11 12 AD27 AD26 51 52 GND AD7 91 92 MAD13 IOC11 131 132 MA2 MA1 13 14 15 AD25 AD24 GND 53 54 55 AD6 AD5 AD4 93 94 95 MAD14 IOC10 MAD15 133 134 135 MA0 IOC3 IOC2 16 C_BE3 17 18 IDSEL AD23 56 57 58 AD3 AD2 AD1 96 97 98 IOC9 MAD16 IOC8 136 137 138 READY MARB_OUT MARB_IN 19 20 21 AD22 Vcc AD21 59 60 61 AD0 Vcc GND 99 100 101 MAD17 Vcc GND 139 140 141 ADS Vcc GND 22 23 24 AD20 AD19 AD18 62 63 64 MAD0 DCS0 MAD1 102 103 104 MA9 MAD18 MA8 142 143 144 CLKIN IOC1 IOC0 25 AD17 65 DCS1 105 MAD19 145 DQM3 26 27 28 29 AD16 GND C_BE2 FRAME 66 67 68 69 MAD2 DCS2 MAD3 DCS3 106 107 108 109 MA7 MAD20 MA6 MAD21 146 147 148 149 DQM2 DQM1 DQM0 BLAST 30 IRDY 31 32 TRDY DEVSEL 70 71 MAD4 GND 110 111 GND MAD22 150 151 WNR GND 33 34 35 STOP PERR SERR 72 73 74 MAD5 MWE MAD6 112 113 114 IOC7 MAD23 IOC6 152 153 154 CLKOUT RSTOUT ALE 75 CAS 115 MAD24 155 SDA 36 37 38 39 40 PAR Vcc C_BE1 AD15 GND 76 77 78 79 80 MAD7 RAS MAD8 MA14 GND 116 117 118 119 120 IOC5 MAD25 IOC4 MAD26 GND 156 157 158 159 160 SCL INT0 INT1 INT2 INT3 V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 Copyright © 1999, V3 Semiconductor Inc. V370PDC Figure 1: Pinout for 160-pin EIAJ PQFP (top view) Copyright © 1999, V3 Semiconductor Corp. V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 7 V370PDC Figure 2: 160-pin EIAJ PQFP mechanical details 8 V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 Copyright © 1999, V3 Semiconductor Inc. V370PDC 3.0 DC Specifications The DC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev. 2.2 Section 4.2.1.1. For more information on the PCI DC specifications, see the PCI Specification. Table 5: Absolute Maximum Ratings Symbol Parameter Value Units VCC Supply voltage -0.3 to +3.6 V VIN DC input voltage -0.3 to 6.0 V Storage temperature range -55 to +125 °C TSTG Table 6: Guaranteed Operating Conditions Symbol Parameter VCC Supply voltage Jmax Maximum junction temperature Theta Ja Thermal resistance (Package) Theta Jc Thermal resistance (Junction-Case) TA 3.1 Ambient temperature range Value Units 3.0 to 3.6 V 125 °C 41 to 46 °C/w 21 °C/w -40 to +85 °C PCI Bus DC Specifications Table 7: PCI Bus Signals DC Operating Specifications Symbol Parameter Condition Min Max Units VIH Input high voltage 0.5VCC VCC + 0.5 V VIL Input low voltage -0.5 0.3VCC V IIH Input high leakage current IIL Input low leakage current 0 < VIN < VCC VOH Output high voltage IOUT = -500µA VOL Output low voltage IOUT = 1500µA CIN Input pin capacitance CCLK PCLK pin capacitance Copyright © 1999, V3 Semiconductor Corp. 0.7VCC +10 0.9VCC 5 Notes µA 1 µA 1 V 0.1VCC V 2 10 pF 3 12 pF V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 9 V370PDC Table 7: PCI Bus Signals DC Operating Specifications Symbol CIDSEL LPIN Parameter Condition Min Max Units Notes IDSEL pin capacitance 8 pF 4 Pin inductance 20 nH Notes: 1. Input leakage currents include high impedance output leakage for all bi-directional buffers with tri-state outputs. 2. Signals without pull-up resistors have greater than 3mA low output current. Signals requiring pull resistors have greater than 6mA output current. The latter include FRAME, TRDY, IRDY, STOP, SERR, PERR. 3. Absolute maximum pin capacitance for a PCI unit is 10pF (except for CLK). 4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx]. 3.2 Local Bus DC Specifications Table 8: Local Bus Signals DC Operating Specifications (VCC = 3.3V+ 0.3V) Symbol Condition VIH Input high voltage VIL Input low voltage IIH Input high leakage current VIN = VCC IIL Input low leakage current 10 µA VIN=GND -10 10 µA 2.4 Output low voltage IOUT = 2, 8, 12mA IOZL Low level float input leakage VOL = GND IOZH High level float input leakage VOH = VCC Typical supply current V -10 VOL ICC (typ) Units V IOUT = -2, -8, -12mA Maximum supply current Max 0.8 Output high voltage ICC (max) Min 2.0 VOH CIO 10 Parameter PCLK=33MHz, CLKIN=66MHz, Vcc=3.6v, all buses operating Input and output capacitance V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 V 0.4 V -10 10 µA -10 10 µA 70 mA 40 mA 10 pF Copyright © 1999, V3 Semiconductor Inc. V370PDC 3.3 AC Specifications The AC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev. 2.1, Section 4.2.1.2. For more information on the PCI AC specifications, including the V/I curves for 5V signalling, see section 4.2.1.2 of Rev 2.1 PCI Specification. 3.4 PCI Bus Timings Table 9: PCI Bus Signals AC Operating Specifications Symbol Parameter Switching Current high IOH(AC) (Test point) Switching Current low IOL(AC) Condition Min Max 0V< VOUT≤ 0.3VCC -12VCC mA 0.3VCC<VOUT<0.9V -17.1(VCC-VOUT) mA 0.7VCC<VOUT<VCC Equation C VOUT = 0.7VCC -32VCC Units VCC > VOUT >0.6VCC 16VCC mA 0.6VCC > VOUT >0.1VCC 26.7VCC mA 38VCC (Test point) VOUT=0.18VCC ICL Low clamp current -3V<VIN<-1V -25+(VIN+1)/0.015 tR Unloaded output rise time 0.2VCC to 0.6VCC 1 4 V/ns tF Unloaded output fall time 0.6V to 0.2V 1 4 V/ns Copyright © 1999, V3 Semiconductor Corp. V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 Notes mA mA 11 V370PDC 3.5 Local Bus Timings Table 10: Local Bus AC Test Conditions Symbol Parameter Limits Units VCC Supply voltage 3.3 volt operation 3.0 to 3.60 V VIN Input low and high voltages 0.4 and 2.0 V 50 pF COUT Capacitive load on output and I/O pins Table 11: Capacitive Derating for Output and I/O Pins Output Drive Limit Supply voltage Derating 8mA 3.3 volt 0.019 ns/pF for loads > 50pF 12mA 3.3 volt 0.017 ns/pF for loads > 50pF Figure 3: Clock and Synchronous Signals : 12 V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 Copyright © 1999, V3 Semiconductor Inc. V370PDC Table 12: Local Bus Timing Parameters for Vcc =3.3 Volts +/- 5% 66MHz # Symbol Description Notes Min 1 TC CLKIN period 15 ns 2 TCH CLKIN high time 5.5 ns 3 TCL CLKIN low time 5.5 ns 4 TSU Synchronous input setup 3 ns 4a TSU Asynchronous input setup (READY) 7 ns 5 TH Synchronous input hold 1 ns 6 TCOV CLKIN to output valid delay 3 11 ns 7 TCZO CLKIN to output driving delay 3 11 ns 8 TCOZ CLKIN to high impedance delay 4 12 ns 9 TALE ALE Pulse Width TCH+0.5 TCH+1 ns 10 TCLH CLKIN rising to ALE rising 2 10 ns 11 TAH CLKIN falling to ALE falling 2 10 ns 1 Max Units Notes: 1. Applies only to READY pin when i960_RDY bit in LB_BUS_CFG register is set to ’1’. Table 13: PCI Bus Timing Parameters for Vcc = 3.3 Volts +/- 10% # Symbol Description 1 TC PCLK period 2 TSU Synchronous input setup to PCLK 3 TH Synchronous input hold from PCLK 4 TCOV PCLK to output valid delay 5 TCZO 6 7 Notes Min Max Units 30 ns 7 ns 0 ns 1 3 11 ns PCLK to output driving delay 4 11 ns TCOZ PCLK to high impedance delay 5 18 ns TRST Reset period when PRST used as input Copyright © 1999, V3 Semiconductor Corp. 2 16·TC V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 13 V370PDC 3.6 Serial EEPROM Port TImings The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms generated are shown in Figure 4. Figure 4: Serial EEPROM Waveforms and Timings 512 PCI BUS CLOCKS START CONDITION STOP CONDITION SCL SDA 256 PCI BUS CLOCKS 256 PCI BUS CLOCKS 4.0 Revision History Table 14: Revision History Revision Number 0.8 Date Comments and Changes 01/99 First pre-silicon revision of preliminary data sheet. 0.9 03/99 Update Figure 2: Mechanical Drawing; Update Table 8: Local Bus Signals DC Operating Specifications; Update Table 10: Local Bus AC Test Conditions; Update Table 12: Local Bus Signals AC Operating Specifications. 1.0 03/99 Initial Release. 1.1 06/00 Updated TBA parameters USA: 2348G Walsh Avenue Santa Clara, CA 95051 Phone: (408)988-1050 Fax: (408)988-2601 Toll Free: (800)488-8410 (Canada and U.S. only) World Wide Web: http://www.vcubed.com 14 V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 Copyright © 1999, V3 Semiconductor Inc.