MITSUBISHI
SOUND
PROCESSOR
MITSUBISHI
SOUND
PROCESSOR
ICsICs
M65824FP
M65824FP
SIGNAL PROCESSOR FOR
CDPROCESSOR
PLAYERFOR
WITH
BUILT-IN
D/AD/A
SIGNAL
CD PLAYER
WITH BUILT-IN
DESCRIPTION
The M65824FP is a CMOS IC for playback of a compact disk (CD-DA).
It is equipped with memory, non-adjustment PLL, 4fs digital filter and D-A converter.
The M65824FP can configure a compact CD-DA system.
FEATURES
•Non-adjustment EFM-PLL with wide lock-range (built-in VCO)
•Jitter margin ± 8 frames
•Operatable CLV servo command
•Attenuation (-12 dB)
•Built-in 4fs digital filter
•Built-in digital de-emphasis circuit
•Built-in D-A converter
•Compact set by the adoption of a compact package
•Built-in analog LPF
•External D-A mode
RECOMMENDED OPERATING CONDITIONS
Outline 42P2R-A
Supply voltage range (interface)........................ DVDD = 2.7 to 5.5V
0.8mm pitch 450mil SSOP
(8.4mm x 17.5mm x 2.0mm)
Supply voltage range (internal circuit, analog)
............ DSPS, AVDD = 2.7 to 3.3V
Rated supply voltage (interface).................................. DVDD = 5.0V
Rated supply voltage (internal circuit, analog)
....................... DSPS, AVDD = 3.0V
Rated power consumption.................................................. 100 mW
SYSTEM CONFIGURATION
M65824FP
SUBCODE
INTERFACE
M
MOTOR
DRIVER
OPTICAL
PICK-UP
RF-AMP
PICK-UP
SERVO
AUTO
ADJUSTMENT
Display
EMF
DE-MODULATOR
PLL
SLICER
INTER
POLATION
DEEMP
PLL CLK OSC CLK
18KSRAM
CLV
DIGITAL
SERVO
ECC
C1:2error
C2:2error
MCU I/F
4FS DIGITAL
FILTER
D/A
L
R
SYSTEM CONTROL MICROPROCESSOR
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MITSUBISHI SOUND PROCESSOR ICs
M65824FP
SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/A
PIN CONFIGURATION (TOP VIEW)
BUILT-IN FUNCTIONS
•D/A converter
•64fs 1 bit ∑ ∆ D-A converter
•S/N:74dB (typ.)
AVSS 1
42 AVDD
WDCK 2
41 IREF
LOCK/DRD 3
40 RNEG/LRCK
CKSEL 4
39 ROUT/DSCK
ACLRB 5
38 LNEG/WDCK
C423 6
37 LOUT/DO
C846 7
36 AMPREF
XI 8
DVSS 9
•Memory
•Jitter margin ± 8 frames
•PLL block
• Non-adjustment slice level control
•EFM demodulator
TEST 11
32 MLAB
SBCO 12
31 MSD
SCCK 13
30 MCK
•EFM modulation
•Frame sync detection/protection
and insertion
•Frame monitor output
34 EXP2
33 EXP1
•Built-in non-adjustment VCO
(Bit clock reproduction)
35 CGREF
XO 10
•Built-in 18K SRAM
•Subcode modulator
•Modulation of subcodes P to W.
serial output (conforming to EIJA
CP-309)
•Subcode Q register
•CRC check
SYCLK 14
29 PWM2
EFFK 15
28 PWM1
KILLB 16
27 PWM
emphasis control
EST1 17
26 SCAND
•C1: double correction, C2: double
EST2 18
25 CRCF
correction
HF 19
24 SBQS
•Unscramble
TLC 20
23 DSPS
LPF 21
22 DVDD
•Subcode sync signal output (S0/S1)
•CIRC block
•Emphasis detection, built-in de-
•De-interleave
•Interpolation processing unit
•Error monitor output
•Average value interpolation and pre-
Outline 42P2R-A
value hold
•D-A interface
•Mute control
•Digital filter
•Quadruple over sampling I I R type
filter
•De-emphasis block
•Bi-primary I I R filter
•Emphasis detection/automatic
operation
•CLV servo block
•PWM output
•Reduced disk rotation detection
output
•Microcomputer I/F block
•CLV servo control command
•Mute control
•-12 dB attenuation
•Subcode Q register interface
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ELECTRIC
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MITSUBISHI SOUND PROCESSOR ICs
M65824FP
SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/A
PIN DESCRIPTION
Pin No.
I/O
O
O
I
I
O
O
7
Symbol
AVSS
WDCK
LOCK/DRD
CKSEL
ACLRB
C423
C846
8
XI
I
9
DVss
XO
TEST
SBCO
SCCK
SYCLK
EFFK
KILLB
EST1
EST2
HF
TLC
LPF
DVDD
DSPS
SBQS
CRCF
SCAND
PWM
PWM1
PWM2
MCK
MSD
MLAB
EXP1
EXP2
CGREF
AMPREF
LOUT/DO
LNEG/WDCK
ROUT/DSCK
RNEG/LRCK
IREF
AVDD
O
1
2
3
4
5
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
I
O
I
O
O
O
O
O
I
O
I/O
O
O
O
O
O
O
I
I/O
I
I
I
I
I
O
O
O
O
I
-
Function
Analog system GND
Word clock output: f=88.2kHz
Sync status/reduced disk rotation detection output
System clock select input, "L": 8.4672 MHz/"H": 16.9344 MHz
System reset input: reset="L"
Crystal system 4.2336 MHz clock output
Crystal system 8.4672 MHz clock output
Crystal oscillator input (built-in feedback resistance)
CKSEL="L": 8.4672MHz/CKSEL="H": 16.9344MHz
Digital system GND
Crystal oscillator output
Shipment test pin: For test="H"
Subcode serial output
Subcode read clock input
Frame sync output: Lock="H"
..
PLL system frame clock output: duty=50%
Digital silence output: Silence="L" open drain output
Error status output 1: at C1 error detection="H"
Error status output 2: at C2 error detection="H"
Playback signal input
Slice level control output
PLL loop filter connection terminal
Power supply to I/O block
Power supply to internal logic circuit
Subcode Q register read interrupt signal: Read enable: "L"
CRC result of subcode Q: CRC OK="H"
Subcode sync signal output: Synchronization="H"
Disk motor drive PWM output (both sides)
Disk motor drive PWM output 1 (acceleration side)
Disk motor drive PWM output 2 (deceleration side)
Microcomputer I/F shift lock
Microcomputer I/F serial data I/O
Microcomputer I/F latch clock (built-in 22kΩ pull-up resistance)
Additional microcomputer input port 1 (built-in 4.7kΩ pull-up resistance)
Additional microcomputer input port 2 (built-in 4.7kΩ pull-up resistance)
Current source reference current input pin for LPF
Operation amplifier reference voltage setting pin for LPF
L-ch audio signal output/serial data output (in external D-A mode)
L-ch current source output/word clock output (in external D-A mode)
R-ch audio signal output/data shift clock output (in external D-A mode)
R-ch current source output/L-R clock output (in external D/A mode)
Detection/PLL circuit reference current input
Analog system power supply
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MITSUBISHI SOUND PROCESSOR ICs
M65824FP
SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/A
ABSOLUTE MAXIMUM RATINGS (Ta=25°C, unless otherwise noted)
Symbol
DVDD-DVSS
AVDD-AVSS
DSPS-DVSS
VI
Vo
Pd
Topr
Tstg
Parameter
Supply voltage (I/O)
Supply voltage (analog)
Supply voltage (internal circuit)
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Ratings
-0.3 to +6.5
-0.3 to +3.6
-0.3 to +3.6
DVDD-0.3≤Vi≤DVDD+0.3
DVSS≤Vo≤DVDD
350
-10 to +70
-40 to +125
Unit
V
V
V
V
V
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
DVDD
AVDD
DSPS
VIH
VOL
fosc
fvco
Test conditions
Parameter
Min.
2.7
2.7
2.7
Supply voltage (I/O)
Supply voltage (analog)
Supply voltage (internal circuit)
Input voltage ("H" level)
Output voltage ("L" level)
Oscillation frequency
Oscillation frequency
DVDD•0.7
DVSS
-
Limits
Typ.
5.0
3.0
3.0
8.4672
8.6436
Max.
5.5
3.3
3.3
DVDD
DVSS•0.3
-
Unit
V
V
V
V
V
MHz
MHz
ELECTRICAL CHARACTERISTICS (Ta=25°C, VDD=5V, unless otherwise noted)
Symbol
IDD
VOH
VOL
IIH
IIL
Test conditions
Parameter
Circuit current
Output voltage ("H" level)
Output voltage ("L" level)
Input voltage ("H" level)
Input voltage ("L" level)
fosc=8.4672MHz fvco=8.6436MHz
DVDD=5.0V IOH=-1.0mA
DVDD=5.0V IOL=1.0mA
VIH=4.5
VIL=0.5V
Min.
4.5
-2
Limits
Typ.
20
-
Max.
-
Unit
0.4
2
-
POWER SUPPLY
VDD:3.6 to 5.5V
VDD:2.7 to 3.3V
M65824FP
M65824FP
VDD:2.7 to 3.3V
DVDD 22
DVDD 22
DSPS 23
DSPS 23
AVDD 42
AVDD 42
Fig.1 3.0V system application example (supply voltage
range of 2.7V to 3.3V)
Fig.2 5.0V system application example (two power
supplies are required)
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mA
V
V
µA
µA
MITSUBISHI SOUND PROCESSOR ICs
M65824FP
SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/A
FUNCTION DESCRIPTION
1. MICROCOMPUTER INTERFACE
(2) Description
(1) Pin assignments
MLAB: Latch signal/data I/O switching signal
M65824FP
31
CD-DA
(MLAB="H":Write from µP)
MSD
I/O
(MLAB="L":Read from µP)
MCK
30
SIGNAL
PROCESSOR
32
MCK: Clock signal
MSD: Serial data I/O
µP
O
MLAB
O
(3) Operation description
• Microcomputer command read/write
Data (MSD) is read at a rising edge of the clock pulse (MCK).
•Status request/interface command
When requesting various types of the M65824FP status, a
When a command is determined at a falling edge of the latch line
microcomputer writes data in D3, D2, D1 and D0 for indicating the
(MLAB), the data line (MSD) is concurrently switched to the output
requested status in advance.
mode to output a status requested by data bits D3, D2, D1 and D0.
After this command is latched, the status is continuously output
When the latch line is set to "H", the data line is returned to the
while the latch line (MLAB) is set to "L".
input mode again.
(4) Microcomputer I/F timing chart
MSD
D0
D1
D2
D3
D4
D5
D6
D7
Symbol
t1
t2
t3
t4
Status
MCK
t1
t2 t3
Parameter
Shift clock width
Shift clock setup
Shift clock hold
Shift clock setup
Min.
200
100
100
100
Unit
nsec
nsec
nsec
nsec
t4
MLAB
(5) M65824FP command list
D7
D6
Disk motor
Initial value after power is turned on: 00000000
D5
D4
D3
Audio function
D2
D1
D0
Status/interface command
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MITSUBISHI SOUND PROCESSOR ICs
M65824FP
SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/A
(6) Detailed data
1
Disk motor control
2
Disk motor off
Accelerates the disk motor. Applies the maximum acceleration voltage to the motor.
Decelerates the disk motor. Applies the maximum deceleration voltage to the motor.
Disk motor CLV control
Audio functions
D5
0
D4
0
1
0
1
0
1
1
3
Function
D6
0
1
0
1
D7
0
0
1
1
Function
Muting
Muting release
Reserved
12 dB attenuation
Status/interface command
D3
D2
D1
Function
D0
0
0
0
0
Detects reduced disk rotating speed. "L" when the disk
rotating speed is 2/3 or more of the normal speed.
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PLL lock status. "L" at locked.
Subcode read status. "L" when new subcode is received
External D-A mode (In case of input after reset)
33
Logical
value of EXP1 (pin 33 )
Logical value of EXP2 (pin 34 )
Reserved
Reserved
PLL loop close (= HFD: "L")
PLL loop open (= HFD: "H")
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
1
0
0
0
0
1
1
1
1
(7) Subcode Q register interface
When the subcode ready status is set to "L", a clock is sent with the
Data of subcode Q is stored in the internal 80-bit register and can
latch line (MLAB) kept set to "L" to read the data of subcode Q from
be read using a microcomputer.
the internal register.
Subcode ready status command is written to read subcode Q using
Read all subcode Q data from the rising edge of SBQS until the next
a microcomputer. (MSD DATA 0100xxxx)
rising edge (for approximately 13.1 msec).
SBQS
MSD
MSD
typ.13.1msec
B1
B2
B3
Don't care
B4
B5
Status
B6
Q1
B7
Q2 Q3
B8
Q4
Q5
B9
Q6 Q7
BA
Q8
Q9 Q10 Q11
Q12~Q79 Q80
MCK
t5
MLAB
t5: Mode setup time (min. 200 nsec)
•SBQS is set to "L" when both the following two conditions are satisfied at the same time.
(a) CRC check OK
(b) When the two subcode syncs (S0, S1) are normal
•A microcomputer can read information on subcode Q using the M65824FP only when SBQS is set to "L".
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MITSUBISHI SOUND PROCESSOR ICs
M65824FP
SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/A
2. DISK MOTOR CONTROL PULSE (CLV mode)
22.6757µsec
PWM1
(ACCELERATION)
Min : 0.2362µsec
Max : 15.117µsec
22.6757µsec
PWM2
(DECELERATION)
Min.: 0.2362µsec
Max.: 15.117µsec
22.6757µsec
(DECELERATION)
Hi-Z
PWM
(BOTH SIDES)
(ACCELERATION)
Min.: 0.2362µsec
Max.: 15.117µsec
Min.: 0.2362µsec
Max.: 15.117µsec
22.6757µsec
3. DIGITAL FILTER
0
0
-0.6
Rejection band (f≥24 kHz)
Attenuation -36 dB
-20
-2
-36
-40
-4
-60
-6
-80
-8
-100
0
20
40
60
80
100
-10
Passing band (f≤20 kHz)
Ripple 0.6 dB
0
20
40
60
80
100
FREQUENCY (kHz)
FREQUENCY (kHz)
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MITSUBISHI SOUND PROCESSOR ICs
M65824FP
SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/A
APPLICATION EXAMPLE
1
AVSS
AVDD 42
2
WDCK
IREF 41
3
LOCK/DRD
RNEG/LRCK 40
4
CKSEL
ROUT/DSCK 39
5
ACLRB
LNEG/WDCK 38
6
C423
LOUT/DO 37
7
C846
AMPREF 36
8
XI
9
DVSS
Audio R
Audio L
LPF
CGREF 35
EXP2 34
10 XO
EXP1 33
11 TEST
MLAB 32
12 SBCO
MSD 31
13 SCCK
MCK 30
14 SYCLK
PWM2 29
15 EFFK
PWM1 28
16 KILLB
PWM 27
17 EST1
SCAND 26
18 EST2
CRCF 25
19 HF
SBQS 24
20 TLC
DSPS 23
21 LPF
DVDD 22
SUBCODE I/F
HF INPUT
LPF
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Disc
Motor
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