ADS8515 SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER FEATURES 1 • • • • • • • • • • Standard ±10-V Input Range 90-dB Min SNR with 20-kHz Input ±2.0 LSB Max INL ±1 LSB Max DNL, 16-Bits No Missing Code 5-V Analog Supply, Flexible I/O Supply Voltage at 1.65 V to 5.25 V Pin-Compatible With ADS7805/10 (Low Speed), and 12-Bit ADS7804/8504 Uses Internal or External Reference Full Parallel Data Output 100-mW Typ Power Dissipation at 250 KSPS 28-Pin SSOP Package DESCRIPTION The ADS8515 is a complete 16-bit sampling A/D converter using state-of-the-art CMOS structures. It contains a complete 16-bit, capacitor-based, SAR A/D with S/H, reference, clock, interface for microprocessor use, and 3-state output drivers. The ADS8515 is specified at a 250-kHz sampling rate over the full temperature range. Precision resistors provide an industry standard ±10-V input range, while the innovative design allows operation from a single +5-V supply, with power dissipation under 100 mW. The ADS8515 is available in a 28-pin SSOP package and is fully specified for operation over the industrial -40°C to 85°C temperature range. APPLICATIONS • • • • • Industrial Process Control Data Acquisition Systems Digital Signal Processing Medical Equipment Instrumentation Clock Successive Approximation Register and Control Logic R/C CS BYTE BUSY CDAC 7 kΩ ± 10 V Input 2 kΩ 25.67 kΩ Comparator Output Latches and Three State Drivers Three State Parallel Data Bus CAP Buffer Internal +4.096 V Ref 4 kΩ REF 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PACKAGE/ORDERING INFORMATION (1) PRODUCT MINIMUM INL (LSB) NO MISSING CODE MINIMUM SINAD (dB) SPECIFICATION TEMPERATURE RANGE PACKAGE LEAD PACKAGE DESIGNATOR ADS8515IB ±2 16 89 -40°C to 85°C SSOP-28 DB ADS8515I (1) ±3 16 87 -40°C to 85°C SSOP-28 ORDERING NUMBER ADS8515IBDB ADS8515IBDBR ADS8515IDB DB ADS8515IDBR TRANSPORT MEDIA, QTY Tube, 50 Tape and Reel, 2000 Tube, 50 Tape and Reel, 2000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) (2) ADS8515 Analog inputs Ground voltage differences VIN ±25V CAP +VANA + 0.3 V to AGND2 - 0.3 V REF Indefinite short to AGND2, momentary short to VANA DGND, AGND1, AGND2 ±0.3 V VANA 6V VDIG to VANA 0.3 V VDIG 6V Digital inputs -0.3 V to +VDIG + 0.3 V Maximum junction temperature 165°C Internal power dissipation 825 mW Lead temperature (soldering, 10s) (1) (2) 300°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. ELECTRICAL CHARACTERISTICS TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted) ADS8515I PARAMETER ADS8515IB TEST CONDITIONS UNIT MIN TYP MAX Resolution MIN TYP 16 MAX 16 Bits ANALOG INPUT Voltage range Impedance Capacitance ±10 ±10 8.885 8.885 kΩ V 75 75 pF THROUGHPUT SPEED Conversion cycle time Acquire and convert Throughput rate 4 250 4 250 µs kHz DC ACCURACY INL Integral linearity error -3 3 -2 2 LSB (1) DNL Differential linearity error -1 2 -1 1 LSB (1) No missing codes 16 Transition noise (2) (1) (2) 2 16 0.67 Bits 0.67 LSB LSB means least significant bit. For the 16-bit, ±10-V input ADS8515, one LSB is 305 µV. Typical rms noise at worst case transitions and temperatures. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8515 ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted) ADS8515I PARAMETER UNIT MIN Full-scale error (3) (4) Int. Ref. Full-scale error drift Int. Ref. Full-scale error (3) (4) Ext. 4.096-V Ref. Full-scale error drift Ext. 4.096-V Ref. TYP -0.5 MAX MIN 0.5 -0.25 ±7 -0.25 -4 Bipolar zero error drift 0.25 -0.1 4 -2 -8 MAX 0.25 0.1 -8 %FSR ppm/°C 2 ±2 8 %FSR ppm/°C ±2 ±2 +4.75 V < VD < +5.25 V TYP ±7 ±2 Bipolar zero error (3) Power supply sensitivity (VDIG = VANA = VD) ADS8515IB TEST CONDITIONS mV ppm/°C 8 LSB AC ACCURACY SFDR Spurious-free dynamic range fI = 20 kHz THD Total harmonic distortion fI = 20 kHz SINAD Signal-to-(noise+distortion) 95 fI = 20 kHz 87 –60-dB Input SNR Signal-to-noise ratio 102 -100 97 -94 91 89 30 fI = 20 kHz 88 Full-power bandwidth (6) 92 90 500 dB (5) 102 -100 -96 dB 91 dB 32 dB 92 dB 500 kHz SAMPLING DYNAMICS Aperture delay Transient response 5 FS Step 5 2 Overvoltage recovery (7) ns 2 150 150 µs ns REFERENCE Internal reference voltage 4.076 4.096 4.116 4.076 4.096 4.116 V Internal reference source current (must use external buffer) 1 1 µA Internal reference drift 8 8 ppm/°C External reference voltage range for specified linearity External reference current drain 3.9 4.096 Ext. 4.096-V Ref. 4.2 3.9 100 4.096 4.2 V 100 µA V DIGITAL INPUTS Logic levels VIL Low-level input voltage VDIG = 1.65 V – 5.25 V -0.3 0.8 -0.3 0.35*VDIG VIH High-level input voltage VDIG = 1.65 V – 5.25 V 0.65*VDIG VDIG+0.3 V 0.65*VDIG VDIG+0.3 V V IIL Low-level input current VIL = 0 V ±10 ±10 µA IIH High-level input current VIH = 5 V ±10 ±10 µA 0.4 V DIGITAL OUTPUTS Data format (Parallel 16-bits) Data coding (Binary 2's complement) VOL Low-level output voltage ISINK = 1.6 mA VOH High-level output voltage ISOURCE = 500 µA 0.4 Leakage current Hi-Z state, VOUT = 0 V to VDIG ±5 ±5 µA Output capacitance Hi-Z state 15 15 pF Bus access timing 83 83 ns Bus relinquish timing 83 83 ns 0.8×VDIG 0.8×VDIG V DIGITAL TIMING POWER SUPPLIES (3) (4) (5) (6) (7) As measured with fixed resistors shown in Figure 22. Adjustable to zero with external potentiometer. Full-scale error is the worst case of -full-scale or +full-scale deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. All specifications in dB are referred to a full-scale ±10-V input. Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB, or 10 bits of accuracy. Recovers to specified performance after 2 x FS input overvoltage. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8515 3 ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted) ADS8515I PARAMETER UNIT MIN VDIG Digital input voltage 1.65 VANA Analog input voltage 4.75 IDIG Digital input current IANA Analog input current Power dissipation ADS8515IB TEST CONDITIONS Must be ≤ VANA fS = 250 kHz TYP MAX MIN 5.25 1.65 5 5.25 4.75 0.1 1 TYP MAX 5.25 5 5.25 0.1 1 V V mA 20 25 20 25 mA 100 125 100 125 mW TEMPERATURE RANGE Specified performance -40 85 -40 85 °C Derated performance (8) -55 125 -55 125 °C Storage -65 150 -65 150 °C THERMAL RESISTANCE (ΘJA) SSOP (8) 4 67 67 °C/W The internal reference may not be started correctly beyond the industrial temperature range (-40°C to 85°C), therefore use of an external reference is recommended. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8515 ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 DEVICE INFORMATION DB PACKAGE (TOP VIEW) VIN 1 AGND1 2 28 VDIG 27 VANA REF 3 26 BUSY CAP 4 25 CS AGND2 5 D15 (MSB) 6 24 R/C 23 BYTE D14 7 22 D0 (LSB) D13 8 21 D1 D12 9 20 D2 D11 10 19 D3 D10 11 18 D4 D9 12 17 D5 D8 13 16 D6 DGND 14 15 D7 Terminal Functions TERMINAL NAME SSOP NO. DIGITAL I/O DESCRIPTION AGND1 2 Analog ground. Used internally as ground reference point. AGND2 5 Analog ground. BUSY 26 O At the start of a conversion, BUSY goes low and stays low until the conversion is completed and the digital outputs have been updated. BYTE 23 I Selects 8 most significant bits (low) or 8 least significant bits (high). CAP 4 CS 25 Reference buffer capacitor. 2.2-µF tantalum capacitor to ground. DGND 14 D15 (MSB) 6 O Data bit 15. Most significant bit (MSB) of conversion results. Hi-Z state when CS is high, or when R/C is low. D14 7 O Data bit 14. Hi-Z state when CS is high, or when R/C is low. D13 8 O Data bit 13. Hi-Z state when CS is high, or when R/C is low. D12 9 O Data bit 12. Hi-Z state when CS is high, or when R/C is low. D11 10 O Data bit 11. Hi-Z state when CS is high, or when R/C is low. D10 11 O Data bit 10. Hi-Z state when CS is high, or when R/C is low. D9 12 O Data bit 9. Hi-Z state when CS is high, or when R/C is low. D8 13 O Data bit 8. Hi-Z state when CS is high, or when R/C is low. D7 15 O Data bit 7. Hi-Z state when CS is high, or when R/C is low. D6 16 O Data bit 6. Hi-Z state when CS is high, or when R/C is low. D5 17 O Data bit 5. Hi-Z state when CS is high, or when R/C is low. D4 18 O Data bit 4. Hi-Z state when CS is high, or when R/C is low. D3 19 O Data bit 3. Hi-Z state when CS is high, or when R/C is low. D2 20 O Data bit 2. Hi-Z state when CS is high, or when R/C is low. D1 21 O Data bit 1. Hi-Z state when CS is high, or when R/C is low. I Internally ORed with R/C. If R/C low, a falling edge on CS initiates a new conversion. Digital ground. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8515 5 ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 Terminal Functions (continued) D0 (LSB) 22 O Data bit 0. Least significant bit (LSB) of conversion results. Hi-Z state when CS is high, or when R/C is low. R/C 24 I With CS low and BUSY high, a falling edge on R/C initiates a new conversion. With CS low, a rising edge on R/C enables the parallel output. REF 3 Reference input/output. 2.2-µF tantalum capacitor to ground. VANA 27 Analog supply input. Nominally +5 V. Decouple to ground with 0.1-µF ceramic and 10-µF tantalum capacitors. VDIG 28 Digital supply input. Nominally +5 V. Connect directly to pin 27. Must be ≤ VANA. VIN 1 Analog input. See Figure 24 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY 95 95 90 85 80 75 10 100 fi - Input Frequency - kHz 80 75 10 100 fi - input frequency - kHz 85 80 75 70 1 1000 10 100 fi - input frequency - kHz 1000 Figure 2. Figure 3. SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE AND DISTORTION vs FREE-AIR TEMPERATURE 100 95 90 85 80 75 95 SINAD - Signal to Noise and Distortion - dB 100 SNR - Signal-to-Noise Ratio - dB SFDR - Spurious Free Dynamic Range 85 90 Figure 1. 105 fs = 250 KSPS fi = 20 kHz 90 85 80 75 70 70 1 10 100 fi - input frequency - kHz 1000 Figure 4. 6 90 70 1 1000 95 SINAD - Signal to Noise and Distortion - dB SNR - Signal-to-Noise Ratio - dB THD - Total Harmonic Distortion - dB 100 70 1 SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY -55 -40 -25-10 5 20 35 50 65 80 95 110 125 TA - Free-Air-Temperature - °C Figure 5. Submit Documentation Feedback 100 95 fs = 250 KSPS fi = 20 kHz 90 85 80 75 70 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air-Temperature - °C Figure 6. Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8515 ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE 100 4.1 85 80 75 fs = 250 KSPS fi = 20 kHz 70 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air-Temperature - °C fs = 250 KSPS fi = 20 kHz -75 -80 -85 -90 -95 4.099 4.098 4.097 4.096 4.095 4.094 4.093 4.092 4.091 4.09 -40 -100 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air-Temperature - °C -25 -10 5 20 35 50 65 TA - Free-Air-Temperature - °C Figure 8. Figure 9. BIPOLAR ZERO ERROR vs FREE-AIR TEMPERATURE NEGATIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE NEGATIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 3 2 1 0 -1 -2 -3 -25 -10 5 20 35 50 65 TA - Free-Air-Temperature - °C 0.1 Internal Reference 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 -40 80 NFS - Negative Full-Scale Error - %FSR 0.2 NFS - Negative Full-Scale Error - %FSR 0.25 4 -25 -10 5 20 35 50 65 0.08 External Reference 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.1 -40 80 -25 -10 5 20 35 50 65 Figure 11. Figure 12. POSITIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE POSITIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 0.1 PFS - Positive Full-Scale Error - %FSR Internal Reference 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 -40 -25 -10 5 20 35 50 65 80 TA - Free-Air-Temperature - °C Figure 13. 0.08 0.025 External Reference 0.06 IDD - Supply Current - mA 0.25 80 TA - Free-Air-Temperature - °C TA - Free-Air-Temperature - °C Figure 10. 0.2 80 Figure 7. 5 -5 -40 VREF - Internal Reference Voltage - V THD - Total Harmonic Distortion - dB 90 -4 PFS - Positive Full-Scale Error - %FSR INTERNAL REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE -70 95 BPZ - Bipolar Zero Error - mV SFDR - Spurious Free Dynamic Range - dB SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 0.04 0.02 0 -0.02 -0.04 -0.06 0.023 0.021 0.019 0.017 -0.08 -0.1 -40 -25 -10 5 20 35 50 65 TA - Free-Air-Temperature - °C Figure 14. 80 0.015 -40 -25 -10 5 20 35 50 Product Folder Link(s): ADS8515 80 Figure 15. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated 65 TA - Free-Air-Temperature - °C 7 ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) HISTOGRAM 4500 4103 4000 3645 3500 Count 3000 2500 2000 1500 1000 335 500 0 0 109 0 0 0 65529 65531 65533 65535 65530 65532 65534 65536 Code Figure 16. INL 2 1.5 1 INL - lsb 0.5 0 -0.5 -1 -1.5 -2 0 10000 20000 30000 40000 50000 60000 70000 Code Figure 17. DNL 2 1.5 DNL - lsb 1 0.5 0 -0.5 -1 -1.5 -2 0 10000 20000 30000 40000 50000 60000 70000 Code Figure 18. BASIC OPERATION Figure 19 shows a basic circuit to operate the ADS8515 with a full parallel data output. Taking R/C (pin 24) low for a minimum of 40 ns initiates a conversion. BUSY (pin 26) goes low and stays low until the conversion is completed and the output registers are updated. Data is output in binary 2's complement with the MSB on pin 6. BUSY going high can be used to latch the data. 8 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8515 ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 The ADS8515 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convert commands assures accurate acquisition of a new signal. STARTING A CONVERSION The combination of CS (pin 25) and R/C (pin 24) low for a minimum of 40 ns immediately puts the sample/hold of the ADS8515 in the hold state and starts conversion n. BUSY (pin 26) goes low and stays low until conversion n is completed and the internal output register has been updated. The ADS8515 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convert commands assures accurate acquisition of a new signal. Refer to Table 1 for a summary of CS, R/C, and BUSY states and Figure 21, Figure 22, and Figure 23 for the timing diagrams. CS and R/C are internally ORed and level triggered. There is not a requirement which input goes low first when initiating a conversion. If, however, it is critical that CS or R/C initiates conversion n, be sure the less critical input is low at least 10 ns prior to the initiating input. To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. The parallel output becomes active whenever R/C goes high. Refer to the Reading Data section. Table 1. Control Line Functions for Read and Convert (1) CS R/C BUSY OPERATION 1 X X None. Databus is in Hi-Z state. ↓ 0 1 Initiates conversion n. Databus remains in Hi-Z state. 0 ↓ 1 Initiates conversion n. Databus enters Hi-Z state. 0 1 ↑ Conversion n completed. Valid data from conversion n on the databus. ↓ 1 1 Enables databus with valid data from conversion n. ↓ 1 0 Enables databus with valid data from conversion –1 (1). Conversion n in progress. 0 ↑ 0 Enables databus with valid data from conversion –1 (1). Conversion n in progress. 0 0 ↑ New conversion initiated without acquisition of a new signal. Data is invalid. CS and/or R/C must be high when BUSY goes high. X X 0 Conversion n in progress. See Figure 21 and Figure 22 for constraints on data valid from conversion n-1. 1 28 2 27 3 26 4 25 5 24 D15 (MSB) 6 23 D14 7 D13 + 2.2 µF 2.2 µF + + 0.1 µF +5V + 10 µF BUSY Convert Pulse R/C 22 D0 (LSB) 8 21 D1 D12 9 20 D2 D11 10 19 D3 D10 11 18 D4 D9 12 17 D5 D8 13 16 D6 14 15 D7 ADS8515 40 ns Min Figure 19. Basic Operation Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8515 9 ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 READING DATA The ADS8515 outputs full or byte-reading parallel data in binary 2's complement data output format. The parallel output is active when R/C (pin 24) is high and CS (pin 25) is low. Any other combination of CS and R/C 3-states the parallel output. Valid conversion data can be read in a full parallel, 16-bit word or two 8-bit bytes on pins 6-13 and pins 15-22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle. Refer to Table 2 for ideal output codes and Figure 20 for bit locations relative to the state of BYTE. Table 2. Ideal Input Voltages and Output Codes DESCRIPTION ANALOG INPUT Full-scale range ±10 V DIGITAL OUTPUT BINARY 2's COMPLEMENT BINARY CODE HEX CODE 7FFF Least significant bit (LSB) 305 µV Full scale (10 V-1 LSB) 9.999695 V 0111 1111 1111 1111 Midscale 0V 0000 0000 0000 0000 0000 One LSB below midscale -305 µV 1111 1111 1111 1111 FFFF -Full scale -10 V 1000 0000 0000 0000 8000 PARALLEL OUTPUT (After a Conversion) After conversion n is completed and the output registers have been updated, BUSY (pin 26) goes high. Valid data from conversion n is available on D15-D0 (pins 6-13 and 15-22). BUSY going high can be used to latch the data. Refer to Table 3 and Figure 21, Figure 22, and Figure 23 for timing specifications. PARALLEL OUTPUT (During a Conversion) After conversion n has been initiated, valid data from conversion –1 can be read and is valid up to t2 after the start of conversion n. Do not attempt to read data from t2 after the start of conversion n until BUSY (pin 26) goes high; this may result in reading invalid data. Refer to Table 3 and Figure 21, Figure 22, and Figure 23 for timing specifications. Note: For the best possible performance, data should not be read during a conversion. The switching noise of the asynchronous data transfer can cause digital feedthrough degrading the converter's performance. The number of control lines can be reduced by tying CS low while using the falling edge of R/C to initiate conversions and the rising edge of R/C to activate the output mode of the converter. See Figure 21. Table 3. Conversion Timing SYMBOL MIN TYP MAX UNITS 0.8 1.2 µs 6 20 ns 2 µs tw1 Pulse duration, convert ta Access time, data valid after R/C low tpd Propagation delay time, BUSY from R/C low tw2 Pulse duration, BUSY low td1 Delay time, BUSY after end of conversion 5 td2 Delay time, aperture 5 40 ns tconv Conversion time tacq Acquisition time 2 tdis Disable time, bus 10 15 td3 Delay time, BUSY after data valid 35 50 tv Valid time, previous data remains valid after R/C low 1.5 2 tconv + tacq 10 DESCRIPTION Setup time, R/C to CS ns 2 µs µs Throughput time tsu ns 83 ns ns µs 4 10 µs ns µs tc Cycle time between conversions 4 ten Enable time, bus 10 15 30 ns td4 Delay time, BYTE 10 15 30 ns Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8515 ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 BYTE LOW BYTE HIGH +5 V Bit 15 (MSB) 6 23 Bit 7 6 22 Bit 0 (LSB) Bit 6 7 Bit 13 8 21 Bit 1 Bit 5 8 21 Bit 9 Bit 12 9 20 Bit 2 Bit 4 9 20 Bit 10 Bit 11 10 19 Bit 3 Bit 3 10 19 Bit 11 Bit 10 11 18 Bit 4 Bit 2 11 18 Bit 12 Bit 9 12 17 Bit 5 Bit 1 12 17 Bit 13 Bit 8 13 16 Bit 6 Bit 0 (LSB) 13 16 Bit 14 14 15 Bit 7 14 Bit 14 7 ADS8515 23 22 Bit 8 ADS8515 15 Bit 15 (MSB) Figure 20. Bit Locations Relative to State of BYTE (Pin 23) tw1 R/C tc ta1 tw2 BUSY tpd td2 td1 Acquire MODE Convert Acquire tconv DATA BUS Previous Data Valid Previous Data Valid Hi−Z Convert tacq Not Valid Data Valid Hi−Z Data Valid td3 tdis tv Figure 21. Conversion Timing with Outputs Enabled after Conversion (CS Tied Low) tsu tsu tsu tsu R/C tw1 CS tpd tw2 BUSY td2 MODE Acquire Convert Acquire tconv DATA BUS Hi−Z State Data Valid ten Hi−Z State tdis Figure 22. Using CS to Control Conversion and Read Timing Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8515 11 ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 tsu tsu R/C CS BYTE Pins 6 − 13 Hi−Z Pins 15 − 22 Hi−Z High Byte Low Byte ten td4 Low Byte High Byte Hi−Z tdis Hi−Z Figure 23. Using CS and BYTE to Control Data Bus ADC RESET The ADC reset function of the ADS8515 can be used to terminate the current conversion cycle. Bringing R/C low for at least 40 ns while BUSY is low will initiate the ADC reset. To initiate a new conversion, R/C must return to the high state and remain high long enough to acquire a new sample (see Table 3, tc) before going low to initiate the next conversion sequence. In applications that do not monitor the BUSY signal, it is recommended that the ADC reset function be implemented as part of a system initialization sequence. INPUT RANGES The ADS8515 offers a standard ±10-V input range. Figure 24 shows the necessary circuit connections for the ADS8515 with and without hardware trim. Offset and full-scale error specifications are tested and specified with the fixed resistors shown in Figure 25(b). Full-scale error includes offset and gain errors measured at both +FS and -FS. Adjustments for offset and gain are described in the Calibration section of this data sheet. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the Calibration section). The nominal input impedance of 6.35 kΩ results from the combination of the internal resistor network shown on the front page of the product data sheet. The input resistor divider network provides inherent overvoltage protection assured to at least ±25 V. The 1% resistors used for the external circuitry do not compromise the accuracy or drift of the converter. They have little influence relative to the internal resistors, and tighter tolerances are not required. The input signal must be referenced to AGND1. This minimizes the ground loop problem typical to analog designs. The analog signal should be driven by a low impedance source. A typical driving circuit using an OPA627 or OPA132 is shown in Figure 24. 12 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8515 ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 +15V 2.2 mF 22 pF ADS8515 100 nF VIN GND 2 kW Pin 7 2 kW Vin Pin 2 22 pF Pin3 Pin 1 − OPA 627 or OPA 132 + REF 2.2 mF Pin 6 AGND1 Pin4 GND CAP 2.2 mF GND 100 nF 2.2 mF DGND GND AGND2 GND −15 V GND Figure 24. Typical Driving Circuit (±10 V, No Trim) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8515 13 ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 APPLICATION INFORMATION CALIBRATION The gain of the ADS8515 can be trimmed in software. To achieve optimum performance, several iterations may be required. Hardware Calibration To calibrate the gain of the ADS8515, install the resistors and potentiometer as shown in Figure 25(a). The calibration range is approximately ±100 mV. Software Calibration The offset and gain of the ADS8515 is calibrated with software. See Figure 25(b) for the circuit connections. 1 ±10 V 2 +5 V 2.2 µF + 175 kΩ 20 kΩ 4 + Gain 2.2 µF 30 kΩ 3 5 VIN 1 ±10 V 2 AGND1 2.2 µF + REF 4 CAP 2.2 µF AGND2 (a) ±10 V With Hardware Trim 3 VIN AGND1 REF CAP + 5 AGND2 (b) ±10 V Without Hardware Trim Note: Use 1% metal film resistors. Figure 25. Circuit Diagram For Software Trim REFERENCE The ADS8515 can operate with its internal 4.096-V reference or an external reference. By applying an external reference to pin 5, the internal reference can be bypassed. The reference voltage at REF is buffered internally with the output on CAP (pin 4). The internal reference has an 8 ppm/°C drift (typical) and accounts for approximately 20% of the full-scale error (FSE = ±0.5% for low grade, ±0.25% for high grade). REF REF (pin 3) is an input for an external reference or the output for the internal 4.096-V reference. A 2.2-µF capacitor should be connected as close to the REF pin as possible. The capacitor and the output resistance of REF create a low-pass filter to bandlimit noise on the reference. Using a smaller value capacitor introduces more noise to the reference degrading the SNR and SINAD. The REF pin should not be used to drive external ac or dc loads. The range for the external reference is 3.9 V to 4.2 V and determines the actual LSB size. Increasing the reference voltage increases the full-scale range and the LSB size of the converter which can improve the SNR. 14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8515 ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 CAP CAP (pin 4) is the output of the internal reference buffer. A 2.2-µF capacitor should be placed as close to the CAP pin as possible to provide optimum switching currents for the CDAC throughout the conversion cycle and compensation for the output of the internal buffer. Using a capacitor any smaller than 1 µF can cause the output buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2 µF have little affect on improving performance. The ESR (equivalent series resistance) of these compensation capacitors is also critical. Keep the total ESR under 3 Ω. See Typical Characteristics section for how the worst case ILE is affected by ESR. The output of the buffer is capable of driving up to 2 mA of current to a dc load, but any external load from the CAP pin may degrade the linearity of the ADS8515. Using an external buffer allows the internal reference to be used for larger dc loads and ac loads. Do not attempt to directly drive an ac load with the output voltage on CAP. This causes performance degradation of the converter. The ESR (equivalent series resistance) of these compensation capacitors is also critical. Keep the total ESR under 3 Ω. See the TYPICAL CHARACTERISTICS section concerning how ESR affects performance. LAYOUT POWER For optimum performance, tie the analog and digital power pins to the same +5-V power supply and tie the analog and digital grounds together. As noted in the electrical specifications, the ADS8515 uses 90% of its power for the analog circuitry. The ADS8515 should be considered as an analog component. The +5-V power for the A/D should be separate from the +5 V used for the system's digital logic. Connecting VDIG (pin 28) directly to a digital supply can reduce converter performance due to switching noise from the digital logic. For best performance, the +5-V supply can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If +12-V or +15-V supplies are present, a simple +5-V regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG and VANA should be tied to the same +5-V source. GROUNDING Three ground pins are present on the ADS8515. DGND is the digital supply ground. AGND2 is the analog supply ground. AGND1 is the ground which all analog signals internal to the A/D are referenced. AGND1 is more susceptible to current induced voltage drops and must have the path of least resistance back to the power supply. All the ground pins of the A/D should be tied to the analog ground plane, separated from the system's digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the system ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground. SIGNAL CONDITIONING The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The FET switch on the ADS8515, compared to the FET switches on other CMOS A/D converters, releases 5%-10% of the charge. There is also a resistive front end which attenuates any charge which is released. The end result is a minimal requirement for the anti-alias filter on the front end. Any op amp sufficient for the signal in an application is sufficient to drive the ADS8515. The resistive front end of the ADS8515 also provides an assured ±25-V overvoltage protection. In most cases, this eliminates the need for external input protection circuitry. INTERMEDIATE LATCHES The ADS8515 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus is to be active during conversions. If the bus is not active during conversion, the 3-state outputs can be used to isolate the A/D from other peripherals on the same bus. The 3-state outputs can also be used when the A/D is the only peripheral on the data bus. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8515 15 ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 Intermediate latches are beneficial on any monolithic A/D converter. The ADS8515 has an internal LSB size of 38 µV. Transients from fast switching signals on the parallel port, even when the A/D is 3-stated, can be coupled through the substrate to the analog circuitry causing degradation of converter performance. 16 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8515 ADS8515 www.ti.com SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 Revision History Changes from Original (June 2007) to Revision A ......................................................................................................... Page • Changed ADS8515I VIH MIN from 2 V to 0.65*VDIG .............................................................................................................. 3 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8515 17 PACKAGE OPTION ADDENDUM www.ti.com 29-Aug-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS8515IBDBR ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8515IBDBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8515IDB ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8515IDBG4 ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8515IDBR ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8515IDBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8515IBDBR DB 28 SITE 60 330 16 8.1 10.4 2.5 12 16 Q1 ADS8515IDBR DB 28 SITE 60 330 16 8.2 10.5 2.5 12 16 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) ADS8515IBDBR DB 28 SITE 60 346.0 346.0 33.0 ADS8515IDBR DB 28 SITE 60 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. 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