® ADS ADS7821 782 1 ADS 782 1 16-Bit 10µs Sampling CMOS ANALOG-to-DIGITAL CONVERTER FEATURES DESCRIPTION ● 100kHz min SAMPLING RATE ● 0 to +5V INPUT RANGE The ADS7821 is a complete 16-bit sampling A/D using state-of-the-art CMOS structures. It contains a complete 16-bit, capacitor-based, SAR A/D with S/H, reference, clock, interface for microprocessor use, and three-state output drivers. The ADS7821 is specified at a 100kHz sampling rate, and guaranteed over the full temperature range. Lasertrimmed scaling resistors provide a 0 to +5V input range, with power dissipation under 100mW. The 28-pin ADS7821 is available in a plastic 0.3" DIP and in an SOIC, both fully specified for operation over the –25°C to +85°C range. ● 86dB min SINAD WITH 20kHz INPUT ● DNL: 16-bits “No Missing Codes” ● SINGLE +5V SUPPLY OPERATION ● PIN-COMPATIBLE WITH 12-BIT ADS7820 ● USES INTERNAL OR EXTERNAL REFERENCE ● FULL PARALLEL DATA OUTPUT ● 100mW max POWER DISSIPATION ● 28-PIN 0.3" PLASTIC DIP AND SOIC Clock Successive Approximation Register and Control Logic R/C CS BYTE BUSY CDAC 5kΩ 0 to +5V Input 6.66kΩ 20kΩ Comparator Output Latches and Three State Drivers Three State Parallel Data Bus CAP Internal +2.5V Ref Buffer 4kΩ REF International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1996 Burr-Brown Corporation PDS-1323A 1 Printed in U.S.A. June, 1996 ADS7821 SPECIFICATIONS ELECTRICAL TA = –25°C to +85°C, fS = 100kHz, VDIG = VANA = VD = +5V, using external reference, unless otherwise specified. ADS7821P, U PARAMETER CONDITIONS MIN TYP RESOLUTION ADS7821PB, UB MAX MIN TYP 16 ANALOG INPUT Voltage Range Impedance Capacitance DC ACCURACY Integral Linearity Error No Missing Codes Transition Noise(2) Full Scale Error(3,4) Full Scale Error Drift Full Scale Error(3,4) Full Scale Error Drift Offset Error Offset Error Drift Power Supply Sensitivity (VDIG = VANA = VD) AC ACCURACY Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) Signal-to-Noise Full-Power Bandwidth(6) SAMPLING DYNAMICS Aperture Delay Transient Response Overvoltage Recovery(7) REFERENCE Internal Reference Voltage Internal Reference Source Current (Must use external buffer) Internal Reference Drift External Reference Voltage Range for Specified Linearity External Reference Current Drain Acquire and Convert 10 ±4 15 ±2 ±7 ±2 +4.75V < VD < +5.25V Output Capacitance ±5 ±8 ±12 ±8 –94 30 86 ✱ ✱ 40 ✱ 2 ✱ 150 2.5 1 8 2.5 2.52 ✱ 2.7 ✱ ✱ ✱ ✱ ✱ ✱ dB(5) dB dB dB dB kHz ns µs ns V µA ✱ ppm/°C V ✱ µA ✱ ✱ ✱ ✱ V V µA µA ✱ ✱ V V µA 15 ✱ pF 83 83 ✱ ✱ ns ns 100 DIGITAL TIMING Bus Access Time Bus Relinquish Time ±4 86 FS Step +4 ±0.25 94 83 ISINK = 1.6mA ISOURCE = 500µA High-Z State, VOUT = 0V to VDIG High-Z State LSB(1) Bits LSB % ppm/°C % ppm/°C mV ppm/°C LSB ✱ 28 –0.3 +2.0 DIGITAL OUTPUTS Data Format Data Coding VOL VOH Leakage Current ±0.5 83 Ext. 2.5000V Ref ±3 ±0.25 250 DIGITAL INPUTS Logic Levels VIL VIH IIL IIH µs kHz ✱ –90 2.3 ✱ ✱ ±0.5 90 2.48 V kΩ pF 16 0.9 fIN = 20kHz fIN = 20kHz fIN = 20kHz fIN = –60dB Input fIN = 20kHz Bits ✱ 100 Internal Reference Internal Reference UNITS ✱ ✱ ✱ ✱ 0 to +5 10 35 THROUGHPUT SPEED Conversion Cycle Throughput Rate MAX +0.8 VD +0.3V ±10 ±10 ✱ ✱ Parallel 16 bits Straight Binary +0.4 ✱ ±5 The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS7821 2 SPECIFICATIONS (CONT) ELECTRICAL TA = –25°C to +85°C, f S = 100kHz, VDIG = VANA = VD = +5V, using external reference, unless otherwise specified. ADS7821P, U PARAMETER POWER SUPPLIES Specified Performance VDIG VANA IDIG IANA Power Dissipation ADS7821PB, UB CONDITIONS MIN TYP MAX Must be ≤ VANA +4.75 +4.75 +5 +5 0.3 16 +5.25 +5.25 fS = 100kHz MIN ✱ ✱ TYP ✱ ✱ ✱ ✱ 100 TEMPERATURE RANGE Specified Performance Derated Performance Storage Thermal Resistance (θJA) Plastic DIP SOIC –25 –55 –65 +85 +125 +150 75 75 ✱ ✱ ✱ ✱ ✱ MAX UNITS ✱ ✱ ✱ V V mA mA mW ✱ ✱ ✱ °C °C °C °C/W °C/W NOTES: (1) LSB means Least Significant Bit. For the 16-bit, 0 to +5V input ADS721, one LSB is 76µV. (2) Typical rms noise at worst case transitions and temperatures. (3) Adjustable to zero with external potentiometer as shown in Figure 6a. (4) Full scale error is the worst case of Full Scale untrimmed deviation from ideal last code transition divided by the transition voltage and includes the effect of offset error. (5) All specifications in dB are referred to a full-scale input. (6) FullPower Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified performance after 2 x FS input overvoltage. ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Analog Inputs: VIN ...................................................... –0.7V to VANA +0.3V REF ................................... AGND2 –0.3V to +VANA +0.3V CAP .......................................... Indefinite Short to AGND2, Momentary Short to VANA Ground Voltage Differences: DGND, AGND1, AGND2 ................... ±0.3V VANA ....................................................................................................... 7V VDIG to VANA ..................................................................................... +0.3V VDIG ....................................................................................................... 7V Digital Inputs ............................................................ –0.3V to +VDIG +0.3V Maximum Junction Temperature ................................................... +165°C Internal Power Dissipation ............................................................. 825mW Lead Temperature (soldering, 10s) ................................................ +300°C Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PACKAGE INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) ADS7821P ADS7821PB ADS7821U ADS7821UB Plastic DIP Plastic DIP SOIC SOIC 246 246 217 217 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ORDERING INFORMATION PRODUCT ADS7821P ADS7821PB ADS7821U ADS7821UB MAXIMUM LINEARITY ERROR (LSB) MINIMUM SIGNAL-TO(NOISE + DISTORTION) RATIO (dB) ±4 ±3 ±4 ±3 83 86 83 86 SPECIFICATION TEMPERATURE RANGE PACKAGE –25°C –25°C –25°C –25°C Plastic DIP Plastic DIP SOIC SOIC to to to to +85°C +85°C +85°C +85°C ® 3 ADS7821 DIGITAL I/O PIN # NAME 1 VIN DESCRIPTION 2 AGND1 3 REF Reference Input/Output. 2.2µF tantalum capacitor to ground. Reference Buffer Capacitor. 2.2µF tantalum capacitor to ground. Analog Input. Analog Ground. Used internally as ground reference point. 4 CAP 5 AGND2 6 D15 (MSB) O Data Bit 15. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW. 7 D14 O Data Bit 14. Hi-Z state when CS is HIGH, or when R/C is LOW. 8 D13 O Data Bit 13. Hi-Z state when CS is HIGH, or when R/C is LOW. 9 D12 O Data Bit 12. Hi-Z state when CS is HIGH, or when R/C is LOW. 10 D11 O Data Bit 11. Hi-Z state when CS is HIGH, or when R/C is LOW. 11 D10 O Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW. 12 D9 O Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW. 13 D8 O Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW. 14 DGND 15 D7 O Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW. 16 D6 O Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW. 17 D5 O Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW. 18 D4 O Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW. 19 D3 O Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW. 20 D2 O Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW. 21 D1 O Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW. 22 D0 (LSB) O Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW. 23 BYTE I Swaps Pins 6 through 13 with Pins 15 through 22 when HIGH. See Figures 2 and 5. 24 R/C I With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C enables the parallel output. Analog Ground. Digital Ground. 25 CS I Internally OR’d with R/C. If R/C LOW, a falling edge on CS initiates a new conversion. 26 BUSY O At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs have been updated. 27 VANA Analog Supply Input. Nominally +5V. Decouple to ground with 0.1µF ceramic and 10µF tantalum capacitors. 28 VDIG Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be ≤ VANA. TABLE I. Pin Assignments. PIN CONFIGURATION VIN 1 28 VDIG AGND1 2 27 VANA REF 3 26 BUSY CAP 4 25 CS AGND2 5 24 R/C D15 (MSB) 6 23 BYTE D14 7 22 D0 (LSB) ADS7821 D13 8 21 D1 D12 9 20 D2 D11 10 19 D3 D10 11 18 D4 D9 12 17 D5 D8 13 16 D6 DGND 14 15 D7 ® ADS7821 4 TYPICAL PERFORMANCE CURVES TA = –25°C to +85°C, f S = 100kHz, VDIG = V ANA = +5V, using external reference, unless otherwise specified. INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 8.00 2.52 7.90 2.515 Internal Reference (V) Conversion Time (µs) CONVERSION TIME vs TEMPERATURE 7.80 7.70 7.60 7.50 7.40 7.30 2.51 2.505 2.5 2.495 2.49 2.485 7.20 2.48 –25 0 25 50 75 –25 0 Temp (°C) Min/Max DNL Errors –0.740 at 36431 1.070 at 32767 50 75 Min/Max INL Errors –0.900 at 12447 1.910 at 32767 +2.0 +1.0 16-Bit LSBs 16-Bit LSBs 25 Temp (°C) +0.5 –0.5 –1.0 +1.0 –1.0 –2.0 0 0 8192 16384 24576 32768 40960 49152 57344 65536 8192 16384 24576 32768 40960 49152 57344 65536 ® 5 ADS7821 BASIC OPERATION CS and R/C are internally OR’d and level triggered. There is not a requirement which input goes LOW first when initiating a conversion. If, however, it is critical that CS or R/C initiates conversion ‘n’, be sure the less critical input is LOW at least 10ns prior to the initiating input. Figure 1 shows a basic circuit to operate the ADS7821 with a full parallel data output. Taking R/C (pin 24) LOW for a minimum of 40ns (5µs max) will initiate a conversion. BUSY (pin 26) will go LOW and stay LOW until the conversion is completed and the output registers are updated. Data will be output in Straight Binary with the MSB on pin 6. BUSY going HIGH can be used to latch the data. All convert commands will be ignored while BUSY is LOW. To reduce the number of control pins, CS can be tied LOW using R/C to control the read and convert modes. However, the output will become active whenever R/C goes HIGH. Refer to the Reading Data section. The ADS7821 will begin tracking the input signal at the end of the conversion. Allowing 10µs between convert commands assures accurate acquisition of a new signal. CS R/C BUSY 1 X X None. Databus is in Hi-Z state. ↓ 0 1 Initiates conversion “n”. Databus remains in Hi-Z state. 0 ↓ 1 Initiates conversion “n”. Databus enters Hi-Z state. 0 1 ↑ Conversion “n” completed. Valid data from conversion “n” on the databus. ↓ 1 1 Enables databus with valid data from conversion “n”. ↓ 1 0 Enables databus with valid data from conversion “n-1”(1). Conversion n in progress. 0 ↑ 0 Enables databus with valid data from conversion “n-1”(1). Conversion “n” in progress. 0 0 ↑ New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C must be HIGH when BUSY goes HIGH. X X 0 New convert commands ignored. Conversion “n” in progress. STARTING A CONVERSION The combination of CS (pin 25) and R/C (pin 24) LOW for a minimum of 40ns immediately puts the sample/hold of the ADS7821 in the hold state and starts conversion ‘n’. BUSY (pin 26) will go LOW and stay LOW until conversion ‘n’ is completed and the internal output register has been updated. All new convert commands during BUSY LOW will be ignored. CS and/or R/C must go HIGH before BUSY goes HIGH or a new conversion will be initiated without sufficient time to acquire a new signal. The ADS7821 will begin tracking the input signal at the end of the conversion. Allowing 10µs between convert commands assures accurate acquisition of a new signal. Refer to Table II for a summary of CS, R/C, and BUSY states and Figures 3 through 5 for timing diagrams. + NOTE: (1) See Figures 3 and 4 for constraints on data valid from conversion “n-1”. Table II. Control Line Functions for “Read” and “Convert”. 1 28 2 27 2.2µF 3 26 4 25 5 24 D15 (MSB) 6 23 D14 7 2.2µF + OPERATION + 0.1µF + +5V 10µF Convert Pulse 22 D0 (LSB) ADS7821 D13 8 21 D1 D12 9 20 D2 D11 10 19 D3 D10 11 18 D4 D9 12 17 D5 D8 13 16 D6 14 15 D7 FIGURE 1. Basic Operation. ® ADS7821 6 40ns min 5µs max READING DATA PARALLEL OUTPUT (During a Conversion) After conversion ‘n’ has been initiated, valid data from conversion ‘n-1’ can be read and will be valid up to 5µs after the start of conversion ‘n’. Do not attempt to read data from 5µs after the start of conversion ‘n’ until BUSY (pin 26) goes HIGH; this may result in reading invalid data. Refer to Table IV and Figures 3 through 5 for timing specifications. The ADS7821 outputs full or byte-reading parallel data in Straight Binary data output format. The parallel output will be active when R/C (pin 24) is HIGH and CS (pin 25) is LOW. Any other combination of CS and R/C will tri-state the parallel output. Valid conversion data can be read in a full parallel, 16-bit word or two 8-bit bytes on pins 6-13 and pins 15-22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle. Refer to Table III for ideal output codes and Figure 2 for bit locations relative to the state of BYTE. Note! For the best possible performance, data should not be read during a conversion. The switching noise of the asynchronous data transfer can cause digital feedthrough degrading the converter’s performance. The number of control lines can be reduced by tying CS LOW while using R/C to initiate conversions and activate the output mode of the converter. See Figure 3. DIGITAL OUTPUT STRAIGHT BINARY DESCRIPTION ANALOG INPUT Full Scale Range 0 to +5V Least Significant Bit (LSB) 76µV BINARY CODE HEX CODE Full Scale 4.999924V 1111 1111 1111 1111 Midscale 2.5V 1000 0000 0000 0000 8000 2.499924V 0111 1111 1111 1111 7FFF 0V 0000 0000 0000 0000 0000 One LSB below Midscale Zero Scale FFFF Table III. Ideal Input Voltages and Output Codes. PARALLEL OUTPUT (After a Conversion) After conversion ‘n’ is completed and the output registers have been updated, BUSY (pin 26) will go HIGH. Valid data from conversion ‘n’ will be available on D15-D0 (pin 6-13 and 15-22). BUSY going HIGH can be used to latch the data. Refer to Table IV and Figures 3 through 5 for timing specifications. SYMBOL DESCRIPTION t1 Convert Pulse Width MIN TYP MAX UNITS 5000 ns t2 Data Valid Delay after Start of Conversion 8 µs t3 BUSY Delay from Start of Conversion 65 ns 8 µs t4 BUSY LOW t5 BUSY Delay after End of Conversion 40 220 ns t6 Aperture Delay 40 t7 Conversion Time 7.6 8 µs 2 µs 83 ns t8 Acquisition Time t9 Bus Relinquish Time 10 35 t10 BUSY Delay after Data Valid 50 200 ns t11 Previous Data Valid after Start of Conversion 5 µs ns µs t7 + t6 Throughput Time t12 R/C to CS Setup Time 10 ns t13 Time Between Conversions 10 µs t14 Bus Access Time and BYTE Delay 10 9 10 83 ns TABLE IV. Conversion Timing. BYTE LOW BYTE HIGH +5V Bit 15 (MSB) 6 Bit 14 7 23 Bit 7 6 22 Bit 0 (LSB) Bit 6 7 ADS7821 23 22 Bit 8 ADS7821 Bit 13 8 21 Bit 1 Bit 5 8 21 Bit 9 Bit 12 9 20 Bit 2 Bit 4 9 20 Bit 10 Bit 11 10 19 Bit 3 Bit 3 10 19 Bit 11 Bit 10 11 18 Bit 4 Bit 2 11 18 Bit 12 Bit 9 12 17 Bit 5 Bit 1 12 17 Bit 13 Bit 8 13 16 Bit 6 Bit 0 (LSB) 13 16 Bit 14 14 15 Bit 7 14 15 Bit 15 (MSB) FIGURE 2. Bit Locations Relative to State of BYTE (pin 23). ® 7 ADS7821 t1 R/C t13 t2 t4 BUSY t3 t6 t5 Convert Acquire MODE Acquire t7 DATA BUS Previous Data Valid Previous Data Valid Hi-Z t9 Convert t8 Data Valid Not Valid Hi-Z t10 t11 FIGURE 3. Conversion Timing with Outputs Enabled after Conversion (CS Tied LOW.) t12 t12 t12 t12 R/C t1 CS t3 t4 BUSY t6 MODE Convert Acquire Acquire t7 Hi-Z State DATA BUS Data Valid t9 t14 FIGURE 4. Using CS to Control Conversion and Read Timing. t12 t12 R/C CS BYTE Pins 6 - 13 Hi-Z High Byte t14 Pins 15 - 22 Hi-Z t14 Low Byte FIGURE 5. Using CS and BYTE to Control Data Bus. ® ADS7821 Low Byte 8 High Byte Hi-Z t9 Hi-Z Hi-Z State Data Valid INPUT RANGE The ADS7821 offers a standard 0V to 5V input range. Figure 6 shows the required circuit connections for the ADS7821 with and without the gain adjustment hardware. Adjustments for offset and gain are described in the calibration section of this data sheet. REF REF (pin 3) is an input for an external reference or the output for the internal 2.5V reference. A 2.2µF capacitor should be connected as close to the REF pin as possible. The capacitor and the output resistance of REF create a low pass filter to bandlimit noise on the reference. Using a smaller value capacitor will introduce more noise to the reference degrading the SNR and SINAD. The REF pin should not be used to directly drive external loads. CALIBRATION The range for the external reference is 2.3V to 2.7V and determines the actual LSB size. Increasing the reference voltage will increase the full scale range and the LSB size of the converter which can improve the SNR. The ADS7821 can be trimmed in hardware or software. There is no external offset adjustment. If offset adjustment is required, an op amp featuring an offset trim pin should be used to drive the ADS7821. The offset should be trimmed before the gain since the offset directly affects the gain. To achieve optimum performance, several iterations may be required. CAP CAP (pin 4) is the output of the internal reference buffer. A 2.2µF capacitor should be placed as close to the CAP pin as possible to provide optimum switching currents for the CDAC throughout the conversion cycle and compensation for the output of the internal buffer. Using a capacitor any smaller than 1µF can cause the output buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2µF will have little affect on improving performance. GAIN ADJUSTMENT To calibrate the gain of the ADS7821, a 576kΩ resistor can be tied between the REF pin and a 50kΩ potentiometer as shown in Figure 6a. The calibration range is ±15mV for the gain. REFERENCE The ADS7821 can operate with its internal 2.5V reference or an external reference. By applying an external reference to pin 3, the internal reference can be bypassed. The reference voltage at REF is buffered internally with the output on CAP (pin 4). a) The output of the buffer is capable of driving up to 2mA of current to a static load. Static loads requiring more than 2mA of current from the CAP pin will begin to degrade the linearity of the ADS7821. Use of an external buffer is recommended for loads requiring more than 2mA. Do not attempt to directly drive any dynamic load with the output voltage on CAP. This will cause performance degradation of the converter. With Hardware Gain Trim 1 0 to +5V 2 2.2µF +5V + 3 b) VIN Without Hardware Gain Trim 1 0 to +5V 2 AGND1 2.2µF REF + 3 VIN AGND1 REF 576kΩ 4 50kΩ Gain 2.2µF 4 CAP + 5 2.2µF 5 AGND2 CAP + AGND2 NOTE: Use 1% metal film resistors. FIGURE 6. Circuit Diagram With and Without External Gain Trim. ® 9 ADS7821 LAYOUT SIGNAL CONDITIONING The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The FET switch on the ADS7821, compared to the FET switches on other CMOS A/D converters, releases 5%-10% of the charge. There is also a resistive front end which attenuates any charge which is released. Any op amp sufficient for the signal in an application should be sufficient to drive the ADS7821. POWER For optimum performance, tie the analog and digital power pins to the same +5V power supply and tie the analog and digital grounds together. As noted in the electrical specifications, the ADS7821 uses 98% of its power for the analog circuitry. The ADS7821 should be considered as an analog component. The +5V power for the A/D should be separate from the +5V used for the system’s digital logic. Connecting VDIG (pin 28) directly to a digital supply can reduce converter performance due to switching noise from the digital logic. For best performance, the +5V supply can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If +12V or +15V supplies are present, a simple +5V regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG and VANA should be tied to the same +5V source. INTERMEDIATE LATCHES The ADS7821 does have tri-state outputs for the parallel port, but intermediate latches should be used if the bus will be active during conversions. If the bus is not active during conversion, the tri-state outputs can be used to isolate the A/D from other peripherals on the same bus. Tri-state outputs can also be used when the A/D is the only peripheral on the data bus. Intermediate latches are beneficial on any monolithic A/D converter. The ADS7821 has an internal LSB size of 38µV. Transients from fast switching signals on the parallel port, even when the A/D is tri-stated, can be coupled through the substrate to the analog circuitry causing degradation of converter performance. GROUNDING Three ground pins are present on the ADS7821. DGND is the digital supply ground. AGND2 is the analog supply ground. AGND1 is the ground which all analog signals internal to the A/D are referenced. AGND1 is more susceptible to current induced voltage drops and must have the path of least resistance back to the power supply. All the ground pins of the A/D should be tied to the analog ground plane, separated from the system’s digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the “system” ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground. ® ADS7821 10