1CY74FCT163646 Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT163646 16-Bit Registered Transceiver SCCS058 - March 1997 - Revised March 2000 Features Functional Description • Low power, pin-compatible replacement for LCX and LPT families • 5V tolerant inputs and outputs • 24 mA balanced drive outputs • Power-off disable outputs permits live insertion • Edge-rate control circuitry for reduced noise • FCT-C speed at 5.4 ns • Latch-up performance exceeds JEDEC standard no. 17 • ESD > 2000V per MIL-STD-883D, Method 3015 • Typical output skew < 250 ps • Industrial temperature range of –40˚C to +85˚C • TSSOP (19.6-mil pitch) or SSOP (25-mil pitch) • Typical Volp (ground bounce) performance exceeds Mil Std 883D • VCC = 2.7V to 3.6V The CY74FCT163646 16-bit transceiver is a three-state, D-type register, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a HIGH logic level. Output Enable (OE) and direction pins (DIR) are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register, or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the Output Enable (OE) is Active LOW. In the isolation mode (Output Enable (OE) HIGH), A data may be stored in the B register and/or B data may be stored in the A register. The CY74FCT163646 has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The inputs and outputs were designed to be capable of being driven by 5.0V buses, allowing them to be used in mixed voltage systems as translators. The outputs are also designed with a power-off disable feature enabling them to be used in applications requiring live insertion. Logic Block Diagrams 2OE 1OE 2DIR 2CLKBA 2SBA 2CLKAB 1DIR 1CLKBA 1SBA 1CLKAB 2SAB 1SAB B REG B REG D D C C 1A1 A REG D 1B1 2A1 A REG D 2B1 C C TO 7 OTHER CHANNELS TO 7 OTHER CHANNELS Copyright © 2000, Texas Instruments Incorporated CY74FCT163646 Pin Configuration SSOP/TSSOP Top View 1DIR 1 56 1OE 1CLKAB 1SAB 2 55 3 54 1CLKBA 1SBA GND 4 53 GND 1A1 5 52 1B1 1A2 VCC 1A3 6 51 1B2 7 50 VCC 8 49 1B3 1A4 9 48 1B4 1A5 10 47 1B5 GND 11 46 GND 1A6 12 45 1B6 1A7 13 44 1B7 1A8 14 43 1B8 2A1 15 42 2B1 2A2 16 41 2B2 2A3 17 40 2B3 GND 18 39 GND 2A4 19 38 2B4 2A5 2A6 20 37 2B5 21 36 2B6 VCC 22 35 VCC 2A7 23 34 2B7 2A8 24 33 2B8 GND 25 32 GND 2SAB 26 31 2SBA 2CLKAB 27 30 2DIR 28 29 2CLKBA 2OE Pin Description Pin Names Description A Data Register A Inputs Data Register B Outputs B Data Register B Inputs Data Register A Outputs CLKAB, CLKBA Clock Pulse Inputs SAB, SBA Output Data Source Select Inputs DIR Direction OE Output Enable (Active LOW) Function Table[1] Data I/O[2] Inputs Function OE DIR CLKAB CLKBA SAB SBA A B H H X X H or L H or L X X X X Input Input Isolation Store A and B Data L L L L X X X H or L X X L H Output Input Real Time B Data to A Bus Stored B Data to A Bus L L H H X H or L X X L H X X Input Output Real Time A Data to Bus Stored A Data to B Bus Notes: 1. 2. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care, = LOW-to-HIGH Transition The data output functions may be enabled or disabled by various signals at the OE or DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. 2 CY74FCT163646 BUS A BUS B DIR L OE L CLKAB X CLKBA X SAB X BUS A SBA L DIR H BUS B OE L CLKAB X Real-Time Transfer Bus B to BusA OE L L H CLKAB CLKBA X X SAB L SBA X Real-Time Transfer BusA to Bus B BUS A DIR H L X CLKBA X SAB X X X BUS B BUS A SBA X X X DIR [3] L H Storage from A and/or B BUS A OE L L CLKAB X H or L CLKBA H or L X SAB X H SBA H X Transfer Stored Data to A and/or B Maximum Ratings[4] DC Output Current (Maximum Sink Current/Pin) ...........................−60 to +120 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Power Dissipation .......................................................... 1.0W Storage Temperature ............................... −55°C to +125°C Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied ............................................ −55°C to +125°C Operating Range Supply Voltage Range ..................................... 0.5V to +4.6V DC Input Voltage .................................................−0.5V to +7.0V Range DC Output Voltage ..............................................−0.5V to +7.0V Industrial Ambient Temperature VCC –40°C to +85°C 2.7V to 3.6V Notes: 3. Cannot transfer data to A-bus and B-bus simultaneously. 4. Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 CY74FCT163646 Electrical Characteristics Over the Operating Range VCC=2.7V to 3.6V Parameter Description VIH Input HIGH Voltage VIL Input LOW Voltage Test Conditions All Inputs Min. Typ.[5] 2.0 [6] Max. Unit 5.5 V 0.8 V VH Input Hysteresis VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −1.2 V IIH Input HIGH Current VCC=Max., VI=5.5V ±1 µA IIL Input LOW Current VCC=Max., VI=GND ±1 µA IOZH High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=5.5V ±1 µA IOZL High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=GND ±1 µA IODL Output LOW Dynamic Current[7] VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V 45 180 mA IODH Output HIGH Dynamic Current[7] VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V –45 –180 mA VOH Output HIGH Voltage VCC=Min., IOH= –0.1 mA VOL 100 Output LOW Voltage −0.7 VCC–0.2 VCC=3.0V, IOH= –8 mA 3.0 VCC=3.0V, IOH= –24 mA 2.0 3.0 0.2 VCC=Min., IOL= 24 mA IOS Short Circuit IOFF Power-Off Disable V 2.4[8] VCC=Min., IOL= 0.1mA Current[7] VCC=Max., VOUT=GND mV –60 V 0.3 0.5 –135 –240 mA ±100 µA VCC=0V, VOUT≤4.5V Capacitance[5] (TA = +25˚C, f = 1.0 MHz) Symbol Description[9] Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 4.5 6.0 pF COUT Output Capacitance VOUT =0V 5.5 8.0 pF Notes: 5. Typical values are at VCC=3.3V, TA=+25˚C ambient. 6. This parameter is specified but not tested. 7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametrics tests. In any sequence of parameter tests, IOS tests should be performed last. 8. VOH=VCC–0.6 V at rated current. 9. This parameter is measured at characterization but not tested. 4 CY74FCT163646 Power Supply Characteristics Parameter Description Typ.[5] Max. Unit VIN<0.2V VIN>VCC−0.2V 0.1 10 µA Test Conditions ICC Quiescent Power Supply Current VCC=Max. ∆ICC Quiescent Power Supply Current VCC=Max. TTL Inputs HIGH VIN=VCC–0.6V[10] 2.0 30 µA ICCD Dynamic Power Supply Current[11] VCC=Max., Outputs Open DIR=OE=GND One-Bit Toggling 50% Duty Cycle VIN=VCC or VIN=GND 50 75 µA/MHz IC Total Power Supply Current[12] VCC=Max.,Outputs Open fo=10 MHz (CLKBA) 50% Duty Cycle DIR=OE=GND One-Bit Toggling, f1=5 MHz, 50% Duty Cycle VIN=VCC or VIN=GND 0.5 0.8 mA VIN=VCC–0.6V or VIN=GND 0.5 0.8 VCC=Max., Outputs Open fo=10 MHz (CLKBA) 50% Duty Cycle DIR=OE=GND Sixteen-Bits Toggling f1=2.5 MHz 50% Duty Cycle VIN=VCC or VIN=GND 2.5 3.8[13] VIN=VCC–0.6V or VIN=GND 2.6 4.1[13] Notes: 10. Per TTL driven input); all other inputs at VCC or GND. 11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 12. IC IC = ICC+∆ICCDHNT+ICCD(f0NC /2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input = Duty Cycle for TTL inputs HIGH DH = Number of TTL inputs at DH NT ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero = Number of clock inputs changing at f1 NC f1 = Input signal frequency = Number of inputs changing at f1 N1 All currents are in milliamps and all frequencies are in megahertz. 13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 5 CY74FCT163646 Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V[14,15] CY74FCT163646C Parameter Description Min. Max. Unit Fig. No.[16] tPLH tPHL Propagation Delay Bus to Bus 1.5 5.4 ns 1, 2 tPZH tPZL Output Enable Time DIR or OE to Bus 1.5 7.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time DIR or OE to Bus 1.5 6.3 ns 1, 7, 8 tPLH tPHL Propagation Delay Clock to Bus 1.5 5.7 ns 1, 5 tPLH tPHL Propagation Delay SBA or SAB to Bus 1.5 6.2 ns 1,5 tSU Set-Up Time HIGH or LOW Bus to Clock 2.0 — ns 4 tH Hold Time HIGH or LOW Bus to Clock 1.5 — ns 4 tW Clock Pulse Width HIGH or LOW 5.0 — ns 6 tSK(O) Output Skew[17] — 0.5 ns — Ordering Information CY74FCT163646 Speed (ns) 5.4 Ordering Code Package Name Package Type CY74FCT163646CPACT Z56 56-Lead (240-Mil) TSSOP CY74FCT163646CPVC/PVCT O56 56-Lead (300-Mil) SSOP Notes: 14. Minimum limits are specified but not tested on Propagation Delays. 15. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%. 16. See “Parameter Measurement Information” in the General Information section. 17. Skew any two outputs of the same package switching in the same direction. This parameter is ensured by design. 6 Operating Range Industrial CY74FCT163646 Package Diagrams 56-Lead Shrunk Small Outline Package O56 56-Lead Thin Shrunk Small Outline Package Z56 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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