Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT652T 8-Bit Registered Transceiver SCCS032 - September 1994 - Revised March 2000 Features Functional Description • Function, pinout, and drive compatible with FCT and F logic • FCT-C speed at 5.4 ns max. (Com’l) FCT-A speed at 6.3 ns max. (Com’l) • Reduced VOH (typically = 3.3V) versions of equivalent FCT functions • Edge-rate control circuitry for significantly improved noise characteristics • Power-off disable feature • Matched rise and fall times • Fully compatible with TTL input and output logic levels • Sink Current 64 mA Source Current 32 mA • Independent register for A and B buses • Multiplexed real-time and stored data transfer • Extended commercial range of −40˚C to +85˚C The FCT652T consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. GAB and GBA control pins are provided to control the transceiver functions. SAB and SBA control pins are provided to select either real-time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A LOW input level selects real-time data and a HIGH selects stored data. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (CPAB or CPBA), regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling GAB and GBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. The outputs are designed with a power-off disable feature to allow for live insertion of boards. Logic Block Diagram Pin Configurations CPBA A6 SBA SAB B REG 1 OF 8 CHANNELS B5 D C GAB SAB CPAB NC VCC CPBA SBA GBA CPAB 11 10 9 8 7 6 5 12 4 13 3 14 2 15 1 28 16 27 17 26 18 19 20 21 22 23 24 25 A7 A8 GND NC B8 B7 B6 B4 B3 NC B2 B1 GBA A5 A4 NC A3 A2 A1 LCC Top View GAB SOIC/QSOP Top View A1 A REG B1 CPAB 1 24 VCC SAB 2 23 CPBA GAB 3 22 SBA A1 4 21 GBA A2 5 20 B1 A3 6 19 B2 A4 7 18 B3 A5 8 17 B4 A6 9 16 B5 A7 10 15 B6 A8 11 14 B7 GND 12 13 B8 D C TO 7 OTHER CHANNELS Copyright © 2000, Texas Instruments Incorporated CY74FCT652T BUS A BUS B GAB L GBA L CPAB X CPBA X SAB X BUS A BUS B GAB H SBA L GBA H Real-Time Transfer Bus B to Bus A BUS B GBA H X H CPAB CPBA X SAB X X X X CPBA X SAB L SBA X Real-Time Transfer Bus A to Bus B BUS A GAB X L L CPAB X BUS A BUS B GAB H SBA X X X GBA L CPAB H or L CPBA H or L SAB H SBA H Transferred Stored Data to A and/or B Store Data from A and/or B Function Table[1] Inputs Data I/O GAB GBA CPAB CPBA SAB SBA A1 thru A8 B1 thru B8 L L H H H or L H or L X X X X Input Input Operation or Function X H H H H or L X X[1] X X Input Input Unspecified[2] Output Store A, Hold B Store A in both registers L L X L H or L X X X X[1] Unspecified[2] Output Input Input Hold A, Store B Store B in both registers L L L L X X X H or L X X L H Output Input Real-Time B Data to A Bus Stored B Data to A Bus H H H H X H or L X X L H X X Input Output Real-Time A Data to B Bus Stored A Data to B Bus H L H or L H or L H H Output Output Stored A Data to B Bus and Stored B Data to A Bus Isolation Store A and B Data Notes: 1. Select control=L: clocks can occur simultaneously. Select control=H: clocks must be staggered in order to load both registers. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. = LOW-to-HIGH Transition. 2. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. 2 CY74FCT652T Maximum Ratings[3, 4] DC Output Current (Maximum Sink Current/Pin) ...... 120 mA Power Dissipation .......................................................... 0.5W (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................–65°C to +150°C Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied .............................................–65°C to +135°C Operating Range Supply Voltage to Ground Potential ............... –0.5V to +7.0V Range DC Input Voltage............................................ –0.5V to +7.0V Commercial DC Output Voltage ......................................... –0.5V to +7.0V Range T, AT, CT Ambient Temperature VCC –40°C to +85°C 5V ± 5% Electrical Characteristics Over the Operating Range Parameter VOH Description Test Conditions Output HIGH Voltage Min. VCC=Min., IOH=–32 mA 2.0 VCC=Min., IOH=–15 mA 2.4 VCC=Min., IOL=64 mA Typ.[5] Max. Unit V 3.3 0.3 V VOL Output LOW Voltage 0.55 V VIH Input HIGH Voltage VIL Input LOW Voltage VH Hysteresis[6] All inputs 0.2 VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V II Input HIGH Current VCC=Max., VIN=VCC 5 µA IIH Input HIGH Current[6] VCC=Max., VIN=2.7V ±1 µA IIL Input LOW Current[6] VCC=Max., VIN=0.5V ±1 µA IOZH Off State HIGH-Level Output Current VCC=Max., VOUT=2.7V 10 µA IOZL Off State LOW-Level Output Current VCC=Max., VOUT=0.5V –10 µA IOS Output Short Circuit Current[7] VCC=Max., VOUT=0.0V –225 mA IOFF Power-Off Disable VCC=0V, VOUT=4.5V ±1 µA 2.0 V 0.8 –60 –120 V V Capacitance[6] Parameter Description Typ.[5] Max. Unit CIN Input Capacitance 5 10 pF COUT Output Capacitance 9 12 pF Notes: 3. Unless otherwise noted, these limits are over the operating free-air temperature range. 4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 5. Typical values are at VCC=5.0V, TA=+25˚C ambient. 6. This parameter is specified but not tested. 7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 3 CY74FCT652T Power Supply Characteristics Parameter Description Test Conditions Typ.[5] Max. Unit ICC Quiescent Power Supply Current VCC=Max., VIN≤0.2V, VIN≥VCC–0.2V 0.1 0.2 mA ∆ICC Quiescent Power Supply Current (TTL inputs HIGH) VCC=Max., VIN=3.4V, f1=0, Outputs Open[8] 0.5 2.0 mA ICCD Dynamic Power Supply Current[9] VCC=Max., One Input Toggling, 50% Duty Cycle, Outputs Open, GAB=GND, GBA=GND, VIN≤0.2V or VIN≥VCC–0.2V 0.06 0.12 mA/MHz IC Total Power Supply Current[10] VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=5 MHz, GAB=GND, GBA=GND, SAB=CPAB=GND SBA=VCC, VIN≤0.2V or VIN≥VCC–0.2V 0.7 1.4 mA VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=5 MHz, GAB=GND, GBA=GND, SAB=CPAB=GND SBA=VCC, VIN=3.4V or VIN=GND 1.2 3.4 mA VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, Eight Bits Toggling at f1=5 MHz, GAB=GBA=GND, SAB=CPAB=GND SBA=VCC, VIN≤0.2V or VIN≥VCC–0.2V 2.8 5.6[11] mA VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, Eight Bits Toggling at f1=5 MHz, GAB=GBA=GND, SAB=CPAB=GND SBA=VCC, VIN=3.4V or VIN=GND 5.1 14.6[11] mA Notes: 8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 10. IC IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) = Duty Cycle for TTL inputs HIGH DH = Number of TTL inputs at DH NT ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 = Number of inputs changing at f1 N1 All currents are in milliamps and all frequencies are in megahertz. 11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 4 CY74FCT652T Switching Characteristics Over the Operating Range[12] Parameter Description FCT652T FCT652AT FCT652CT Commercial Commercial Commercial Min. Max. Min. Max. Min. Max. Unit Fig. No.[13] tPLH tPHL Propagation Delay Bus to Bus 1.5 9.0 1.5 6.3 1.5 5.4 ns 1, 3 tPZH tPZL Output Enable Time Enable to Bus 1.5 14.0 1.5 9.8 1.5 7.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time Enable to Bus 1.5 9.0 1.5 6.3 1.5 6.3 ns 1, 7, 8 tPLH tPHL Propagation Delay Clock to Bus 1.5 9.0 1.5 6.3 1.5 5.7 ns 1, 5 tPLH tPHL Propagation Delay SBA or SAB to A or B 1.5 11.0 1.5 7.7 1.5 6.2 ns 1, 5 tS Set-Up Time HIGH or LOW Bus to Clock 4.0 2.0 2.0 ns 4 tH Hold Time HIGH or LOW Bus to Clock 2.0 1.5 1.5 ns 4 tW Clock Pulse Width,[14] HIGH or LOW 6.0 5.0 5.0 ns 5 Ordering Information Speed (ns) 5.4 6.3 9.0 Ordering Code Package Name Package Type CY74FCT652CTQCT Q13 24-Lead (150-Mil) QSOP CY74FCT652CTSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC CY74FCT652ATQCT Q13 24-Lead (150-Mil) QSOP CY74FCT652ATSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC CY74FCT652TQCT Q13 24-Lead (150-Mil) QSOP Notes: 12. Minimum limits are specified but not tested on Propagation Delays. 13. See “Parameter Measurement Information” in the General Information section. 14. With one data channel toggling, tW(L)=tW(H)=4.0 ns and tr=tf=1.0 ns. Document #: 38-00268-B 5 Operating Range Commercial Commercial Commercial CY74FCT652T Package Diagrams 24-Lead Quarter Size Outline Q13 24-Lead (300-Mil) Molded SOIC S13 6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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