TI UCC28950PW

UCC28950
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SLUSA16A – MARCH 2010 – REVISED JULY 2010
Green Phase-Shifted Full-Bridge Controller With Synchronous Rectification
Check for Samples: UCC28950
FEATURES
APPLICATIONS
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1
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Enhanced Wide Range Resonant Zero Voltage
Switching (ZVS) Capability
Direct Synchronous Rectifier (SR) Control
Light-Load Efficiency Management Including
– Burst Mode Operation
– Discontinuous Conduction Mode (DCM),
Dynamic SR On/Off Control with
Programmable Threshold
– Programmable Adaptive Delay
Average or Peak Current Mode Control with
Programmable Slope Compensation and
Voltage Mode Control
Closed Loop Soft Start and Enable Function
Programmable Switching Frequency up to 1
MHz with Bi-Directional Synchronization
(+/-3%) Cycle-by-Cycle Current Limit
Protection with Hiccup Mode Support
150-µA Start-Up Current
VDD Under Voltage Lockout
Wide Temperature Range -40°C to 125°C
Phase-Shifted Full-Bridge Converters
Server, Telecom Power Supplies
Industrial Power Systems
High-Density Power Architectures
Solar Inverters, and Electric Vehicles
DESCRIPTION
The UCC28950 enhanced phase-shifted controller
builds upon Texas Instrument’s industry standard
UCCx895 phase-shifted controller family with
enhancements that offer best in class efficiency in
today’s high performance power systems. The
UCC28950 implements advanced control of the
full-bridge along with active control of the
synchronous rectifier output stage.
The primary-side signals allow programmable delays
to ensure ZVS operation over wide-load current and
input voltage range, while the load current naturally
tunes the secondary-side synchronous rectifiers
switching delays, maximizing overall system
efficiency.
UCC28950 Typical Application
+
CT
VS
CREF
-
R1
UCC28950
R2
1
VREF
GND 24
2
EA+
VDD 23
3
EA-
OUTA 22
CVDD
R3
VSENSE
C1
R5
C2
R6 R4 C3
ENABLE
4
COMP
OUTB 21
B
CSS
5
SS/EN
OUTC 20
C
RAB
6
DELAB
OUTD 19
D
RCD
7
DELCD
OUTE 18
E
REF
8
DELEF
OUTF 17
F
9
TMIN
SYNC 16
SYNC
RA(hi)
RTMIN
RT
VREF
10 RT
RSUM
11 RSUM
R7
VREF
12 DCM
VDD
A
VDD
QA
QC
QB
QD
VDD
B
C
VDD
D
VOUT
+
CS 15
ADEL 14
RDCM(hi)
Voltage Current
Sense
VDD
A
RAEF(hi)
E
UCC27324
QE
UCC27324
QF
F
ADELEF 13
-
RA
RCS
RDCM
RAEF
VSENSE
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
UCC28950
SLUSA16A – MARCH 2010 – REVISED JULY 2010
www.ti.com
DESCRIPTION (CONT.)
The UCC28950 also offers multiple light-load management features including burst mode and dynamic SR on/off
control when transitioning in and out of Discontinuous Current Mode (DCM) operation, ensuring ZVS operation is
extended down to much lighter loads.
In addition, the UCC28950 includes support for peak current along with voltage mode control, programmable
switching frequency up to 1 MHz and a wide set of protection features including cycle-by-cycle current limit,
UVLO and thermal shutdown. A 90-degree phase-shifted interleaved synchronized operation can be easily
arranged between two converters.
The UCC28950 is available in TSSOP-24 package.
ORDERING INFORMATION
TEMPERATURE RANGE, TA =
TJ
PACKAGE
-40°C to 125°C
Plastic 24-pin TSSOP (PW)
TAPE AND REEL QTY.
PART NUMBER
250
UCC28950PW
2000
UCC28950PWR
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2)
PARAMETER
Input supply voltage range, VDD
VALUE
(3)
-0.4 to 20.0
OUTA, OUTB, OUTC, OUTD, OUTE, OUTF
-0.4 to VDD + 0.4
Inputs voltages on DELAB, DELCD, DELEF, SS/EN, DCM, TMIN, RT, SYNC, RSUM, EA+, EA-,
COMP, CS, ADEL, ADELEF
Output voltage on VREF
-0.4 to VREF +
0.4
2k
ESD rating, CDM
500
Continuous total power dissipation
See dissipation rating table
Operating virtual junction temperature range, TJ
-40 to 150
Operating ambient temperature range, TA
-40 to 125
Storage temperature, Tstg
-65 to 150
Lead temperature (soldering, 10 sec.)
(2)
(3)
V
-0.4 to 5.6
ESD rating, HBM
(1)
UNIT
°C
300
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Packaging Section of the datasheet for thermal limitations and considerations of packages.
DISSIPATION RATINGS (1)
PACKAGE
PW
(1)
2
RqJC
(°C/W)
RqJA
(°C/W)
18.5
89.3
DERATING
FACTOR
POWER RATING
ABOVE TA =
25°C
TA < 25°C
TA = 70°C
TA = 85°C
11.2 mW/ °C
1.12 W
0.615 W
0.448 W
These thermal data are taken at standard JEDEC test conditions and are useful for the thermal performance comparison of different
packages. The cooling condition and thermal impedance RqJA of practical design is specific.
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SLUSA16A – MARCH 2010 – REVISED JULY 2010
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
Supply voltage range, VDD
8
MAX
17
V
-40
125
°C
Converter switching frequency setting range, FSW(nom)
50
1000
kHz
Programmable delay range between OUTA, OUTB and OUTC, OUTD set by
resistors DELAB and DELCD and parameter KA (1)
30
1000
Programmable delay range between OUTA, OUTF and OUTB, OUTE set by
resistor DELEF, and parameter KEF (1)
30
1400
Programmable DCM range as percentage of voltage at CS (1)
5%
30%
Programmable TMIN range
100
800
Operating junction temperature range
(1)
12
UNIT
ns
ns
Verified during characterization only.
ELECTRICAL CHARACTERISTICS (1)
VDD = 12 V, TA = TJ = -40°C to 125°C, CVDD = 1 µF, CREF = 1 µF, RAB = 22.6 kΩ, RCD = 22.6 kΩ , REF = 13.3 kΩ, RSUM = 124
kΩ, RMIN = 88.7 kΩ, RT = 59 kΩ connected between RT pin and 5-V voltage supply to set FSW = 100 kHz (FOSC = 200 kHz)
(unless otherwise noted). All component designations are from the Typical Application Diagram.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Under Voltage Lockout (UVLO)
UVLO_R
Start threshold
TH
6.75
7.3
7.9
UVLO_F
TH
6.15
6.7
7.2
0.53
0.6
0.75
150
270
µA
5
10
mA
5
5.075
Minimum operating voltage
after start
UVLO_H
Hysteresis
YST
V
Supply Currents
IDD(off)
Startup current
IDD
Operating supply current
VDD is 5.2 V
VREF Output Voltage
VREF
VREF total output range
0 ≤ IR ≤ 20 mA; VDD = from 8 V to 17 V
ISCC
Short circuit current
VREF = 0 V
4.925
-53
V
-23
mA
KHz
Switching Frequency (½ of internal oscillator frequency FOSC)
FSW(nom)
Total range
DMAX
Maximum duty cycle
92
100
108
95%
97%
Synchronization
PHSYNC
Total range
RT = 59 kΩ between RT and GND; Input pulses
200 kHz, D = 0.5 at SYNC
85
90
95
°PH
FSYNC
Total range
RT = 59 kΩ between RT and 5 V; -40 °C ≤ TJ ≤
125°C
180
200
220
kHz
TPW
Pulse width
2.2
2.5
2.8
µs
(1)
Typical values for TA = 25°C
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ELECTRICAL CHARACTERISTICS(1) (continued)
VDD = 12 V, TA = TJ = -40°C to 125°C, CVDD = 1 µF, CREF = 1 µF, RAB = 22.6 kΩ, RCD = 22.6 kΩ , REF = 13.3 kΩ, RSUM = 124
kΩ, RMIN = 88.7 kΩ, RT = 59 kΩ connected between RT pin and 5-V voltage supply to set FSW = 100 kHz (FOSC = 200 kHz)
(unless otherwise noted). All component designations are from the Typical Application Diagram.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Error Amplifier
VICM range ensures parameters, the functionality
ensured for 3.6 V < VICM < VREF + 0.4 V, and -0.4
V < VICM < 0.5 V
VICM
Common mode input voltage
range
VIO
Offset voltage
IBIAS
Input bias current
EAHIGH
High-level output voltage
(EA+) - (EA-) = 500 mV, IEAOUT = -0.5 mA
EALOW
Low-level output voltage
(EA+) - (EA-) = -500 mV, IEAOUT = 0.5 mA
ISOURCE
Error amplifier source current
ISINK
Error amplifier sink current
IVOL
Open-loop dc gain
GBW
Unity gain bandwidth (2)
0.5
3.6
-7
7
mV
-1
1
µA
3.9
4.25
0.25
0.35
-8
-3.75
-0.5
2.7
4.6
5.75
100
V
V
mA
dB
3
MHz
Cycle-by-Cycle Current Limit
VCS_LIM
CS pin cycle-by-cycle
threshold
TCS
Propagation delay from CS to
OUTC and OUTD outputs
1.94
Input pulse between CS and GND from zero to 2.5
V
2
2.06
100
V
ns
Internal Hiccup Mode Settings
IDS
Discharge current to set
cycle-by-cycle current limit
duration
VHCC
Hiccup OFF Time threshold
IHCC
Discharge current to set
Hiccup Mode OFF Time
CS = 2.5 V, VSS = 4 V
15
20
25
µA
3.2
3.6
4.2
V
1.90
2.55
3.2
µA
20
25
30
µA
0.25
0.50
0.70
3.3
3.7
4.3
4.20
4.65
4.95
Soft Start/Enable
ISS
Charge current
VSS_STD
Shutdown/restart/reset
threshold
VSS_PU
Pull up threshold
VSS_CL
Clamp voltage
(2)
4
VSS = 0 V
V
Verified during characterization only.
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ELECTRICAL CHARACTERISTICS(1) (continued)
VDD = 12 V, TA = TJ = -40°C to 125°C, CVDD = 1 µF, CREF = 1 µF, RAB = 22.6 kΩ, RCD = 22.6 kΩ , REF = 13.3 kΩ, RSUM = 124
kΩ, RMIN = 88.7 kΩ, RT = 59 kΩ connected between RT pin and 5-V voltage supply to set FSW = 100 kHz (FOSC = 200 kHz)
(unless otherwise noted). All component designations are from the Typical Application Diagram.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Programmable Delay Time Set Accuracy and Range (3) (4) (5) (6) (7)
TABSET1
Short delay time set accuracy
between OUTA and OUTB
CS = ADEL = ADELEF = 1.8 V
32
45
56
TABSET2
Long delay time set accuracy
between OUTA and OUTB
CS = ADEL = ADELEF = 0.2 V
216
270
325
TCDSET1
Short delay time set accuracy
between OUTC and OUTD
CS = ADEL = ADELEF = 1.8 V
32
45
56
TCDSET2
Long delay time set accuracy
between OUTC and OUTD
CS = ADEL = ADELEF = 0.2 V
216
270
325
TAFSET1
Short delay time set accuracy
between falling OUTA, OUTF
CS = ADEL = ADELEF = 0.2 V
22
35
48
TAFSET2
Long delay time set accuracy
between falling OUTA, OUTF
CS = ADEL = ADELEF = 1.8 V
190
240
290
TBESET1
Short delay time set accuracy
between falling OUTB, OUTE
CS = ADEL = ADELEF = 0.2 V
22
35
48
TBESET2
Long delay time set accuracy
between falling OUTB, OUTE
CS = ADEL = ADELEF = 1.8 V
190
240
290
ΔTADBC
Pulse matching between
OUTA rise, OUTD fall and
OUTB rise, OUTC fall
CS = ADEL = ADELEF = 1.8 V, COMP = 2 V
-50
0
50
ΔTABBA
Half cycle matching between
OUTA rise, OUTB rise and
OUTB rise, OUTA rise
CS = ADEL = ADELEF = 1.8 V, COMP = 2 V
-50
0
50
ΔTEEFF
Pulse matching between
OUTE fall, OUTE rise and
OUTF fall, OUTF rise
CS = ADEL = ADELEF = 0.2 V, COMP = 2 V
-60
0
60
ΔTEFFE
Pulse matching between
OUTE fall, OUTF rise and
OUTF fall, OUTE rise
CS = ADEL = ADELEF = 0.2 V, COMP = 2 V
-60
0
60
(3)
(4)
(5)
(6)
(7)
ns
See Figure 3 for timing diagram and TABSET1, TABSET2, TCDSET1, TCDSET2 definitions.
See Figure 6 for timing diagram and TAFSET1, TAFSET2, TBESET1, TBESET2 definitions.
Pair of outputs OUTC, OUTE and OUTD, OUTF always going high simultaneously.
Outputs A or B are never allowed to go high if both outputs OUTE and OUTF are high.
All delay settings are measured relatively 50% of pulse amplitude.
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ELECTRICAL CHARACTERISTICS(1) (continued)
VDD = 12 V, TA = TJ = -40°C to 125°C, CVDD = 1 µF, CREF = 1 µF, RAB = 22.6 kΩ, RCD = 22.6 kΩ , REF = 13.3 kΩ, RSUM = 124
kΩ, RMIN = 88.7 kΩ, RT = 59 kΩ connected between RT pin and 5-V voltage supply to set FSW = 100 kHz (FOSC = 200 kHz)
(unless otherwise noted). All component designations are from the Typical Application Diagram.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Light Load Efficiency Circuit
DCM threshold, T = 25°C
VDCM = 0.4 V, Sweep CS confirm there are OUTE
and OUTF pulses
0.37
0.39
0.41
DCM threshold, T = 0°C to
85°C (8)
VDCM = 0.4 V, Sweep CS, confirm there are OUTE
and OUTF pulses
0.364
0.390
0.416
DCM threshold, T= -40°C to
125°C (8)
VDCM = 0.4 V, Sweep CS, confirm there are OUTE
and OUTF pulses
0.35
0.39
0.43
IDCM,SRC
DCM Sourcing Current
CS < DCM threshold
TMIN
Total range
RTMIN = 88.7 kΩ
VDCM
V
14
20
26
µA
425
525
625
ns
OUTPUTS OUTA, OUTB, OUTC, OUTD, OUTE, OUTF
ISINK/SRC
Sink/Source peak current (8)
TR
Rise time
CLOAD = 100 pF
9
25
TF
Fall time
CLOAD = 100 pF
7
25
RSRC
Output source resistance
IOUT = 20 mA
10
20
35
RSINK
Output sink resistance
IOUT = 20 mA
5
10
30
0.2
A
ns
Ω
THERMAL SHUTDOWN
Rising threshold (8)
160
Falling threshold (8)
140
Hysteresis
(8)
6
°C
20
Verified during characterization only.
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SLUSA16A – MARCH 2010 – REVISED JULY 2010
DEVICE INFORMATION
Plastic 24-pin TSSOP (PW)
UCC28950
1
VREF
GND 24
2
EA+
VDD 23
3
EA-
OUTA 22
4
COMP
OUTB 21
5
SS/EN
OUTC 20
6
DELAB
OUTD 19
7
DELCD
OUTE 18
8
DELEF
OUTF 17
9
TMIN
SYNC 16
10 RT
CS 15
11 RSUM
12 DCM
ADEL 14
ADELEF 13
TERMINAL FUNCTIONS
TERMINAL
I/O
FUNCTION
NUMBER
NAME
1
VREF
O
5-V, ±1.5%, 20-mA reference voltage output.
2
EA+
I
Error amplifier non-inverting input.
3
EA-
I
Error amplifier inverting input.
4
COMP
I/O
5
SS/EN
I
Soft-start programming, device enable and hiccup mode protection circuit.
6
DELAB
I
Dead-time delay programming between OUTA and OUTB.
7
DELCD
I
Dead-time delay programming between OUTC and OUTD.
8
DELEF
I
Delay-time programming between OUTA to OUTF, and OUTB to OUTE.
9
TMIN
I
Minimum duty cycle programming in burst mode.
10
RT
I
Oscillator frequency set. Master or slave mode setting.
11
RSUM
I
Slope compensation programming. Voltage mode or peak current mode setting.
12
DCM
I
DCM threshold setting.
13
ADELEF
I
Delay-time programming between primary side and secondary side switches, TAFSET
and TBESET.
14
ADEL
I
Dead-time programming for the primary switches over CS voltage range, TABSET and
TCDSET.
Current sense for cycle-by-cycle over-current protection and adaptive delay functions.
Error amplifier output and input to the PWM comparator.
15
CS
I
16
SYNC
I/O
Synchronization out from Master controller to input of slave controller.
17
OUTF
O
0.2-A sink/source synchronous switching output.
18
OUTE
O
0.2-A sink/source synchronous switching output.
19
OUTD
O
0.2-A sink/source primary switching output.
20
OUTC
O
0.2-A sink/source primary switching output.
21
OUTB
O
0.2-A sink/source primary switching output.
22
OUTA
O
0.2-A sink/source primary switching output.
23
VDD
I
Bias supply input.
24
GND
Ground. All signals are referenced to this node.
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Functional Block Diagram
ADEL
14
VDD
UVLO
COMP
VDD
Thermal
Shutdown
VDD 23
EN
+
+ 7.3 V Rise
- 6.7 V Fall
VREF
1
COMP
4
EA-
3
EA+
2
22 OUTA
Reference
Generator
Programmable
Delay AB
VDD
ON/OFF
5V LDO
DELAB
21 OUTB
20 OUTC
PWM
COMP
+
+
+
Programmable
Delay CD
Logic Block
Lower "+" Input
is Dominant
6
CLK
7
DELCD
19 OUTD
Oscillator
RT 10
RAMP 2.8 V
0.8 V
13 ADELEF
Ramp
Summing
RSUM 11
18 OUTE
+
CS
Cycle-by-Cycle
ILIM
CS 15
Synchronization
Block
+
-
Programmable
Delay EF
8
DELEF
CS
Light-Load
Efficiency Block
2V
Soft Stat and Enable
with 0.55 V Threshold
16
24
12
9
5
SYNC
GND
DCM
TMIN
SS/EN
17 OUTF
Typical Application Diagram
+
CT
VS
CREF
-
R1
UCC28950
R2
1
VREF
GND 24
2
EA+
VDD 23
3
EA-
OUTA 22
CVDD
R3
VSENSE
C1
R5
C2
R6 R4 C3
ENABLE
RT
4
COMP
OUTB 21
B
CSS
5
SS/EN
OUTC 20
C
RAB
6
DELAB
OUTD 19
D
RCD
7
DELCD
OUTE 18
E
REF
8
DELEF
OUTF 17
F
RTMIN
9
TMIN
SYNC 16
SYNC
RA(hi)
VREF
10 RT
RSUM
11 RSUM
R7
VREF
VDD
A
VDD
QA
QC
QB
QD
VDD
B
C
VDD
D
VOUT
+
CS 15
ADEL 14
RDCM(hi)
Voltage Current
Sense
VDD
A
12 DCM
RAEF(hi)
E
UCC27324
QE
UCC27324
QF
F
ADELEF 13
-
RA
RCS
RDCM
RAEF
VSENSE
8
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Startup Timing Diagram
2 VP-P
F
E
D
C
B
A
TMIN
COMP
RAMP
PWM
Add 0.85 V offset to RAMP
No PWM pulses shorter than TMIN
except during cycle-by-cycle current limit
PWM
TMIN
SS > 0.5 V, then release COMP, DCM, CS , Outputs A,B,C,D,E and F
CLK
TMIN
4.8-V rise, 4.6-V fall
VREF
VREF_GOOD
VDD 7.3-V rise, 6.7-V fall
VDD_GOOD
Burst Mode at the beginning of
start up until PWM> TMIN pulses
No output delay shown, COMP-to-RAMP offset not included.
Figure 1. UCC28950 Timing Diagram
NOTE
There is no pulse on OUTE during burst mode at startup. Two falling edge PWM pulses
are required before enabling the synchronous rectifier outputs.
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Steady State/Shutdown Timing Diagram
No output delay shown, COMP-to-RAMP offset not included.
VDD failed and VDD_GOOD goes low,
Everything is shutdown
7.3V rise, 6.7V fall
VDD
VDD_GOOD
4.8V rise, 4.6V fall
VREF
VREF_GOOD
TMIN
CLK
TMIN
Add 0.85V offset to RAMP
COMP
2Vp-p
RAMP
PWM
No PWM pulses shorter than TMIN except
during cycle-by-cycle current limit
A
B
C
D
E
F
Figure 2. UCC28950 Timing Diagram
10
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DETAILED PIN DESCRIPTION AND PARAMETER SETTINGS
Start-Up Protection Logic
Before the UCC28950 controller will start up, the following conditions must be met:
• VDD voltage exceeds rising UVLO threshold 7.3 V typical.
• The 5-V reference voltage is available.
• Junction temperature is below the thermal shutdown threshold of 140°C.
• The voltage on the soft-start capacitor is not below 0.55 V typical.
If all those conditions are met, an internal enable signal EN is generated that initiates the soft start process. The
duty cycle during the soft start is defined by the voltage at the SS pin, and cannot be lower than the duty cycle
set by TMIN, or by cycle-by-cycle current limit circuit depending on load conditions.
Voltage Reference (VREF)
The accurate (±1.5%) 5-V reference voltage regulator with the short circuit protection circuit supplies internal
circuitry and provides up to 20-mA external output current for setting DC/DC converter parameters. Place low
ESR and ESL, preferably ceramic decoupling capacitor CREF in 1 µF to 2.2 µF range from this pin to GND as
close to the related pins as possible for best performance. The only condition where the reference regulator is
shut down internally is during under voltage lockout.
Error Amplifier (EA+, EA-, COMP)
The error amplifier has two uncommitted inputs, EA+ and EA-, with a 3-MHz unity bandwidth, which allows
flexibility in closing the feedback loop. The EA+ is a non-inverting input, the EA- is an inverting input and the
COMP is the output of the error amplifier. The input voltage common mode range, where the parameters of error
amplifier are guaranteed, is from 0.5 V to 3.6 V. The output of the error amplifier is connected internally to the
non-inverting input of the PWM comparator. The range of the error amplifier output of 0.25 V to 4.25 V far
exceeds the PWM comparator input ramp-signal range, which is from 0.8 V to 2.8 V. The soft-start signal serves
as an additional non-inverting input of the error amplifier. The lower of the two non-inverting inputs of the error
amplifier is the dominant input and sets the duty cycle where the output signal of the error amplifier is compared
with the internal ramp at the inputs of the PWM comparator.
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Soft Start and Enable (SS/EN)
The soft-start pin SS/EN is a multi-function pin used for the following operations:
• Closed loop soft start with the gradual duty cycle increase from the minimum set by TMIN up to the steady
state duty cycle required by the regulated output voltage.
• Setting hiccup mode conditions during cycle-by-cycle over current limit.
• On/off control for the converter.
During soft start, one of the voltages at the SS/EN or EA+ pins, whichever is lower (SS/EN - 0.55 V) or EA+
voltage (see Block Diagram), sets the reference voltage for a closed feedback loop. Both SS/EN and EA+ signals
are non-inverting inputs of the error amplifier with the COMP pin being its output. Thus the soft start always goes
under the closed feedback loop and the voltage at COMP pin sets the duty cycle. The duty cycle defined by
COMP voltage can not be shorter than TMIN pulse set by the user. However, if the shortest duty cycle is set by
the cycle-by-cycle current limit circuit, then it becomes dominant over the duty cycle defined by COMP voltage or
by TMIN block.
The soft-start duration is defined by an external capacitor CSS, connected between SS/EN pin and ground, and
the internal charge current that has typical value of 25 µA. Pulling the soft-start pin externally below 0.55 V shuts
down the controller. The release of the soft-start pin enables the controller to start, and if there is no current limit
condition, the duty cycle applied to the output inductor gradually increases until it reaches the steady state duty
cycle defined by the regulated output voltage of the converter. This happens when the voltage at the SS/EN pin
reaches and then exceeds the voltage at EA+ pin defined as VNI by 0.55 V. Thus for the given soft-start time
TSS, the CSS value can be defined by Equation 1 or Equation 2:
CSS(master ) =
CSS(slave) =
TSS ´ 25 mA
(VNI + 0.55 )
(1)
TSS
20.6
æ
ö
825K ´ Ln ç
÷
è 20.6 - VNI - 0.55 ø
(2)
For example, in Equation 1, if the soft-start time TSS is selected to be 10 ms, and the VNI is 2.5 V, then the
soft-start capacitor CSS is equal to 82-nF.
NOTE
If the converter is configured in Slave Mode, make sure you place an 825-kΩ resistor from
SS pin to ground.
Light-Load Power Saving Mode
The UCD28950 offers four different light-load management techniques for improving the efficiency of a power
converter over a wide load current range.
1. Adaptive Delay,
(a) ADEL, which sets and optimizes the dead-time control for the primary switches over wide load current
range.
(b) ADELEF, which sets and optimizes the delay-time control between the primary side switches and the
secondary side switches.
2. TMIN, sets the minimum duty cycle as long as the part is not in current limit mode.
3. Dynamic synchronous rectifier on/off control in DCM Mode, For increased efficiency at light loads. The DCM
Mode starts when the voltage at CS pin is lower than the threshold set by the user. In DCM Mode, the
synchronous output drive signals OUTE and OUTF are brought down low.
4. Burst Mode, for maximum efficiency at very light loads or no load. Burst Mode has an even number of PWM
TMIN pulses followed by off time. Transition to the Burst Mode is defined by the TMIN duration set by the
user.
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Adaptive Delay, (Delay between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
The resistor RAB from the DELAB pin, DELAB to GND, along with the resistor divider RAHI from CS pin to ADEL
pin and RA from ADEL pin to GND sets the delay TABSET between one of outputs OUTA or OUTB going low and
another output going high Figure 3.
OUTA
(OUTC)
TABSET2
TABSET2
TCDSET2
TCDSET2
TABSET1
TABSET1
TCDSET1
TCDSET1
OUTB
(OUTD)
Figure 3. Delay definitions between OUTA and OUTB, OUTC and OUTD
This delay gradually increases as a function of the CS signal from TABSET1, which is measured at VCS = 1.8 V, to
TABSET2, which is measured at the VCS = 0.2 V. This approach ensures there will be no shoot-through current
during the high-side and low-side MOSFET switching and optimizes the delay for ZVS condition over a wide load
current range. Depending on the resistor divider RAHI and RA, the proportional ratio between longest and shortest
delay is set. The max ratio is achieved by tying the CS and ADEL pins together. If ADEL is connected to GND,
then the delay is fixed, defined only by the resistor RAB from DELAB to GND. The delay TCDSET1 and TCDSET2
settings and their behaviour for outputs OUTC and OUTD are very similar to the one described for OUTA and
OUTB. The difference is that resistor RCD connected between DELCD pin and GND sets the delay TCDSET.
Delays for outputs OUTC and OUTD share with the outputs OUTA and OUTB the same CS voltage dependence
pin ADEL.
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The delay time TABSET is defined by the following Equation 3.
æ
ö
5 ´ R AB
TABSET = ç
÷ ns + 5ns
è 0.15 V + CS ´ K A ´ 1.46 ø
(3)
The same equation is used to define the delay time TCDSET in another leg except RAB is replaced by RCD.
æ
ö
5 ´ RCD
TCDSET = ç
÷ ns + 5ns
è 0.15 V + CS ´ K A ´ 1.46 ø
(4)
In these equations RAB and RCD are in kΩ and CS, the voltage at pin CS, is in volts and KA is a numerical
coefficient in the range from 0 to 1. The delay time TABSET and TCDSET are in ns. These equations are empirical
and they are approximated from measured data. Thus, there is no unit agreement in the equations. As an
example, assume RAB = 15 kΩ, CS = 1 V and KA = 0.5. Then the TABSET is going to be 90.25 ns. In both
Equation 3 and Equation 4, KA is the same and is defined as:
KA =
RA
R A + R AHI
(5)
KA sets how the delay is sensitive to CS voltage variation. If KA = 0 (ADEL shorted to GND), the delay is fixed. If
KA = 1 (ADEL is tied to CS), the delay is maximum at CS = 0.2 V and gradually decreases when CS goes up to
1.8 V. The ratio between the maximum and minimum delay can be up to 6:1.
It is recommended to start by setting KA = 0 and set TABSET and TCDSET relatively large using equations or plots in
the data sheet to avoid hard switching or even shoot through current. The delay between outputs A, B and C, D
set by resistors RAB and RCS accordingly. Program the optimal delays at light load first. Then by changing KA set
the optimal delay for the outputs A, B at maximum current. KA for outputs C, D is the same as for A,D. Usually
outputs C, D always have ZVS if sufficient delay is provided.
NOTE
The allowed resistor range on DELAB and DELCD, RAB and RCD are 13 kΩ to 90 kΩ.
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RA and RAHI define the portion of voltage at pin CS applied to the pin ADEL (See Typical Application Diagram).
KA defines how significantly the delay time depends on CS voltage. Ka varies from 0, where ADEL pin is shorted
to ground (RA = 0) and the delay does not depend on CS voltage, to 1, where ADEL is tied to CS (RAH = 0).
Setting KA, RAB and RCD provides the ability to maintain optimal ZVS conditions of primary switches over load
current because the voltage at CS pin includes reflected load current to primary side through the current sensing
circuit. The plots in Figure 4 and Figure 5 show the delay time settings as a function of CS voltage and KA for two
different conditions: RAB = RCD = 13 kΩ (Figure 4) and RAB = RCD = 90 kΩ (Figure 5 ).
TIME DELAY (RAB = RCD = 13 kW)
vs
CS VOLTAGE
350
TABSET, TCDSET - Time Delay - ns
300
250
KA = 0.0
KA = 0.1
200
KA = 0.25
KA = 0.50
150
KA = 0.75
KA = 1.0
100
50
5
0.0
0.2
0.4
0.6
0.8
1.0 1.2
1.4
1.6
1.8 2.0
CS Voltage - V
Figure 4. Delay Time Set TABSET and TCDSET
(Over CS voltage variation and selected KA for RAB and RCD equal 13 kΩ)
TIME DELAY (RAB = RCD = 90 kW)
vs
CS VOLTAGE
2000
TABSET, TCDSET - Time Delay - ns
1800
1600
1400
KA = 0.0
1200
KA = 0.1
1000
KA = 0.50
KA = 0.25
KA = 0.75
800
KA = 1.0
600
400
200
0
0.0
0.2
0.4
0.6
0.8
1.0 1.2
1.4
1.6
1.8 2.0
CS Voltage - V
Figure 5. Delay time set TABSET and TCDSET
(Over CS voltage variation and selected KA for RAB and RCD equal 90 kΩ)
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Adaptive Delay (Delay between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF))
The resistor REF from the DELEF pin to GND along with the resistor divider RAEFHI from CS pin to ADELEF pin
and RAEF from ADELEF pin to GND sets equal delays TAFSET and TBESET between outputs OUTA or OUTB going
low and related output OUTF or OUTE going low Figure 6.
OUTA
(OUTB)
OUTD
(OUTC)
TAFSET1
TBESET1
OUTF
(OUTE)
TAFSET2
TBESET2
Figure 6. Delay Definitions Between OUTA and OUTF, OUTB and OUTE
These delays gradually increase as function of CS signal from TAFSET1, which is measured at VCS = 0.2 V, to
TAFSET2, which is measured at VCS = 1.8 V. Opposite to the DELAB and DELCD behaviour, this delay is longest
(TAFSET2) when the signal at CS pin is maximized and shortest (TAFSET1) when the CS signal is minimized. This
approach will reduce the synchronous rectifier MOSFET body diode conduction time over a wide load current
range thus improving efficiency and reducing diode recovery time. Depending on the resistor divider RAEFHI and
RAEF, the proportional ratio between longest and shortest delay is set. If CS and ADELEF are tied, the ratio is
maximized. If ADELEF is connected to GND, then the delay is fixed, defined only by resistor REF from DELEF to
GND.
The delay time TAFSET is defined by the following Equation 6. The same defines the delay time TBESET.
ææ
ö
ö
5 ´ REF
TAFSET = ç ç
ns + 4ns ÷
÷
ç
÷
è è 2.65 V - CS ´ K EF ´ 1.32 ø
ø
(6)
In this equation REF is in kΩ, the CS, which is the voltage at pin CS, is in volts and KEF is a numerical gain factor
of CS voltage from 0 to 1. The delay time TAFSET is in ns. This equation is empirical approximation of measured
data, thus, there is no unit agreement in it. As an example of calculation, assume REF = 15 kΩ, CS = 1 V and KEF
= 0.5. Then the TAFSET is going to be 41.7 ns. KEF is defined as:
K EF =
R AEF
R AEF + R AEF(hi)
(7)
RAEF and RAEFHI define the portion of voltage at pin CS applied to the pin ADELEF (See Typical Application
Diagram ). KEF defines how significantly the delay time depends on CS voltage. KEF varies from 0, where
ADELEF pin is shorted to ground (RAEF = 0) and the delay does not depend on CS voltage, to 1, where ADELEF
is tied to CS (RAEFHI = 0).
NOTE
The allowed resistor range on DELEF, REF is 13 kΩ to 90 kΩ.
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The plots in Figure 7 and Figure 8 show delay time settings as function of CS voltage and KEF for two different
conditions: REF = 13 kΩ (Figure 7) and REF = 90 kΩ (Figure 8)
TIME DELAY (TEF = REF = 13 kW)
vs
CS VOLTAGE
350
TAFSET, TBESET - Time Delay - ns
300
250
KA = 0.00
KA = 0.25
200
KA = 0.50
KA = 0.75
150
KA = 0.90
KA = 1.00
100
50
5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
CS Voltage - V
Figure 7. Delay Time TAFSET and TBESET
(Over CS voltage and selected KEF for REF equal 13 kΩ)
TIME DELAY (TAF = RBE = 90 kW)
vs
CS VOLTAGE
2000
TAFSET, TBESET - Time Delay - ns
1800
1600
1400
KA = 0.0
1200
KA = 0.4
1000
KA = 0.8
KA = 0.5
KA = 0.9
800
KA = 1.0
600
400
200
5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
CS Voltage - V
Figure 8. Delay Time TAFSET and TBESET
(Over CS voltage and selected KEF for REF equal 90 kΩ)
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Minimum Pulse (TMIN)
The resistor RTMIN from TMIN pin to GND sets fixed minimum pulse TMIN applied to the output rectifier enabling
ZVS of the primary switches at light load. If the output PWM pulse demanded by the feedback loop is shorter
than TMIN, then controller proceeds to the burst mode of operation where even number of TMIN pulses are
followed by the off time dictated by the feedback loop. The proper selection of TMIN duration is dictated by the
time it takes to raise the sufficient magnetizing current in the power transformer to maintain ZVS. The minimum
pulse TMIN is defined by the following Equation 8.
TMIN = (5.92 ´ RTMIN ) ns
(8)
In this equation RTMIN is in kΩ and TMIN is in ns.
NOTE
The minimum allowed resistor on TMIN, RTMIN is 13 kΩ.
The related plot is shown in Figure 9
MINIMUM TIME
vs
RESISTOR SETTING
900
800
TMIN - Minimum Time - ns
700
600
500
400
300
200
100
0
15 25 35 45 55 65 75 85 95 105 115 125
5
RTMIN - Resistor Setting - kW
Figure 9. Minimum Time TMIN Over Setting Resistor RTMIN
The value of minimum duty cycle DMIN is determined by Equation 9.
(
)
DMIN = TMIN ´ FSW (osc ) ´ 10-4 %
(9)
Here, FSW(osc) is oscillator frequency in kHz, TMIN is the minimum pulse in ns and DMIN is in percents.
Burst Mode
If the converter is commanding a duty cycle lower than TMIN, then the controller will go into Burst Mode. The
controller will always deliver even number of Power cycles to Power transformer. The controller always stops its
bursts with OUTB and OUTC power delivery cycle. If the controller is still demanding a duty cycle less than
TMIN, then the controller goes into shut down mode. Then it waits until the converter is demanding a duty cycle
equal or higher than TMIN before the controller puts out TMIN or a PWM duty cycle as dictated by COMP
voltage pin.
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Switching Frequency Setting (RT)
Connecting an external resistor RT between the RT pin and VREF pins sets the fixed frequency operation and
configures the controller as a master providing synchronization output pulses at SYNC pin with 0.5 duty cycle
and frequency equal to the internal oscillator. To set the converter in Slave Mode, connect the external resistor
RT between RT-pin to GND and place an 825-kΩ resistor form SS pin to GND in parallel to the SS_EN
capacitor. This configures the controller as a slave. The slave controller operates with 90° phase shift relatively to
the master converter if their SYNC pins are tied together. The switching frequency of the converter is equal to the
frequency of output pulses. The following Equation 10 defines the nominal switching frequency of the converter
configured as a master (resistor RT between RT-pin and VREF). On the UCC28950 there is an internal clock
oscillator frequency which is twice as that of the controller outputs frequency.
FSW (nom)
æ
ö
ç
÷
3
2.5 ´ 10
ç
÷ kHz
=
çæ
RT
kW ö ÷
+ 1´
çç ç
÷÷
V ø ø÷
è è VREF - 2.5 V
(10)
In this equation the RT is in kΩ, VREF is in volts and FSW(nom) is in kHz. This is also empirical approximation and
thus, there is no unit agreement. Assume for example, VREF = 5 V, RT = 65 kΩ. Then the switching frequency
FSW(nom) is going to be 92.6 kHz.
The Equation 11 defines the nominal switching frequency of converter if the converter configured as a slave and
the resistor RT is connected between RT pin and GND.
FSW (nom)
æ
ö
ç
÷
3
2.5 ´ 10
ç
÷ kHz
=
ç æ RT
kW ö ÷
+ 1´
çç
÷
V ÷ø ø
è è 2.5 V
(11)
In this equation the RT is in kΩ, and FSW(nom) is in kHz. Notice that for VREF = 5 V, Equation 10 and Equation 11
yield the same results.
The plot in Figure 10 shows how FSW(nom) depends on the resistor RT value when the VREF = 5 V. As it is seen
from Equation 10 and Equation 11, the switching frequency FSW(nom) is set to the same value for either master, of
slave configuration provided the same resistor value RT is used.
SWITCHING FREQUENCY
vs
RESISTOR RT VALUE
1000
FSW(nom) - Switching Frequency - kHz
900
800
700
600
500
400
300
200
100
0
5
15 25 35 45 55 65 75 85 95 105 115 125
RT - Resistor - kW
Figure 10. Converter Switching Frequency FSW(nom) Over Resistor RT Value
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Slope Compensation (RSUM)
Slope compensation is the technique that adds additional ramp signal to the CS signal and applied to the:
• Input of PWM comparator in case of peak current mode control.
• Input of cycle-by-cycle current limit comparator.
This prevents sub-harmonic oscillation at D > 50% (some publications suggest it might happen even at D <
50%). At low duty cycle and light load, the slope compensation ramp reduces noise sensitivity of Peak Current
Mode control.
Too much additional slope compensation ramp reduces benefits of PCM control. In case of cycle-by-cycle
current limit, the average current limit becomes lower and this might reduce the start up capability with the large
output capacitance. The optimal compensation slope varies depending on duty cycle, LO and LM.
The slope compensation is needed for the controller operating at peak current mode control or during the
cycle-by-cycle current limit at duty cycle above 50%. Placing a resistor from RSUM pin to ground allows the
controller to operate in peak current control mode. Connecting RSUM pin through resistor to VREF switches
controller to the voltage mode control with the internal PWM ramp. However, the resistor value still provides CS
signal compensation for cycle-by-cycle current limit. In other words, in VMC, the slope compensation is applied
only to cycle-by-cycle comparator. While in PCM, the slope compensation applied to both PWM and
cycle-by-cycle current limit comparators.
The operation logic of slope compensation circuit is shown in Figure 11.
COMP
4
+
+
Oscillator
VREF
VCM
0.85 V
CLK
PCM
Ramp
Generator
VMC
RAMP
Cycle-by-Cycle ILIM
RSUM
11
Two Direction
Current Sense
Ramp
Summing
CS_SLOPECOMP
+
CS 15
2V
+
-
Mode Select
GND
PCM
7
GND
Figure 11. The Operation Logic of Slope Compensation Circuit
The slope of the additional ramp, me, added to CS signal by placing a resistor from RSUM pin to the ground is
defined by the following Equation 12.
æ
öV
2.5
me = ç
÷
è 0.5 ´ RSUM ø ms
20
(12)
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If the resistor from RSUM pin is connected to VREF pin, then the controller operates in voltage mode control, still
having the slope compensation added to CS signal used for cycle-by-cycle current limit. In such a case the slope
is defined by the following Equation 13.
æ (V - 2.5 V) ö V
me = ç REF
÷
è 0.5 ´ RSUM ø ms
(13)
In Equation 12 and Equation 13, the VREF is in volts, RSUM is in kΩ, and me is in V/µs. These are empirical
equations without unit agreement. As an example, substituting VREF = 5 V and RSUM = 40 kΩ, yields the result
0.125 V/µs. The related plot of me as function of RSUM is shown in Figure 12. Because VREF = 5 V, the plots
generated from Equation 12 and Equation 13 coincide.
SLOPE
vs
RESISTOR
0.50
0.45
0.40
Slope - V/ms
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
5
20
40
60
80
100 120 140 160 180 200
Rsum - Resistor - kW
Figure 12. Slope of the Added Ramp Over Resistor RSUM
NOTE
The recommended resistor range for RSUM is 10 kΩ to 1 MΩ.
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Dynamic SR ON/OFF Control (DCM Mode)
The voltage at the DCM pin provided by the resistor divider Rdcmhi between VREF pin and DCM, and Rdcm
from DCM pin to GND, sets the percentage of 2-V current limit threshold for the Current Sense pin, (CS). If the
CS pin voltage falls below the DCM pin threshold voltage, then the controller initiates the light load power saving
mode, and shuts down the synchronous rectifiers, OUTE and OUTF. If the CS pin voltage is higher than the
DCM pin threshold voltage, then the controller runs in CCM mode. Connecting the DCM pin to VREF makes the
controller run in DCM mode and shuts both Outputs OUTE and OUTF. Shorting the DCM pin to GND disables
the DCM feature and the controller runs in CCM mode under all conditions.
VREF
1
20 mA
RDCM(hi)
CS
DCM
R = 77 kW
PWM
DCM_COMP
15
2-Cycle
Counter
+
R = 77 kW
0 = DCM
1 = CCM
12
C = 6.5 pF
RDCM
C = 6.5 pF
Other Blocks
Figure 13. DCM Functional Block
DUTY CYCLE
vs
LOAD CURRENT
Moving into
DCM Mode
0.8
VS(max)
Duty Cycle - %
0.6
Setting DMIN
15.6%
VS(min)
0.4
0.2
Burst Mode
Area
0
0
1
2
3
4
5
6
7
8
9
10
Load Current - A
Figure 14. Duty Cycle Change Over Load Current Change
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There is a nominal 20-µA switched current source used to create hysteresis. The current source is active only
when the system is in DCM Mode. Otherwise, it is inactive and does not affect the node voltage. Therefore, when
being in DCM region, the DCM threshold is the voltage divider plus ΔV explained in Equation 14 below. When
being in CCM region, the threshold is the voltage set by the resistor divider. When CS pin reaches the threshold
set on the DCM pin, the system waits to see two consecutive falling edge PWM cycles before switching from
CCM to DCM and vice-versa. The magnitude of the hysteresis is a function of the external resistor divider
impedance. The hysteresis can be calculated using the following Equation 14:
DV = 2 ´ 10 -5
RDCMHI ´ RDCM
RDCMHI + RDCM
(14)
PWM
DCM Threshold
+ Hysteresis
CS
E
F
Figure 15. Moving from DCM to CCM Mode
PWM
DCM Threshold
+ Hysteresis
CS
E
F
Figure 16. Moving from CCM to DCM Mode
DCM must be used in order to prevent reverse current in the output inductor which could cause the synchronous
FETS to fail.
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Current Sensing (CS)
The signal from current sense pin is used for cycle-by-cycle current limit, peak-current mode control, light-load
efficiency management and setting the delay time for outputs OUTA, OUTB, OUTC, OUTD and delay time for
outputs OUTE, OUTF. Connect the current sense resistor RCS between CS and GND. Depending on layout, to
prevent a potential electrical noise interference, it is recommended to put a small R-C filter between RCS resistor
and CS pin.
Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
The cycle-by-cycle current limit provides peak current limiting on the primary side of the converter when the load
current exceeds its predetermined threshold. For peak current mode control, certain leading edge blanking time
is needed to prevent the controller from false tripping due to switching noise. In order to save external RC filter
for the blanking time, an internal 30-ns filter at CS input is provided. The total propagation delay TCS from CS
pin to outputs is 100 ns. An external RC filter is still needed if the power stage requires more blanking time. The
2.0-V ±3% cycle-by-cycle current limit threshold is optimized for efficient current transformer based sensing. The
duration when a converter operates at cycle-by-cycle current limit depends on the value of soft-start capacitor
and how severe the over current condition is. This is achieved by the internal discharge current IDS Equation 15
and Equation 16 at SS pin.
IDS(master ) = (-25 ´ (1 - D ) + 5 )mA
(15)
IDS(slave) = (-25 ´ (1 - D ))mA
(16)
The soft-start capacitor value also determines the so called hiccup mode off-time duration. The behavior of the
converter during different modes of operation, along with related soft start capacitor charge/discharge currents
are shown in Figure 17.
SS Pin (V)
SS Clamp Voltage
4.65
Pull Up Threshold
3.70
3.60
Soft Start
Cycle-by-Cycle ILIM
Normal
.
Operation
OFF Time Before Restart
25 mA
Soft Restart
Fast Pull Up
by 1 kW Switch IDS = (-25 x (1-D)+5) mA
Output Enable
Threshold
ISS=25 mA
0.55
0.00
IHCC = 2.5 mA
Output Pulses (D)
Figure 17. Timing Diagram of Soft-Start Voltage VSS
24
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The largest discharge current of 20 µA is when the duty cycle is close to zero. This current sets the shortest
operation time during the cycle-by-cycle current limit which is defined as:
TCL(on _ master ) =
TCL(on _ slave) =
CSS ´ (4.65 V - 3.7 V )
20 mA
(17)
CSS ´ (4.65 V - 3.7 V )
25 mA
(18)
Thus, if the soft-start capacitor CSS = 100 nF is selected, then the TCL(on) time will be 5 ms.
To calculate the hiccup off time TCL(off) before the restart, the following Equation 19 or Equation 20 needs to be
used:
TCL(off _ master ) =
TCL(off _ slave) =
C SS ´ (3.6 V - 0.55 V )
2.5 mA
(19)
CSS ´ (3.6 V - 0.55 V )
4.9 mA
(20)
With the same soft start capacitor value 100 nF, the off time before the restart is going to be 122 ms. Notice, that
if the over current condition happens before the soft start capacitor voltage reaches the 3.7-V threshold during
start up, the controller limits the current but the soft start capacitor continues to be charged. As soon as the 3.7-V
threshold is reached, the soft-start voltage is quickly pulled up to the 4.65-V threshold by an internal 1-kΩ RDS(on)
switch and the cycle-by-cycle current limit duration timing starts by discharging the soft start capacitor.
Depending on specific design requirements, the user can override default parameters by applying external
charge or discharge currents to the soft start capacitor. The whole cycle-by-cycle current limit and hiccup
operation is shown in Figure 17. In this example the cycle-by-cycle current limit lasts about 5 ms followed by 122
ms of off time.
Similar to the over current condition, the hiccup mode with the restart can be overridden by the user if a pull up
resistor is connected between the SS and VREF pins. If the pull up current provided by the resistor exceeds 2.5
µA, then the controller remains in the latch off mode. In this case, an external soft-start capacitor value should be
calculated with the additional pull-up current taken into account. The latch off mode can be reset externally if the
soft-start capacitor is forcibly discharged below 0.55 V or the VDD voltage is lowered below the UVLO threshold.
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Synchronization (SYNC)
The UCC28950 allows flexible configuration of converters operating in synchronized mode by connecting all
SYNC pins together and by configuration of the controllers as master and/or slaves. The controller configured as
Master (resistor between RT and VREF) provides synchronization pulses at the SYNC pin with the frequency
equal to 2X the converter frequency FSW(nom) and 0.5 duty cycle. The controller configured as a Slave (resistor
between RT and GND and 825-kΩ resistor between SS_EN pin to GND) does not generate the synchronization
pulses. The Slave controller synchronizes its own clock to the falling edge of synchronization signal thus
operating 90° phase shifted versus the master converter’s frequency FSW(nom). Because the Slave is
synchronized to the falling edge of the SYNC pulses, the slave operates at 180˚ delayed versus Master’s CLK or
90˚ delayed versus output switching pulses of Master.
Such operation between Master and Slave provides maximum input capacitor and output capacitor ripple
cancellation effect if inputs and outputs of converters are tied together. To avoid system issues during the
synchronized operation of few converters the following conditions should be taken care of.
• If any converter is configured a as a Slave, the SYNC frequency must be greater than or equal to 1.8 times
the converter frequency.
• Slave converter does not start until at least one synchronization pulse has been received.
• If any or all converters are configured as Slaves, then each converter operates at its own frequency without
synchronization after receiving at least one synchronization pulse. Thus, If there is an interruption of
synchronization pulses at the slave converter, then the controller uses its own internal clock pulses to
maintain operation based on the RT value that is connected to GND in the Slave converter.
• In Master mode, SYNC pulses start after SS pin passes its Enable threshold which is 0.55 V.
• Slave starts generating SS/EN voltage even though synchronization pulses have not been received.
• It is recommended that the SS on the Master controller starts before the SS on the Slave controller; therefore
SS/EN pin on master converter must reach its Enable threshold voltage before SS/EN on the slave converter
starts for proper operation. On the same note, it’s recommended that TMIN resistors on both Master and Slave
are set at the same value.
CLK
SYNC_OUT
A
B
Figure 18. SYNC_OUT (Master Mode) Timing Diagram
SYNC_IN
CLK
A
B
Figure 19. SYNC_IN (Slave Mode) Timing Diagram
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Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
•
•
•
•
•
•
All MOSFET control outputs have 0.2-A drive capability.
The control outputs are configured as P-MOS and N-MOS totem poles with typical RDS(on) 20 Ω and 10 Ω
accordingly.
The control outputs are capable of charging 100-pF capacitor within 12 ns and discharge within 8 ns.
The amplitude of output control pulses is equal to VDD.
Control outputs are designed to be used with external gate MOSFET/IGBT drivers.
The design is optimized to prevent the latch up of outputs and verified by extensive tests.
The UCC28950 has outputs OUTA, OUTB driving the active leg, initiating the duty cycle leg of power MOSFETs
in phase-shifted full bridge power stage, and outputs OUTC, OUTD driving the passive leg, completing the duty
cycle leg, as it is shown in typical timing diagram in Figure 47. Outputs OUTE and OUTF are optimized to drive
the synchronous rectifier MOSFETs (Figure 20). These outputs have 200-mA peak-current capabilities and are
designed to drive relatively small capacitive loads like inputs of external MOSFET or IGBT drivers.
Recommended load capacitance should not exceed 100 pF. The amplitude of output signal is equal to VDD
voltage.
The capacitors COSS shown in Figure 20 are internal MOSFET capacitances that must be taken into account
during design procedure to estimate zero voltage condition and switching losses.
+
Lm
COSS
OUTA
VS
COSS
OUTC
LLK
RPR
XT
A
B
COSS
COSS
OUTB
OUTD
-
COSS
COSS
OUTE
OUTF
LO
DCR
CO
-
VOUT
+
Figure 20. Power Stage
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Supply Voltage (VDD)
Connect this pin to bias supply from 8 V to 17 V range. Place high quality, low ESR and ESL, at least 1-µF
ceramic bypass capacitor CVDD from this pin to GND. It is recommended to use 10-Ω resistor in series to VDD
pin to form RC filter with CVDD capacitor.
Ground (GND)
All signals are referenced to this node. It is recommended to have a separate quite analog plane connected in
one place to the power plane. The analog plane combines the components related to the pins VREF, EA+, EA-,
COMP, SS/EN, DELAB, DELCD, DELEF, TMIN, RT, RSUM. The power plane combines the components related
to the pins DCM, ADELEF, ADEL, CS, SYNC, OUTF, OUTE, OUTD, OUTC, OUTB, OUTA, and VDD. An
example of layout and ground planes connection is shown in Figure 21.
R1
VREF
GND 24
2
EA+
VDD 23
3
EA-
OUTA 22
A
4
COMP
OUTB 21
B
CSS
5
SS/EN
OUTC 20
C
RAB
6
DELAB
OUTD 19
D
RCD
7
DELCD
OUTE 18
E
REF
8
DELEF
OUTF 17
F
RT(min)
9
TMIN
SYNC 16
SYNC
C1
VDD
R5
R4
R6
CVDD
1
R3
VSENSE
UCC28950
CREF
R2
C3
C2
ENABLE
Analog
Plane
10 RT
RT
Power
Plane
CS 15
RA(hi)
RSUM)
11 RSUM
ADEL 14
RA
RDCM(hi)
VREF
12 DCM
ADELEF 13
RAEF(hi)
Current Sense
R7
RCS
RDCM
RAEF
Figure 21. Layout Recommendation for Analog and Power Planes
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TYPICAL CHARACTERISTICS
UVLO THRESHOLDS
vs
TEMPERATURE
UVLO HYSTERESIS
vs
TEMPERATURE
640
UVLO - Under Voltage Lockout Hysteresis - mV
UVLO - Under Voltage Lockout Thresholds - V
7.6
UVLO_RTH
7.4
7.2
7.0
UVLO_FTH
6.8
6.6
6.4
630
620
UVLO_HYST
610
600
590
580
6.2
-40
25
125
-40
TJ - Temperature - °C
125
TJ - Temperature - °C
Figure 22.
Figure 23.
SUPPLY CURRENT
vs
TEMPERATURE
STARTUP CURRENT
vs
TEMPERATURE
250
3.9
3.8
IDD - Startup Current - mA
IDD - Operating Supply Current - mA
25
3.7
3.6
200
150
100
3.5
3.4
50
-40
25
125
-40
TJ - Temperature - °C
25
125
TJ - Temperature - °C
Figure 24.
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
VOLTAGE REFERENCE (VDD = 12 V)
vs
TEMPERATURE
LINE VOLTAGE REGULATION (ILOAD = 10 mA)
vs
TEMPERATURE
5.010
5.001
ILOAD = 10 mA
5.000
ILOAD = 1 mA
4.995
ILOAD = 10 mA
4.990
4.985
VREF _ 10 mA _ 12 VDD
4.999
VREF - Line Voltage Regulation - V
VREF - Voltage Reference - V
5.005
ILOAD = 20 mA
4.980
4.997
4.995
VREF _ 10 mA _ 10 VDD
4.993
4.991
4.989
4.975
4.987
-40
25
125
4.985 -40
TJ - Temperature - °C
25
125
TJ - Temperature - °C
Figure 26.
Figure 27.
SHORT CIRCUIT CURRENT
vs
TEMPERATURE
MAXIMUM DUTY CYCLE
vs
TEMPERATURE
38.5
95.4
95.2
DMAX - Maximum Duty Cycle - %
38.0
Short Circuit Current - mA
VREF _ 10 mA _ 8 VDD
37.5
37.0
36.5
36.0
95.0
94.8
94.6
94.4
94.2
94.0
35.5
93.8
35.0
93.6
-40
25
125
-40
TJ - Temperature - °C
125
TJ - Temperature - °C
Figure 28.
30
25
Figure 29.
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TYPICAL CHARACTERISTICS (continued)
MAXIMUM SWITCHING FREQUENCY
vs
TEMPERATURE
NOMINAL SWITCHING FREQUENCY
vs
TEMPERATURE
1079
FSW(max) - Maximum Switching Frequency - Hz
FSW(nom) - Nominal Switching Frequency - Hz
95.4
95.0
94.6
94.0
1059
1039
1019
999
93.6
-40
-40
125
25
25
125
TJ - Temperature - °C
TJ - Temperature - °C
Figure 30.
Figure 31.
ERROR AMPLIFIER OFFSET VOLTAGE
vs
TEMPERATURE
0.00
VOLTAGE ERROR AMPLIFIER
(Open Loop Gain)
vs
TEMPERATURE
125
120
-0.10
AVOL - Voltage Error Amplifier - dB
Error Amplifier OFFSET voltage - mV
-0.05
-0.15
-0.20
VIO = 500 mV
-0.25
VIO = 3.6 V
-0.30
-0.35
VIO = 2.5 V
-0.40
-0.45
115
110
105
100
95
90
-0.50
-40
25
TJ - Temperature - °C
125
85
-40
25
125
TJ - Temperature - °C
Figure 32.
Figure 33.
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TYPICAL CHARACTERISTICS (continued)
ISS CHARGE CURRENT
vs
TEMPERATURE
SHUTDOWN/RESTART/RESET THRESHOLD
vs
TEMPERATURE
26.0
VSS(std) - Shutdown/Restart/Reset Threshold - V
0.60
ISS - Charge Current - mA
25.5
25.0
24.5
24.0
23.5
-40
0.50
0.45
0.40
0.35
0.30
125
25
0.55
-40
TJ - Temperature - °C
25
125
TJ - Temperature - °C
Figure 34.
Figure 35.
SS PULL-UP THRESHOLD
vs
TEMPERATURE
SS CLAMP VOLTAGE
vs
TEMPERATURE
4.69
3.71
VSS(CL) - SS Clamp Voltage - V
VSS(pu) - SS Pullup Threshold - V
4.69
3.71
3.70
3.70
4.68
4.68
4.68
4.68
4.68
4.67
4.67
3.69
4.67
-40
25
125
-40
TJ - Temperature - °C
Figure 36.
32
25
125
TJ - Temperature - °C
Figure 37.
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TYPICAL CHARACTERISTICS (continued)
CURRENT SENSE CYCLE-BY-CYCLE LIMIT
vs
TEMPERATURE
CURRENT SENSE PROPAGATION DELAY
vs
TEMPERATURE
110
TCS(prop) - Current Sense Propagation Delay - ns
VCS(lim) - Current Sense Cycle-By-Cycle Limit - V
1.996
1.994
1.992
1.990
1.988
1.986
1.984
107
104
101
98
95
-40
125
25
-40
TJ - Temperature - °C
125
TJ - Temperature - °C
Figure 38.
Figure 39.
OUTPUTS SINK RESISTANCE
vs
TEMPERATURE
OUTPUTS SINK RESISTANCE
vs
TEMPERATURE
17.5
RSINK - Outputs Sink Resistance - W
17.5
RSINK - Outputs Sink Resistance - W
25
RSINK_OUTF
RSINK_OUTD
15.5
RSINK_OUTA
13.5
11.5
9.5
RSINK_OUTE
RSINK_OUTC
15.5
RSINK_OUTB
13.5
11.5
9.5
7.5
7.5
-40
25
125
-40
25
125
TJ - Temperature - °C
TJ - Temperature - °C
Figure 40.
Figure 41.
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TYPICAL CHARACTERISTICS (continued)
OUTPUTS SOURCE RESISTANCE
vs
TEMPERATURE
OUTPUTS SOURCE RESISTANCE
vs
TEMPERATURE
25
RSRC - Outputs Source Resistance - W
RSRC - Outputs Source Resistance - W
25
RSRC_OUTF
RSRC_OUTC
23
RSRC_OUTA
21
19
17
15
RSRC_OUTE
RSRC_OUTD
23
RSRC_OUTB
21
19
17
15
-40
25
125
-40
25
TJ - Temperature - °C
125
TJ - Temperature - °C
Figure 42.
Figure 43.
DEAD TIME DELAY
vs
TEMPERATURE
DEAD TIME DELAY
vs
TEMPERATURE
50
280
TCDSET2
270
TOFFTIME - Dead Time Delay - ns
TOFFTIME - Dead Time Delay - ns
TCDSET1
TABSET1
45
40
TAFSET1
35
TABSET2
260
250
TAFSET2
240
TBESET2
230
TBESET1
30
220
-40
25
125
-40
TJ - Temperature - °C
125
TJ - Temperature - °C
Figure 44.
34
25
Figure 45.
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TYPICAL CHARACTERISTICS (continued)
DCM THRESHOLD
vs
TEMPERATURE
0.405
DCM - DCM Threshold - V
0.400
0.395
0.390
0.385
0.380
0.380
0.375
-40
25
125
TJ - Temperature - °C
Figure 46.
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APPLICATION INFORMATION
UCC28950 Application Description
The efficiency improvement of phase-shifted full-bridge DC/DC converter with UCC28950 is achieved by using
the synchronous rectification technique, control algorithm providing ZVS condition over the entire load current
range, accurate adaptive timing of the control signals between primary and secondary FETs and special
operating modes at light load for the highest efficiency and power saving. The simplified electrical diagram of this
converter is shown in Figure 47. The controller device is located on the secondary side of converter, although it
could be located on primary side as well. The location on secondary side allows easy power system level
communication and better handling of some transient conditions that require fast direct control of the
synchronous rectifier MOSFETs. The power stage includes primary side MOSFETs, QA, QB, QC, QD and
secondary side synchronous rectifier MOSFETs, QE and QF. For example, for the 12-V output converters in
server power supplies use of the center-tapped rectifier scheme with L-C output filter is a popular choice.
To maintain high efficiency at different output power conditions, the converter operates in nominal synchronous
rectification mode at mid and high output power levels, with transitioning to the diode rectifier mode at light load
and further followed by the burst mode, as the output power becomes even lower. All these transitions are based
on the current sensing on the primary side using the current sense transformer in this specific case.
TSW(nom)
TABSET2
OUTA
TABSET1
TCDSET2
TSW(osc)
OUTB
OUTC
TCDSET1
OUTD
TBESET1
OUTE
TAFSET1
TBESET2
OUTF
TAFSET2
IPR
VDSQE
TON = 0.5 x D x TSW(nom)
VDSQF
VOUT x (1-D) / D
VLOUT
VOUT
ILOUT
IOUT
Figure 47. Major Waveforms of Phase-Shifted Converter
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Major waveforms of the phase-shifted converter during nominal operation mode are shown in Figure 47. Upper
six waveforms in the Figure 47 show the output drive signals of the controller. At nominal mode, the outputs
OUTE and OUTF overlap during the part of the switching cycle when the both rectifier MOSFETs are conducting
and the windings of power transformer are shorted. Current, IPR, is the current flowing through the primary
winding of power transformer. The bottom four waveforms show the drain-source voltages of rectifier MOSFETs,
VDS_QE and VDS_QF, the voltage at the output inductor, V LOUT, and the current through the output inductor, I LOUT.
Proper timing between the primary switches and synchronous rectifier MOSFETs is critical to achieve highest
efficiency and reliable operation in this mode. The controller device adjusts the turn OFF timing of rectifier
MOSFETs as function of load current to ensure the minimum conduction time and reverse recovery losses of
their internal body diodes.
ZVS is an important feature of relatively high input voltage converters to reduce switching losses associated with
the internal parasitic capacitances of power switches and transformers. The controller ensures ZVS conditions
over the entire load current range by adjusting the delay time between the primary MOSFETs switching in the
same leg in accordance to the load variation. Controller also limits the minimum ON-time pulse applied to the
power transformer at light load, allowing the storage of sufficient energy in the inductive components of power
stage for the ZVS transition.
As soon as the load current keeps reducing from the mid load current down to no-load condition, the controller
selects the most efficient power saving mode by moving the converter from the nominal operation mode to the
discontinuous-current diode-rectification mode and, eventually, at very light-load and at no-load condition, to the
burst mode. These modes and related output signals, OUTE, OUTF, driving the rectifier MOSFETs, are shown in
Figure 48.
OUTE
(CCM Mode)
OUTF
(CCM Mode)
OUTE
OUTE and OUTF are disabled if VCS < VDCM
OUTF
OUTE and OUTF are disabled if VCS < VDCM
Burst Mode at light load with TMIN maintaining ZVS
(The time scale is different versus above diagram)
Transformer
Winding
Magnetizing
Current
Figure 48. Major Waveforms During Transitions Between Different Operating Modes
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It is necessary to prevent the reverse current flow through the synchronous rectifier MOSFETs and output
inductor at the light load, during parallel operation and at some transient conditions. Such reverse current results
in circulating of some extra energy between the input voltage source and the load and, therefore, causes
increased losses and reduces efficiency. Another negative effect of such reverse current is the loss of ZVS
condition. The suggested control algorithm prevents reverse current flow, still maintaining most of the benefits of
synchronous rectification by switching off the drive signals of rectifier MOSFETs in a predetermined way. At
some pre-determined load current threshold, the controller disables outputs OUTE and OUTF by bringing them
down to zero.
Synchronous rectification using MOSFETs requires some electrical energy to drive the MOSFETs. There is a
condition below some light-load threshold when the MOSFET drive related losses exceed the saving provided by
the synchronous rectification. At such light load, it is best to disable the drive circuit and use the internal body
diodes of rectifier MOSFETs, or external diodes in parallel with the MOSFETs, for more efficient rectification. In
most practical cases, the drive circuit needs to be disabled close to DCM mode. This mode of operation is called
discontinuous-current diode-rectification mode.
At very light-load and no-load condition, the duty cycle, demanded by the closed-feedback-loop control circuit for
output voltage regulation, can be very low. This could lead to the loss of ZVS condition and increased switching
losses. To avoid the loss of ZVS, the control circuit limits the minimum ON-time pulse applied to the power
transformer using resistor from TMIN pin to GND. Therefore, the only way to maintain regulation at very light load
and at no-load condition is to skip some pulses. The controller skips pulses in a controllable manner to avoid
saturation of the power transformer. Such operation is called burst mode. In Burst Mode there are always an
even number of pulses applied to the power transformer before the skipping off time. Thus, the flux in the core of
the power transformer always starts from the same point during the start of every burst of pulses.
Voltage Loop Compensation Recommendation
For best results in the voltage loop it is recommended to use Type 2 or Type 3 compensation network
(Figure 49). A type 2 compensation network does not require passive components CZ2 and RZ2. Type 1
compensation is not versatile enough for a phase shifted full bridge. When evaluating the COMP for best results
it is recommended to put a 1-kΩ resistor between the scope probe and the COMP pin of the UCC28950.
VOUT
CZ2
VREF
EA+
RI
+
EA1 kW
RD
RZ2
CZ1
R
RZ1
CP1
R
When evaluating COMP, for best
results put a 1-kW resistor between
COMP and probe.
Figure 49. Type 3 Compensation Evaluation
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Experimental Results Example
The following experimental results are based on 660-W output power prototype of phase shifted full-bridge
DC/DC converter. The input voltage is 300 V to 400 V and the output is 12 V, 55 A. The primary MOSFETs are
SPA11N60CFD and the synchronous rectifier MOSFETs are FDP047AN08A0, two in parallel. The measured
efficiency of the prototype is shown in Figure 50.
EFFICIENCY
vs
LOAD CURRENT
100
VIN = 300 V with LRES
98
96
Efficiency - %
94
92
VIN = 350 V with LRES
90
88
86
84
82
VIN = 400 V with LRES
80
0
5
10
15
20
25
30
35
40
45
50
55
Load Current - A
Figure 50. Efficiency of the Prototype Phase-Shifted Converter
(VIN = 300 V, 350 V and 400 V, VOUT = 12 V)
Because of the power saving need even at very light and no-load conditions, careful optimization of operation at
light load condition is required to set the proper boundaries between different operation modes. The result of this
optimization is shown in Figure 51. This plot demonstrates the power savings while moving from the synchronous
rectification mode above 1-A load current, into the discontinuous current mode with the diode rectification
between 0.3-A and 1-A load current, and eventually into the burst mode operation at load current below 0.3 A.
LIGHT-LOAD POWER LOSSES
vs
LOAD CURRENT
12
11
Light-Load Power Losses - W
10
DCM Mode
with Diode
Rectification
9
8
7
CCM Mode with
Synchronous FETs
6
5
4
3
Burst Mode
2
1
0
0
0.2
0.4
0.6
0.8 1.0
1.2
1.4
1.6
1.8 2.0
Load Current - A
Figure 51. Power Losses of the Prototype at Light-Load and No-Load Conditions
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28950
39
UCC28950
SLUSA16A – MARCH 2010 – REVISED JULY 2010
www.ti.com
REVISION HISTORY
Changes from Original (March 2010) to Revision A
Page
•
Changed UCC28950 Typical Application Diagram ............................................................................................................... 1
•
Changed Converter switching frequency from 1400 kHz to 1000 kHz ................................................................................. 3
•
Changed Functional Block Diagram ..................................................................................................................................... 8
•
Changed Typical Application Diagram .................................................................................................................................. 8
•
Added Figure 5 ................................................................................................................................................................... 15
•
Changed Equation .............................................................................................................................................................. 16
•
Added Typical Application Diagram .................................................................................................................................... 16
•
Added always deliver even number of Power cycles to Power transformer. ..................................................................... 18
•
Deleted deliver either one or two power delivery cycle pulses. If controller delivers a power delivery cycle for OUTB
and OUTC, then it stops. If it starts delivering to OUTA and OUTD, then it continues with another power delivery
cycle to OUTB and OUTC, and then it stops. ..................................................................................................................... 18
40
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28950
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jan-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
UCC28950PW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
UCC28950PWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
UCC28950PWR
Package Package Pins
Type Drawing
TSSOP
PW
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC28950PWR
TSSOP
PW
24
2000
346.0
346.0
33.0
Pack Materials-Page 2
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