ETC ES3986F

ES3986
Digital-Audio Processor
Product Brief
ESS Technology, Inc.
DESCRIPTION
FEATURES
The ES3986 digital-audio processor chip is ESS
Technology’s highly integrated, optimal-quality, and costeffective single-chip solution for the emerging digital-audio
market. Its target applications include internet audio
platforms, MP3 CD players in boom box and combination
systems, portable MP3 CD player, etc.
Based on the programmable multimedia processor (PMP)
architecture,
the
ES3986
integrates
softwareconfigurable 32-bit reduced instruction set computing
(RISC) processor and a 64-bit vector processor core. The
RISC CPU can be used in place of a microcontroller to
provide the functions of system management, user
interface, and peripheral control. The vector processor is
dedicated for audio-specific processing. In addition to
MPEG audio decoding, it will generate 3D sound effects,
and support karaoke features, such as key control and
echo. The chip also provides the voice-activated ADPCM
codec for voice recording and language learning through
MIC input.
The ES3986 supports a variety of CD servos directly to
provide the system solution of lower BOM cost and
manufacturing flexibility. With its low system power
consumption, the built-in antishock capabilities, and 16Mbit DRAM support, the ES3986 is very suitable for
portable audio applications.
Figure 1 shows a typical standalone system using a
MP3 player, where the MP3 stream from a CD-ROM is
passed to the ES3986, which parses the system layer
and decodes the audio layer. The decoded MPEG
audio and 3D sound enhancement is then passed to the
external audio DAC.
• Programmable multimedia processor (PMP)
architecture
• MPEG1/MPEG2 and MP3 audio decoder
• CD block decoder functions
• STC interpretation and audio phase-lock loop (PLL)
• 256/384 fs for audio system clock
• Programmable master clock for external audio DAC
• Independent bit clock for audio transmit and receive
• Power management
• 2.5V power supply with 5V-tolerant I/Os
• 3D sound and surround sound
• Karaoke function
• Vocal reverb: simulates a theater acoustic
environment
• 0.3W power dissipation
• 2-Mb DRAM support
• 100-pin plastic quad flat pack (PQFP) package digitalaudio processor
Remote
Control/
Keypad
Panel
Interface
CD ROM
ES3986
Digital-Audio
DRAM
1M x 16
Audio
Processor
AUDIO
DAC
Headphones
Amplifier
ROM
Figure 1 ES3986 VCD Processor System Block Diagram
ESS Technology, Inc.
SAM0393-031201
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ES3986 PRODUCT BRIEF
PINOUT
PINOUT
VDD
AUX6
AUX5
AUX7
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LWR#
LOE#
LCS3#
LCS1#
LCS0#
LA0
LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LA10
LA11
VSS
The pinouts for the ES3896 are shown in Figure 2.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VPP
81
50
VSS
LA12
82
49
AUX4
LA13
83
AUX3
LA14
84
48
47
LA15
85
46
AUX1
LA16
86
45
AUX0
LA17
87
ACLK
88
44
43
NC
NC
AOUT/SEL_PLL0
89
42
CPUCLK
ATCLK
90
NC
ATFS/SEL_PLL1
91
41
40
DA9/DOE#
92
39
NC
AIN
93
38
NC
ARCLK
94
NC
ARFS
95
37
36
TDMCLK
96
35
NC
TDMDR
97
NC
TDMFS
98
34
33
CAS#
99
32
31
NC
NC
NC
NC
VDD
VSS
RESET#
DBUS15
DBUS14
DBUS13
DBUS12
DBUS11
DBUS10
DBUS9
DBUS8
DBUS7
DBUS66
DBUS5
DBUS4
DBUS3
DBUS2
DBUS1
DBUS0
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DWE#
VDD
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
RAS#
VSS
ES3986F
100-pin PQFP
AUX2
Figure 2 ES3986 Pinout Diagram
2
SAM0393-031201
ESS Technology, Inc.
ES3986 PRODUCT BRIEF
ES3986 PIN DESCRIPTIONS
ES3986 PIN DESCRIPTIONS
The ES3986 pins are listed and described in Table 1.
Table 1 ES3896 Pin Descriptions
Names
Pin Numbers
I/O
VDD
1, 31, 51
I
Voltage supply for 2.5V.
RAS#
2
O
DRAM row address strobe (active low).
DWE#
3
O
DRAM write enable (active low).
DA[8:0]
4:12
O
DRAM multiplexed row and column address bus.
DBUS[15:0]
13:28
I/O
DRAM data bus.
29
I
System reset (active low).
VSS
30, 50, 80, 100
I
Ground.
NC
32:41, 43, 44
—
CPUCLK
42
I
AUX[7:0]
44:49, 54, 52,
53,
I/O
Auxiliary control pins (AUX0 and AUX1 are open collectors.)
LD[7:0]
55:62
I/O
RISC interface data bus.
LWR#
63
O
RISC interface write enable (active low).
LOE#
64
O
RISC interface output enable (active low).
65, 66, 67
O
RISC interface chip select (active low).
68:79, 82:87
O
RISC interface address bus.
VPP
81
I
Digital supply voltage for 5V.
ACLK
88
I/O
Master clock for external audio DAC (8.192 MHz, 11.2896 MHz, 12.288 MHz, 16.9344
MHz, and 18.432 MHz)
AOUT/
SEL_PLL0
89
O
Dual-purpose pin. AOUT is the audio interface serial data output.
I
Pins SEL_PLL[1:0] select phase-lock loop (PLL) clock frequency CPUCLK
for the ES3986:
00 = bypass PLL
01 = 54-MHz PLL
10 = 67.5-MHz PLL
11 = 81-MHz PLL.
ATCLK
90
I/O
Audio transmit bit clock.
ATFS/
SEL_PLL1
91
O
Dual-purpose pin. ATFS is the audio interface transmit frame sync.
I
Pins SEL_PLL[1:0] select phase-lock loop clock frequency CPUCLK for the ES3986.
(Refer to the SEL_PLL0 pin above for the settings.)
DA9/DOE#
92
O
Dual-purpose pin: DRAM output enable (active low)/DRAM multiplexed row and column
address bus.
AIN
93
I
Audio interface serial data input.
ARCLK
94
I
Audio receive bit clock.
ARFS
95
I
Audio interface receive frame sync.
TDMCLK
96
I
TDM interface serial clock.
TDMDR
97
I
TDM interface serial data receive.
TDMFS
98
I
TDM interface frame sync.
CAS#
99
O
DRAM column address strobe bank 0 (active low).
RESET#
LCS[3,1,0]#
LA[17:0]
ESS Technology, Inc.
Definitions
No Connect.
RISC and system clock input.
CPUCLK is used only if SEL_PLL[1:0] = 00.
SAM0393-031201
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ES3986 PRODUCT BRIEF
ORDERING INFORMATION
ORDERING INFORMATION
Description
Part Number
ES3986F
Digital-Audio Processor
ESS Technology, Inc.
48401 Fremont Blvd.
Fremont, CA 94538
Tel: (510) 492-1088
Fax: (510) 492-1898
4
Package
100-pin PQFP
No part of this publication may be reproduced, stored in a
retrieval system, transmitted, or translated in any form or
by any means, electronic, mechanical, manual, optical, or
otherwise, without the prior written permission of ESS
Technology, Inc.
ESS Technology, Inc. makes no representations or
warranties regarding the content of this document.
All specifications are subject to change without prior
notice.
(P) U.S. patents pending.
Visba, SmartScale, SmartStream, and VideoDrive are
trademarks of ESS Technology, Inc.
MPEG is the Moving Picture Experts Group of the ISO/
IEC. References to MPEG2 in this document refer to the
ISO/IEC 13818-1.
All other trademarks are owned by their respective
holders and are used for identification purposes only.
ESS Technology, Inc. assumes no responsibility for any
errors contained herein.
© 2001 ESS Technology, Inc. All rights reserved.
SAM0393-031201