TPS650241-Q1 TPS650243-Q1 www.ti.com ......................................................................................................................................................................................... SLVS994 – SEPTEMBER 2009 POWER MANAGEMENT ICs FOR Li-ION POWERED SYSTEMS Check for Samples: TPS650241-Q1 TPS650243-Q1 FEATURES APPLICATIONS • • • • • • • 1 • • • • • • • • • • • Qualified for Automotive Applications 1.6-A, 1.0-A or 0.8-A, 97% Efficient Step-Down Converter for System Voltage (VDCDC1) – 3.3-V or 2.80-V or Adjustable 1.6-A, 1.0-A or 0.8-A, up to 95% Efficient Step-Down Converter for Memory Voltage (VDCDC2) – 1.8 V or 2.5 V or Adjustable 0.8-A 90% Efficient Step-Down Converter for Processor Core (VDCDC3) Two Selectable Voltages for VDCDC3 – TPS650241 – DEFDCDC3 = LOW: VO = 0.9 V – DEFDCDC3 = HIGH: VO = 1.375 V – TPS650243 – DEFDCDC3 = LOW: VO = 1.0 V – DEFDCDC3 = HIGH: VO = 1.2 V 30-mA LDO for Vdd_alive Two 200-mA General Purpose LDOs (LDO1 and LDO2) Dynamic Voltage Management for Processor Core LDO1 and LDO2 Voltage Externally Adjustable Separate Enable Pins for Inductive Converters 2.25-MHz Switching Frequency 85-μA Quiescent Current Thermal Shutdown Protection PDA Cellular/Smart Phone GPS Digital Still Camera Split Supply DSP and Microprocessor Solutions: Samsung ARM-Based Processors, etc. DESCRIPTION The TPS65024x are integrated Power Management ICs for applications powered by one Li-Ion or Li-Polymer cell, which require multiple power rails. The TPS65024x provide three highly efficient, step-down converters targeted at providing the core voltage, peripheral, I/O and memory rails in a processor based system. All three step-down converters enter a low power mode at light load for maximum efficiency across the widest possible range of load currents. The converters can be forced into fixed frequency PWM mode by pulling the MODE pin high. The TPS65024x also integrate two general purpose 200-mA LDO voltage regulators, which are enabled with an external input pin. Each LDO operates with an input voltage range between 1.5 V and 6.5 V, allowing them to be supplied from one of the step-down converters or directly from the battery. The output voltage of the LDOs can be set with an external resistor divider for maximum flexibility. Additionally there is a 30-mA LDO typically used to provide power in a processor based system to a voltage rail that is always on. TPS65024x provide voltage scaling on DCDC3 using the DEFDCDC3 pin. This pin either needs to be connected to a logic HIGH or logic LOW level to set the output voltage of DCDC3. TPS65024x come in a small 5-mm x 5-mm 32-pin QFN package (RHB). ORDERING INFORMATION (1) TJ –40°C to 125°C (1) (2) PACKAGE QFN – RHB (2) Reel of 3000 ORDERABLE PART NUMBER TOP-SIDE MARKING TPS650241QRHBRQ1 TPS650241Q TPS650243QRHBRQ1 TPS650243Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TPS650241-Q1 TPS650243-Q1 SLVS994 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT –0.3 to 7 V –0.3 to 3.6 V Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3 2000 mA Peak current at all other pins 1000 mA Input voltage range on all pins except A/PGND, VLDO1 and VLDO2 pins with respect to AGND Voltage range on pins VLDO1 and VLDO2 with respect to AGND Continuous total power dissipation See Dissipation Rating Table TJ Operating junction temperature –40 to 125 °C Tst Storage temperature –65 to 150 °C 260 °C Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS PACKAGE RHB (1) 2 (1) RθJA TJ ≤ 25°C POWER RATING DERATING FACTOR ABOVE TJ = 25°C TJ = 70°C POWER RATING TJ = 85°C POWER RATING 35°C/W 2.85 W 28 mW/°C 1.57 W 1.14 W The thermal resistance junction to ambient of the RHB package is measured on a high K board. The thermal resistance junction to power pad is 1.5°C/W. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650241-Q1 TPS650243-Q1 www.ti.com ......................................................................................................................................................................................... SLVS994 – SEPTEMBER 2009 RECOMMENDED OPERATING CONDITIONS MIN VINDCDC1, VINDCDC2, VINDCDC3, VCC Input voltage range step-down converters VDCDC1 NOM MAX UNIT 2.5 6.0 V Output voltage range for VDCDC1 step-down converter (1) 0.6 VINDCDC1 V VDCDC2 Output voltage range for mem step-down converter (1) 0.6 VINDCDC2 V VDCDC3 Output voltage range for core step-down converter 0.9 1.5 V VINLDO1, VINLDO2 Input voltage range for LDOs 1.5 6.5 V VLDO1-2 Output voltage range for LDOs 1.0 3.3 IOUTDCDC1 Output current at L1 L1 Inductor at L1 (2) 1600 1.5 CINDCDC1 Input capacitor at VINDCDC1 COUTDCDC1 Output capacitor at VDCDC1 (2) IOUTDCDC2 Output current at L2 L2 Inductor at L2 (2) CINDCDC2 Input capacitor at VINDCDC2 (2) 10 COUTDCDC2 Output capacitor at VDCDC2 (2) 10 22 IOUTDCDC3 Output current at L3 L3 Inductor at L3 (2) 1.5 2.2 CINDCDC3 Input capacitor at VINDCDC3 (2) 10 COUTDCDC3 Output capacitor at VDCDC3 (2) 10 10 μF μF 22 1600 1.5 (2) Input capacitor at VCC Cin1-2 Input capacitor at VINLDO (2) COUT1-2 Output capacitor at VLDO1, VLDO2 (2) ILDO1,2 Output current at VLDO1, VLDO2 CVRTC Output capacitor at Vdd_alive (2) IVdd_alive Output current at Vdd_alive TA Operating ambient temperature TJ Operating junction temperature RCC Resistor from VINDCDC3,VINDCDC2, VINDCDC1 to Vcc used for filtering (3) mA μH 2.2 μF μF 800 CVCC (1) (2) (3) 10 μH 2.2 (2) V mA mA μH μF μF 22 1 μF 1 μF 2.2 μF 200 mA 30 mA –40 125 °C –40 125 °C 10 Ω μF 2.2 1 When using an external resistor divider at DEFDCDC2, DEFDCDC1. See applications section for more information, for Vout > 2.85 V choose 3.3-μH inductor. Up to 2.5 mA can flow into Vcc when all three converters are running in PWM; this resistor causes the UVLO threshold to be shifted accordingly. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 Submit Documentation Feedback 3 TPS650241-Q1 TPS650243-Q1 SLVS994 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) CONTROL SIGNALS: EN_DCDC1, EN_DCDC2, EN_DCDC3, EN_LDO, MODE, EN_VDD_ALIVE MAX UNIT VIH PARAMETER High level input voltage TEST CONDITIONS 1.45 MIN TYP VCC V VIL Low level input voltage 0 0.4 V IH Input bias current 0.01 0.1 μA 135 170 μA PFM All three dc-dc converters enabled, zero load and no switching, LDO1, LDO2 = OFF, Vdd_alive = ON 75 100 PFM DCDC1 and DCDC2 converters enabled, zero load and no switching, LDO1, LDO2 = OFF, Vdd_alive = ON 55 80 PFM DCDC1 converter enabled, zero load and no switching, LDO1, LDO2 = OFF, Vdd_alive = ON 40 60 SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3 I(qPFM) Operating quiescent current IVCC(PWM) Current into Vcc, PWM PFM All three dc-dc converters enabled, zero load and no switching, LDOs enabled All three dc-dc converters enabled and running in PWM, LDOs off Vcc = 3.6 V Vcc = 3.6 V PWM DCDC1 and DCDC2 converters enabled and running in PWM, LDOs off PWM DCDC1 converter enabled and running in PWM, LDOs off Iq Quiescent current All converters disabled, LDO1, LDO2 = OFF, Vdd_alive = OFF Vcc = 3.6 V All converters disabled, LDO1, LDO2 = OFF, Vdd_alive = ON 4 Submit Documentation Feedback 2 mA 1.5 2.5 0.85 2.0 16 μA 26 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650241-Q1 TPS650243-Q1 www.ti.com ......................................................................................................................................................................................... SLVS994 – SEPTEMBER 2009 ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDCDC1 STEP-DOWN CONVERTER VVINDCDC1 Input voltage range 2.5 6.0 IO Maximum output current VO = 3.3 V ISD Shutdown supply current in VINDCDC1 EN_DCDC1 = GND 0.1 1 μA RDS(ON) P-channel MOSFET on-resistance VINDCDC1 = VGS = 3.6 V 125 261 mΩ ILP P-channel leakage current VINDCDC1 = 6.0 V 2 μA RDS(ON) N-channel MOSFET on-resistance VINDCDC1 = VGS = 3.6 V 130 260 mΩ ILN N-channel leakage current VDS = 6.0 V 7 10 μA ILIMF Forward current limit (P- and N-channel) 2.5V < VINMAIN < 6.0 V 1.7 1.97 2.2 A fS Oscillator frequency 1.95 2.25 2.55 MHz VDCDC1 Fixed output voltage MODE = 0 (PWM/PFM) 2.80 V Fixed output voltage MODE = 1 (PWM) 2.80 V 1600 mA VINDCDC1 = 3.3 V to 6.0 V; 0 mA ≤ IO ≤ 1.6A –2% 2% –2% 2% VINDCDC1 = 3.7 V to 6.0 V; 0 mA ≤ IO ≤ 1.6 A –1% 1% –1% 1% Adjustable output voltage with resistor divider at DEFDCDC1 MODE = 0 (PWM/PFM) VINDCDC1 = VDCDC1 + 0.4 V (min 2.5 V) to 6.0 V; 0 mA ≤ IO ≤ 1.6 A –2% 2% Adjustable output voltage with resistor divider at DEFDCDC1; MODE = 1 (PWM) VINDCDC1 = VDCDC1 + 0.4 V (min 2.5 V) to 6.0 V; 0 mA ≤ IO ≤ 1.6 A –1% 1% Line regulation VINDCDC1 = VDCDC1 + 0.3 V (min 2.5 V) to 6.0 V; IO = 10 mA Load regulation tSS Soft start ramp time R(L1) Internal resistance from L1 to GND 3.3 V 3.3 V V 0.0 %/V IO = 10 mA to 1.6 A 0.25 %/A VDCDC1 ramping from 5% to 95% of target value 750 μs 1 MΩ Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 Submit Documentation Feedback 5 TPS650241-Q1 TPS650243-Q1 SLVS994 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDCDC2 STEP-DOWN CONVERTER VVINDCDC2 Input voltage range 2.5 6.0 IO Maximum output current VO = 2.5 V ISD Shutdown supply current in VINDCDC2 EN_DCDC2 = GND 0.1 1 μA RDS(ON) P-channel MOSFET on-resistance VINDCDC2 = VGS = 3.6 V 140 300 mΩ ILP P-channel leakage current VINDCDC2 = 6.0 V 2 μA RDS(ON) N-channel MOSFET on-resistance VINDCDC2 = VGS = 3.6 V 150 297 mΩ ILN N-channel leakage current VDS = 6.0 V 7 10 μA ILIMF Forward current limit (P- and N-channel) 2.5 V < VINDCDC2 < 6.0 V 1.22 1.35 1.50 A fS Oscillator frequency 1.95 2.25 2.55 MHz VDCDC2 Fixed output voltage MODE = 0 (PWM/PFM) 1000 mA 1.8V VINDCDC2 = 2.5 V to 6.0 V; 0 mA ≤ IO ≤ 1.6 A –2% 2% 2.5V VINDCDC2 = 3.0 V to 6.0 V; 0 mA ≤ IO ≤ 1.6 A –2% 2% 1.8V VINDCDC2 = 2.5 V to 6.0 V; 0 mA ≤ IO ≤ 1.6 A –2% 2% 2.5V VINDCDC2 = 3.0 V to 6.0 V; 0 mA ≤ IO ≤ 1.6 A –1% 1% Adjustable output voltage with resistor divider at DEFDCDC2 MODE = 0 (PWM) VINDCDC2 = VDCDC2 + 0.5 V (min 2.5 V) to 6.0 V; 0 mA ≤ IO ≤ 1.6 A –2% 2% Adjustable output voltage with resistor divider at DEFDCDC2; MODE = 1 (PWM) VINDCDC2 = VDCDC2 + 0.5 V (min 2.5 V) to 6.0 V; 0 mA ≤ IO ≤ 1.6 A –1% 1% Line regulation VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V) to 6.0 V; IO = 10 mA Load regulation tSS Soft start ramp time R(L2) Internal resistance from L2 to GND Fixed output voltage MODE = 1 (PWM) 6 Submit Documentation Feedback V 0.0 %/V IO = 10 mA to 1.6 A 0.25 %/A VDCDC2 ramping from 5% to 95% of target value 750 μs 1 MΩ Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650241-Q1 TPS650243-Q1 www.ti.com ......................................................................................................................................................................................... SLVS994 – SEPTEMBER 2009 ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDCDC3 STEP-DOWN CONVERTER VVINDCDC3 Input voltage range 2.5 6.0 IO Maximum output current VO = 1.6 V ISD Shutdown supply current in VINDCDC3 EN_DCDC3 = GND 0.1 1 μA RDS(ON) P-channel MOSFET on-resistance VINDCDC3 = VGS = 3.6 V 310 698 mΩ ILP P-channel leakage current VINDCDC3 = 6.0V 0.1 2 μA RDS(ON) N-channel MOSFET on-resistance VINDCDC3 = VGS = 3.6 V 220 503 mΩ ILN N-channel leakage current VDS = 6.0 V 7 10 μA ILIMF Forward current limit (P- and N-channel) 2.5 V < VINDCDC3 < 6.0 V 1.00 1.20 1.40 A fS Oscillator frequency 1.95 2.25 2.55 MHz VDCDC3 Fixed output voltage VO = 0.9V to MODE = 0 1.6V (PWM/PFM) VINDCDC3 = 2.5 V to 6.0 V; 0 mA ≤ IO ≤ 800 mA –2% 2% –1% 1% 800 Fixed output voltage MODE = 1 (PWM) Line regulation VINDCDC3 = VDCDC3 + 0.3 V (min. 2.5 V) to 6.0 V; IO = 10 mA Load regulation tSS Soft start ramp time R(L3) Internal resistance from L3 to GND V mA 0.0 %/V IO = 10 mA to 600 mA 0.25 %/A VDCDC3 ramping from 5% to 95% of target value 750 μs 1 MΩ Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 Submit Documentation Feedback 7 TPS650241-Q1 TPS650243-Q1 SLVS994 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VLDO1 and VLDO2 Low Dropout Regulators I(q) Operating quiescent current Current per LDO into VINLDO 16 30 μA I(SD) Shutdown current Total current into VINLDO, VLDO = 0 V 0.6 2 μA VINLDO Input voltage range for LDO1, LDO2 6.5 V VFB LDO1 and LDO2 feedback voltage See IO Maximum output current for LDO1, LDO2 Vin = 1.8 V, Vo = 1.3 V IO Maximum output current for LDO1, LDO2 Vin = 1.5 V; Vo = 1.3 V ISC LDO1 & LDO2 short circuit current limit VLDO1 = GND, VLDO2 = GND 400 mA Minimum voltage drop at LDO1, LDO2 IO = 50 mA, VINLDO = 1.8 V 120 mV Minimum voltage drop at LDO1, LDO2 IO = 50 mA, VINLDO = 1.5 V 150 mV Minimum voltage drop at LDO1, LDO2 IO = 200 mA, VINLDO = 1.8 V 300 mV Output voltage accuracy for LDO1, LDO2 IO = 10 mA –2% 1% Line regulation for LDO1, LDO2 VINLDO1,2 = VLDO1,2 + 0.5 V (min 2.5 V) to 6.5 V, IO = 10 mA –1% 1% Load regulation for LDO1, LDO2 IO = 0 mA to 200 mA –1% Regulation time for LDO1, LDO2 Load change from 10% to 90% 10 IO = 0 mA 1.2 1.5 (1) 1.0 V 200 mA 120 65 mA 1% μs Vdd_alive Low Dropout Regulator Vdd_alive Vdd_alive LDO output voltage IO Output current for Vdd_alive ISC Vdd_alive short circuit current limit Vdd_alive = GND Output voltage accuracy for Vdd_alive IO = 0mA –1% Line regulation for Vdd_alive VCC = Vdd_alive + 0.5 V to 6.5 V, IO = 0 mA –1% Regulation time for Vdd_alive Load change from 10% to 90% V 30 mA 100 mA 1% 1% μs 10 AnaLogic Signals DEFDCDC1, DEFDCDC2, DEFDCDC3 VIH High level input voltage 1.3 VCC VIL Low level input voltage 0 0.1 V IH Input bias current 0.05 μA 0.001 V THERMAL SHUTDOWN TSD Thermal shutdown Increasing junction temperature 160 °C Thermal shutdown hysteresis Decreasing junction temperature 20 °C INTERNAL UNDER VOLTAGE LOCK OUT UVLO Internal UVLO VUVLO_HYST Internal UVLO comparator hysteresis VCC falling –3% 2.35 3% 120 V mV VOLTAGE DETECTOR COMPARATOR PWRFAIL_SNS Comparator threshold Falling threshold Hysteresis VOL (1) 8 –2% 1.0 2% V 40 50 60 mV Propagation delay 25-mV overdrive 10 μs Power fail output low voltage IOL = 5 mA 0.3 V If the feedback voltage is forced higher than 1.2 V, a leakage current into the feedback pin may occur. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650241-Q1 TPS650243-Q1 www.ti.com ......................................................................................................................................................................................... SLVS994 – SEPTEMBER 2009 DEVICE INFORMATION DEFDCDC3 AGND1 PWRFAIL_SNS Vcc VINDCDC2 L2 PGND2 VDCDC2 PIN ASSIGNMENTS 32 31 30 29 28 27 26 25 VDCDC3 PGND3 L3 VINDCDC3 VINDCDC1 L1 PGND1 VDCDC1 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 EN_Vdd_alive MODE DEFDCDC2 PWRFAIL EN_DCDC1 EN_DCDC2 EN_DCDC3 EN_LDO DEFDCDC1 FB_LDO2 FB_LDO1 Vdd_alive AGND2 VLDO2 VINLDO VLDO1 9 10 11 12 13 14 15 16 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION SWITCHING REGULATOR SECTION AGND1 31 Analog ground connection. All analog ground pins are connected internally on the chip. AGND2 13 Analog ground connection. All analog ground pins are connected internally on the chip. PowerPad – VINDCDC1 5 L1 6 VDCDC1 8 PGND1 7 VINDCDC2 28 L2 27 VDCDC2 25 PGND2 26 VINDCDC3 4 L3 3 VDCDC3 1 PGND3 2 Vcc 29 I Power supply for digital and analog circuitry of DCDC1, DCDC2 and DCDC3 DC-DC converters. This must be connected to the same voltage supply as VINDCDC3, VINDCDC1 and VINDCDC2. DEFDCDC1 9 I Input signal indicating default VDCDC1 voltage, 0 = 2.80 V, 1 = 3.3 V Connect the power pad to analog ground. I Input voltage for VDCDC1 step-down converter. This must be connected to the same voltage supply as VINDCDC2, VINDCDC3 and VCC. Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here. I VDCDC1 feedback voltage sense input, connect directly to VDCDC1 Power ground for VDCDC1 converter I Input voltage for VDCDC2 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC3 and VCC. Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here. I VDCDC2 feedback voltage sense input, connect directly to VDCDC2 Power ground for VDCDC2 converter I Input voltage for VDCDC3 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC2 and VCC. Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here. I VDCDC3 feedback voltage sense input, connect directly to VDCDC3 Power ground for VDCDC3 converter This pin can also be connected to a resistor divider between VDCDC1 and GND. In this case the output voltage of the DCDC1 converter can be set in a range from 0.6 V to VINDCDC1. DEFDCDC2 22 I Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 2.5 V This pin can also be connected to a resistor divider between VDCDC2 and GND. In this case the output voltage of the DCDC2 converter can be set in a range from 0.6 V to VINDCDC2. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 Submit Documentation Feedback 9 TPS650241-Q1 TPS650243-Q1 SLVS994 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O DESCRIPTION DEFDCDC3 32 I Input signal indicating VDCDC3 voltage. TPS650241: 0 = 0.9 V, 1 = 1.375 V TPS650243: 0 = 1.0 V, 1 = 1.2 V EN_DCDC1 20 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator. EN_DCDC2 19 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator. EN_DCDC3 18 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator. LDO REGULATOR SECTION VINLDO 15 I Input voltage for LDO1 and LDO2 VLDO1 16 O Output voltage of LDO1 VLDO2 14 O Output voltage of LDO2 EN_LDO 17 I Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs EN_Vdd_alive 24 I Enable input for Vdd_alive LDO. Logic high enables the LDO, logic low disables the LDO Vdd_alive 12 O Output voltage for Vdd_alive FB_LDO1 11 I Feedback pin for LDO1 FB_LDO2 10 I Feedback pin for LDO2 CONTROL AND I2C SECTION MODE 23 I Select between Power Safe Mode and forced PWM Mode for DCDC1, DCDC2 and DCDC3. In Power Safe Mode PFM is used at light loads, PWM for higher loads. If PIN is set to high level, forced PWM Mode is selected. If Pin has low level, then Device operates in Power Safe Mode. PWRFAIL 21 O Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition. PWRFAIL_SNS 30 I Input for the comparator driving the /PWRFAIL output 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650241-Q1 TPS650243-Q1 www.ti.com ......................................................................................................................................................................................... SLVS994 – SEPTEMBER 2009 FUNCTIONAL BLOCK DIAGRAM TPS650240 1R VCC Vbat 1mF L1 VINDCDC 1 Vbat 10mF DCDC1 (I/O) ENABLE STEP-DOWN CONVERTER 1000 mA EN_DCDC 1 VINDCDC 2 Vbat DCDC 2 (memory) 10mF STEP-DOWN CONVERTER 800 mA EN_DCDC 2 ENABLE VINDCDC 3 Vbat VDCDC1 R1 22 mF DEFDCDC 1 PGND 1 R2 2.5V or 1.8V L2 VDCDC2 2.2 mH STEP-DOWN CONVERTER 800 mA DEFDCDC 3 EN_DCDC 3 R3 22 mF DEFDCDC 2 PGND 2 R4 1.0V or 1.3V L3 DCDC 3 (core) 10mF 1.0V / 1.3V ENABLE 3.3V or 2.8V 2.2 mH VDCDC 3 2.2uH 22 mF PGND 3 MODE PWM / PFM VIN_LDO VIN VLDO 1 VLDO1 R5 200 mA LDO EN_LDO ENABLE 2.2 mF R6 VLDO 2 VLDO2 R7 200 mA LDO R8 EN_Vdd_aliv e ENABLE VCC Vbat 2.2 mF VLDO 3 30 mA LDO Vdd_alive 1.2 V 2.2 mF R9 I/O voltage PWRFAIL _SNS R10 - PWRFAIL R19 + Vref = 1 V AGND 1 AGND2 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 Submit Documentation Feedback 11 TPS650241-Q1 TPS650243-Q1 SLVS994 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS Parameter Measurement Information Graphs were taken using the EVM with the following inductor/output capacitor combinations: CONVERTER INDUCTOR OUTPUT CAPACITOR OUTPUT CAPACITOR VALUE DCDC1 VLCF4020-3R3 C2012X5R0J226M 22 μF DCDC2 VLCF4020-2R2 C2012X5R0J226M 22 μF DCDC3 LPS3010-222 C2012X5R0J226M 22 μF Table of Graphs FIGURE η Efficiency VDCDC1 vs Load current PWM/PFM; VO = 3.3 V Figure 1 η Efficiency VDCDC1 vs Load current PWM; VO = 3.3 V Figure 2 η Efficiency VDCDC2 vs Load current PWM/PFM; VO = 1.8 V Figure 3 η Efficiency VDCDC2 vs Load current PWM; VO = 1.8 V Figure 4 η Efficiency VDCDC3 vs Load current PWM/PFM; VO = 1.3 V Figure 5 η Efficiency VDCDC3 vs Load current PWM; VO = 1.3 V Figure 6 12 Line transient response VDCDC1 Figure 7 Line transient response VDCDC2 Figure 8 Line transient response VDCDC3 Figure 9 Load transient response VDCDC1 Figure 10 Load transient response VDCDC2 Figure 11 Load transient response VDCDC3 Figure 12 Output voltage ripple DCDC2; PFM mode Figure 13 Output voltage ripple DCDC2; PWM mode Figure 14 Load regulation for Vdd_alive Figure 15 Start-up VDCDC1 to VDCDC3 Figure 16 Start-up LDO1 and LDO2 Figure 17 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650241-Q1 TPS650243-Q1 www.ti.com ......................................................................................................................................................................................... SLVS994 – SEPTEMBER 2009 DCDC1: EFFICIENCY vs OUTPUT CURRENT 100 100 90 90 VI = 3.8 V 80 VI = 4.2 V 70 VI = 5 V 60 50 40 60 VI = 3.8 V 50 VI = 4.2 V 40 30 30 VI = 5 V TA = 25°C, VO = 3.3 V, PFM/PWM Mode 20 10 0 0.1 TA = 25°C, VO = 3.3 V, PWM Mode 80 Efficiency - % 70 Efficiency - % DCDC1: EFFICIENCY vs OUTPUT CURRENT 1 10 100 1k IO - Output Current - mA 20 10 0 0.1 10k 1 10 100 1k IO - Output Current - mA Figure 1. Figure 2. DCDC2: EFFICIENCY vs OUTPUT CURRENT DCDC2: EFFICIENCY vs OUTPUT CURRENT 10k VI = 2.5 V VI = 3.8 V Efficiency - % Efficiency - % VI = 3.8 V VI = 4.2 V VI = 4.2 V VI = 2.5 V VI = 5 V VI = 5 V TA = 25oC VO = 1.8 V PWM Mode o TA = 25 C VO = 1.8 V PWM / PFM Mode 0.01 0.1 1 10 100 IO - Output Current - mA 1k 10 k 0.01 0.1 1 10 100 1k 10 k IO - Output Current - mA Figure 3. Figure 4. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 Submit Documentation Feedback 13 TPS650241-Q1 TPS650243-Q1 SLVS994 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com DCDC3: EFFICIENCY vs OUTPUT CURRENT DCDC3: EFFICIENCY vs OUTPUT CURRENT 100 100 TA = 25°C, 90 VO = 1.5 V, PWM/PFM Mode 80 80 60 VI = 3 V 50 VI = 3.8 V 30 0 0.01 VI = 3 V VI = 3.8 V 60 50 VI = 4.2 V 40 VI = 5 V 30 VI = 4.2 V 20 20 10 VI = 2.5 V 70 VI = 2.5 V Efficiency - % Efficiency - % 70 40 TA = 25°C, VO = 1.5 V, PWM Mode 90 VI = 5 V 0.1 10 1 10 100 IO - Output Current - mA 1k 0 0.01 0.1 1 10 100 IO - Output Current - mA Figure 5. Figure 6. VDCDC1 LINE TRANSIENT RESPONSE VDCDC2 LINE TRANSIENT RESPONSE Ch1 = VI 1k Ch1 = VI Ch2 = VO Ch2 = VO IO = 100 mA VI = 3.8 V to 4.5 V VO = 3.3 V IO = 100 mA VI = 3 V to 4 V VO = 1.8 V PWM Mode Figure 7. 14 Submit Documentation Feedback Figure 8. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650241-Q1 TPS650243-Q1 www.ti.com ......................................................................................................................................................................................... SLVS994 – SEPTEMBER 2009 VDCDC3 LINE TRANSIENT RESPONSE VDCDC1 LOAD TRANSIENT RESPONSE Ch1 = VI Ch1 = VI Ch2 = VO Ch2 = VO IO = 160 mA to 14000 mA VI = 3.3 V VO = 4.2 V IO = 100 mA VI = 3 V to 4 V VO = 1.375 V Figure 9. Figure 10. VDCDC2 LOAD TRANSIENT RESPONSE VDCDC3 LOAD TRANSIENT RESPONSE Ch4 = IO Ch4 = IO Ch2 = VO Ch2 = VO IO = 80 mA to 720 mA VO = 1.375 V IO = 100 mA to 900 mA VO = 1.8 V Figure 11. Figure 12. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 Submit Documentation Feedback 15 TPS650241-Q1 TPS650243-Q1 SLVS994 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com VDCDC2 OUTPUT VOLTAGE RIPPLE VDCDC2 OUTPUT VOLTAGE RIPPLE IO = 1 mA o TA = 25 C PFM Mode VI = 3.8 V VO = 1.8 V VI = 3.8 V VO = 1.8 V IO = 1 mA TA = 25oC PWM Mode Figure 13. Figure 14. VDD_ALIVE OUTPUT VOLTAGE vs OUTPUT CURRENT STARTUP VDCDC1, VDCDC2, VDCDC3 1.26 ENABLE VCC = 3.6 V VO - Output Voltage - V 1.24 VDCDC1 1.22 1.2 VDCDC2 1.18 VDCDC3 1.16 1.14 0 5 10 15 20 25 30 35 IO - Output Current - mA 40 45 Figure 15. 16 Submit Documentation Feedback Figure 16. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650241-Q1 TPS650243-Q1 www.ti.com ......................................................................................................................................................................................... SLVS994 – SEPTEMBER 2009 STARTUP LDO1 AND LDO2 ENABLE LDO1 LDO2 Figure 17. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 Submit Documentation Feedback 17 TPS650241-Q1 TPS650243-Q1 SLVS994 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com DETAILED DESCRIPTION STEP-DOWN CONVERTERS, VDCDC1, VDCDC2 AND VDCDC3 The TPS65024x incorporate three synchronous step-down converters operating typically at 2.25MHz fixed frequency PWM (Pulse Width Modulation) at moderate to heavy load currents. At light load currents the converters automatically enter Power Save Mode and operate with PFM (Pulse Frequency Modulation). VDCDC1 delivers up to 1.6A, VDCDC2 is capable of delivering up to 1.0A of output current while the VDCDC3 converter is capable of delivering up to 800mA. The converter output voltages can be programmed via the DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins. The pins can either be connected to GND, VCC or to a resistor divider between the output voltage and GND. The VDCDC1 converter defaults to 2.80V or 3.3V depending on the DEFDCDC1 configuration pin, if DEFDCDC1 is tied to ground the default is 2.80V, if it is tied to VCC the default is 3.3V. When the DEFDCDC1 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6V to VINDCDC1 V. Reference the section on Output Voltage Selection for details on setting the output voltage range. The VDCDC2 converter defaults to 1.8V or 2.5V depending on the DEFDCDC2 configuration pin, if DEFDCDC2 is tied to ground the default is 1.8V, if it is tied to VCC the default is 2.5V. When the DEFDCDC2 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6V to VINDCDC2 V. The VDCDC3 converter defaults to 1.0V or 1.3V for the TPS650240 depending on the DEFDCDC3 configuration pin, if DEFDCDC3 is tied to ground the default is 1.0V, if it is tied to VCC the default is 1.3V. The DEFDCDC3 pin cannot be connected to a resistor divider. In opposition to DEFDCDC1 and DEFDCDC2, the DEFDCDC3 pin can be used to change the core voltage during operation by changing its logic level from HIGH to LOW or vice versa. TPS65024x allow different voltages for the VDCDC3 converter. See Table 4 for the default voltage options. During PWM operation the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch in case the current limit of the P-channel switch is exceeded. After the adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off the N-channel rectifier and turning on the P-channel switch. The three DC/DC converters operate synchronized to each other, with the VDCDC1 converter as the master. A 180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3 switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7V to 3.3V, the VDCDC2 converter from 3.7V to 2.5V and the VDCDC3 converter from 3.7V to 1.5V. POWER SAVE MODE OPERATION As the load current decreases, the converters enter Power Save Mode operation. During Power Save Mode the converters operate in a burst mode (PFM mode) with a frequency between 1.125MHz and 2.25MHz for one burst cycle. However, the frequency between different burst cycles depends on the actual load current and is typically far less than the switching frequency, with a minimum quiescent current to maintain high efficiency. In order to optimize the converter efficiency at light load the average current is monitored and if in PWM mode the inductor current remains below a certain threshold, then Power Save Mode is entered. The typical threshold to enter Power Save Mode can be calculated as follows: 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650241-Q1 TPS650243-Q1 www.ti.com ......................................................................................................................................................................................... SLVS994 – SEPTEMBER 2009 I PFMDCDC1enter + VINDCDC 1 24 W I PFMDCDC2enter + VINDCDC 2 26 W I PFMDCDC3leave + VINDCDC 3 39 W (1) During Power Save Mode the output voltage is monitored with a comparator and by maximum skip burst width. As the output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the converter effectively delivers a constant current as defined below. I PFMDCDC1leave + VINDCDC 1 18 W I PFMDCDC2leave + VINDCDC 2 20 W I PFMDCDC3enter + VINDCDC 3 29 W (2) If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode if either of the following conditions are met: 1. The output voltage drops 2% below the nominal VO due to increased load current 2. The PFM burst time exceeds 16 × 1/fs (7.1μs typical) These control methods reduce the quiescent current to typically 14μA per converter and the switching activity to a minimum thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal output voltage at light load current results in a very low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor; increasing capacitor values makes the output ripple tend to zero. Power Save Mode can be disabled by pulling the MODE pin high. This forces all DC/DC converters into fixed frequency PWM mode. SOFT START Each of the three converters has an internal soft start circuit that limits the inrush current during start-up. The soft start is realized by using a very low current to initially charge the internal compensation capacitor. The soft start time is typically 750μs if the output voltage ramps from 5% to 95% of the final target value. If the output is already pre-charged to some voltage when the converter is enabled, then this time is reduced proportionally. There is a short delay of typically 170μs between the converter being enabled and switching activity actually starting. This is to allow the converter to bias itself properly, to recognize if the output is pre-charged, and if so, to prevent discharging of the output while the internal soft start ramp catches up with the output voltage. 100% DUTY CYCLE LOW DROPOUT OPERATION The TPS65024x converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve the longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage required to maintain DC regulation depends on the load current and output voltage and can be calculated as: Vin min + Vout min ) Iout max ǒRDSonmax ) R LǓ (3) With: Ioutmax = Maximum load current (note: ripple current in the inductor is zero under these conditions) RDSonmax = Maximum P-channel switch RDSon RL = DC resistance of the inductor Voutmin = Nominal output voltage minus 2% tolerance limit Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 Submit Documentation Feedback 19 TPS650241-Q1 TPS650243-Q1 SLVS994 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com LOW DROPOUT VOLTAGE REGULATORS The low dropout voltage regulators are designed to operate well with low value ceramic input and output capacitors. They operate with input voltages down to 1.5V. The LDOs offer a maximum dropout voltage of 300mV at the rated output current. Each LDO sports a current limit feature. Both LDOs are enabled by the EN_LDO pin. The LDOs also have reverse conduction prevention. This allows the possibility to connect external regulators in parallel in systems with a backup battery. The TPS65024x step-down and LDO voltage regulators automatically power down when the Vcc voltage drops below the UVLO threshold or when the junction temperature rises above 160°C. UNDERVOLTAGE LOCKOUT The undervoltage lockout circuit for the five regulators on the TPS65024x prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. It disables the converters and LDOs. The UVLO circuit monitors the Vcc pin; the threshold is set internally to 2.35V with 5% (120mV) hysteresis. Note that when any of the DC/DC converters are running there is an input current at the Vcc pin, which can be up to 3mA when all three converters are running in PWM mode. This current needs to be taken into consideration if an external RC filter is used at the Vcc pin to remove switching noise from the TPS65024x internal analog circuitry supply. See the Vcc-Filter section for details on the external RC filter. POWER-UP SEQUENCING The TPS65024x power-up sequencing is designed to be entirely flexible and customer driven; this is achieved simply by providing separate enable pins for each switch-mode converter and a common enable signal for LDO1 and LDO2. The relevant control pins are described in Table 1. Table 1. Control Pins for DCDC Converters PIN NAME INPUT/ OUTPUT DEFDCDC3 I Defines the default voltage of the VDCDC3 switching converter. See Table 4 for details. DEFDCDC2 I Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to 1.8V, DEFDCDC2 = VCC defaults VDCDC2 to 2.5V. DEFDCDC1 I Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 2.80V, DEFDCDC1 = VCC defaults VDCDC1 to 3.3V. EN_DCDC3 I Set EN_DCDC3 = 0 to disable or EN_DCDC3 = 1 to enable the VDCDC3 converter EN_DCDC2 I Set EN_DCDC2 = 0 to disable or EN_DCDC2 = 1 to enable the VDCDC2 converter EN_DCDC1 I Set EN_DCDC1 = 0 to disable or EN_DCDC1 = 1 to enable the VDCDC1 converter FUNCTION PWRFAIL The PWRFAIL signal is generated by a voltage detector at the PWRFAIL_SNS input. The input signal is compared to a 1V threshold (falling edge) with 5% (50mV) hysteresis. PWRFAIL is an open drain output which is actively low when the input voltage at PWRFAIL_SNS is below the threshold. DESIGN PROCEDURE Inductor Selection for the dcdc Converters The three converters operate with 2.2uH output inductors. Larger or smaller inductor values can be used to optimize performance of the device for specific conditions. The selected inductor has to be rated for its dc resistance and saturation current. The dc resistance of the inductor influences directly the efficiency of the converter. Therefore, an inductor with the lowest dc resistance should be selected for the highest efficiency. For a fast transient response, a 2.2μH inductor in combination with a 22μF output capacitor is recommended. For an output voltage above 2.8V, an inductor value of 3.3μH minimum is required. Lower values result in an increased output voltage ripple in PFM mode. The minimum inductor value is 1.5μH, but an output capacitor of 22μF minimum is needed in this case. Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is recommended because during heavy load transient the inductor current rises above the calculated value. 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650241-Q1 TPS650243-Q1 www.ti.com ......................................................................................................................................................................................... SLVS994 – SEPTEMBER 2009 DI L + Vout 1 * Vout Vin L ƒ I Lmax + I outmax ) DI L 2 (4) With: f = Switching frequency (2.25 MHz typical) L = Inductor value ΔIL = Peak-to-peak inductor ripple current ILmax = Maximum inductor current The highest inductor current occurs at maximum Vin. Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus a comparable shielded inductor. A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. Consideration must be given to the difference in the core material from inductor to inductor which has an impact on efficiency especially at high switching frequencies. See Table 2 and the typical applications for possible inductors. Table 2. Tested Inductors DEVICE INDUCTOR VALUE TYPE COMPONENT SUPPLIER 3.3μH LPS3015-332 (output current up to 1A) Coilcraft 2.2μH LPS3015-222 (output current up to 1A) Coilcraft 3.3μH VLCF4020T-3R3N1R5 TDK 2.2μH VLCF4020T-2R2N1R7 TDK 2.2μH LPS3010-222 Coilcraft 2.2μH LPS3015-222 Coilcraft 2.2μH VLCF4020-2R2 TDK DCDC3 converter Output Capacitor Selection The advanced Fast Response voltage mode control scheme of the inductive converters implemented in the TPS65024x allows the use of small ceramic capacitors with a typical value of 10uF for each converter, without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low ESR values have the lowest output voltage ripple and are recommended. Refer to Table 3 for recommended components. If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application requirements. For completeness, the RMS ripple current is calculated as: 1 * Vout 1 Vin I RMSCout + Vout L ƒ 2 Ǹ3 (5) At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: 1 * Vout 1 Vin DVout + Vout ) ESR 8 Cout ƒ L ƒ (6) ǒ Ǔ Where the highest output voltage ripple occurs at the highest input voltage, Vin. At light load currents the converters operate in Power Save Mode and output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. Typical output voltage ripple is less than 1% of the nominal output voltage. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 Submit Documentation Feedback 21 TPS650241-Q1 TPS650243-Q1 SLVS994 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing interference with other circuits caused by high input voltage spikes. Each dcdc converter requires a 10uF ceramic input capacitor on its input pin VINDCDCx. The input capacitor can be increased without any limit for better input voltage filtering. The Vcc pin should be separated from the input for the DC/DC converters. A filter resistor of up to 10Ω and a 1μF capacitor should be used for decoupling the Vcc pin from switching noise. Note that the filter resistor may affect the UVLO threshold since up to 3mA can flow via this resistor into the Vcc pin when all converters are running in PWM mode. Table 3. Possible Capacitors CAPACITOR VALUE CASE SIZE 22μF 1206 TDK C3216X5R0J226M Ceramic 22μF 1206 Taiyo Yuden JMK316BJ226ML Ceramic 22μF 0805 TDK C2012X5R0J226MT Ceramic 22μF 0805 Taiyo Yuden JMK212BJ226MG Ceramic 10μF 0805 Taiyo Yuden JMK212BJ106M Ceramic 10μF 0805 TDK C2012X5R0J106M Ceramic COMPONENT SUPPLIER COMMENTS Output Voltage Selection The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down converter. See Table 4 for the default voltages if the pins are pulled to GND or to Vcc. Table 4. Voltage Options PIN DEFDCDC1 DEFDCDC2 DEFDCDC3 LEVEL All versions All versions TPS650241 TPS650243 DEFAULT OUTPUT VOLTAGE VCC 3.3V GND 2.80V VCC 2.5V GND 1.8V VCC 1.375V GND 0.9V VCC 1.2V GND 1.0V If a different voltage is needed, an external resistor divider can be added to the DEFDCDC1 or DEFDCDC2 pin as shown below: 10 R Vbat VCC 1 mF VDCDC1 L1 VINDCDC1 CIN COUT EN_DCDC1 VOUT L R1 DEFDCDC1 R2 AGND PGND When a resistor divider is connected to DEFDCDC1 or DEFDCDC2, the output voltage can be set from 0.6V up to the input voltage Vbat. The total resistance (R1+R2) of the voltage divider should be kept in the 1MΩ range in order to maintain a high efficiency at light load. VDEFDCDCx = 0.6V 22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650241-Q1 TPS650243-Q1 www.ti.com ......................................................................................................................................................................................... SLVS994 – SEPTEMBER 2009 V OUT + VDEFDCDCx R1 ) R2 R2 R1 + R2 ǒ V OUT VDEFDCDCx Ǔ * R2 Voltage Change on VDCDC3 The output voltage of VDCDC3 can be changed during operation from, for example, 0.9V to 1.375V (TPS650241) and back. While the output voltage at VDCDC1 and VDCDC2 is fixed after the device exits undervoltage lockout (UVLO), the status of the DEFDCDC3 pin is sensed during operation and the voltage is changed as soon as the logic level on this pin changes from low to high or vice versa. Therefore it is not possible to connect a resistor divider to DEFDCDC3 and set a voltage different from the predefined voltages. Vdd_alive Output The Vdd_alive LDO is typically connected to the Vdd_alive input of the Samsung application processor. It provides an output voltage of 1.2V at 30mA. For the TPS650245, the output voltage is 1.1V. It is recommended to add a capacitor of 2.2μF minimum to the Vdd_alive pin. The LDO can be disabled by pulling the EN_Vdd_alive pin to GND. LDO1 and LDO2 The LDOs in the TPS65024x are general purpose LDOs which are stable using ceramics capacitors. The minimum output capacitor required is 2.2μF. The LDOs output voltage can be changed to different voltages between 1.0V and Vin using an external resistor divider. Therefore they can also be used as general purpose LDOs in the application. The supply voltage for the LDOs needs to be connected to the VINLDO pin, giving the flexibility to connect the lowest voltage available in the system and therefore providing the highest efficiency. The total resistance (R5+R6) of the voltage divider should be kept in the 1MΩ range in order to maintain high efficiency at light load. VFBLDOx= 1.0V. V OUT + VFBLDOx R5 ) R6 R6 R5 + R6 ǒ V OUT VFBLDOx Ǔ * R6 Vcc-Filter An RC filter connected at the Vcc input is used to keep noise from the internal supply for the bandgap and other analog circuitry. A typical value of 1Ω and 1μF is used to filter the switching spikes, generated by the DC/DC converters. A larger resistor than 10Ω should not be used because the current into Vcc of up to 2.5mA causes a voltage drop at the resistor causing the undervoltage lockout circuitry connected at Vcc internally to switch off too early. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 Submit Documentation Feedback 23 TPS650241-Q1 TPS650243-Q1 SLVS994 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com APPLICATION INFORMATION TYPICAL CONFIGURATION FOR THE TITAN 2 PROCESSOR The core voltage is generated using DCDC2 with the output voltage set to 1.2V using a resistor divider at DEFDCDC2 as only DCDC2 can support an output current of up to 1.6A. DCDC3 is used for the memory voltage of 1.8V. As DCDC3 does not support an external resistor divider, the output voltage is programmed to 1.6V by setting DEFDCDC3 = HIGH. In addition, there is a resistor at the input of the internal voltage divider at pin VDCDC3 which adds another 200mV. The internal resistance at VDCDC3 when programmed to 1.6V is 480kΩ, so the external resistance needed to increase the output voltage from 1.6V to 1.8V is 60kΩ (62kΩ). The typical configuration for the Titan 2 processor is shown in Figure 18. Vcc VIN Titan TPS650244 1mF VINDCDC1 VIN 10mF 3.3mH LPS3015 L1 VINDCDC2 VIN DCDC1 800mA 10mF VINDCDC3 VIN VDDIO (3.3V) 10mF VDCDC1 2.2mH LPS3015 L3 VDD _ MEM (1.8V) 10mF DCDC3 800mA DEFDCDC1 VIN DEFDCDC3 (set to1.8V) VIN DCDC2 1600mA VDCDC2 220kW 62kW 22mF VDCDC3 L2 2.2mH VLCF4020 core (1.2V) VDCDC2 22mF DEFDCDC2 LDO2 RTC I /O (3.3V) 220kW LDO2 200mA EN_DCDC1 2.2mF 130kW EN_DCDC2 LDO1 EN_DCDC3 VIN 300kW FB_LDO2 LDO1 200mA 100kW FB_LDO1 RTC core (1.2V) 2.2mF 510kW VINLDO1/2 1mF Vdd_alive 1.2V (not used) open EN_LDO1/2 VIO 1MW EN_VDDalive PWRFAIL_SNS Input Voltage TBD POWERFAIL + Figure 18. Titan Processor Configuration 24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650241-Q1 TPS650243-Q1 www.ti.com ......................................................................................................................................................................................... SLVS994 – SEPTEMBER 2009 TYPICAL CONFIGURATION FOR THE SAMSUNG PROCESSOR S3C6400-533MHz The typical configuration for the Samsung processor S3C6400-533MHz is shown in Figure 19. S3C6400533MHz Vcc VIN TPS650245 1m F VIN VDDMMC (3.3V) VINDCDC1 DCDC1 1000mA 10mF VIN VINDCDC2 10mF VIN VDDEXT (3.3V) 3.3mH L1 VDDHI (3.3V) 10mF L2 DCDC2 800mA VINDCDC3 VDDLCD (3.3V) VDDPCM (3.3V) VDCDC1 VDDSYS (3.3V) 2.2mH VDCDC2 VDD_MEM0 (1.8V) VDD_MEM1 (1.8V) 10mF 10mF DCDC3 800mA DEFDCDC1 VIN L3 10mF LDO2 300kW LDO2 200mA FB_LDO2 DEFDCDC3 VDDADC (3.3V) VDDDAC (3.3V) 2.2mF VDDOTG (3.3V) VDDUH (3.3V) 130kW LDO1 EN_DCDC1 LDO1 200mA EN_DCDC2 EN_DCDC3 VDDOTGI (1.1V) 33kW FB_LDO1 2.2mF 330kW VINLDO1/2 VIN VDDARM (0.9V/1.1V) VDCDC3 DEFDCDC2 0.9V/1.1V 2.2mH 1 mF Vdd_alive 1.1V VDDALIVE EN_LDO1/2 1mF VIO VIN EN_VDDalive VIN 1MW R2 PWRFAIL PWRFAIL_SNS - R3 1V + GND APLL (1.0V) 2.2mH EPLL (1.0V) MPLL (1.0V) VIN VIN 10mF AGND , PowerPAD VDDINT (1.0V) SW EN EN TPS62260 MODE FB 22pF GND 100kW 10mF 150kW Figure 19. Samsung Processor Configuration Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 Submit Documentation Feedback 25 PACKAGE OPTION ADDENDUM www.ti.com 5-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS650241QRHBRQ1 ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPS650243QRHBRQ1 ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. 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