TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com 5-CHANNEL POWER MGMT IC WITH TWO STEP DOWN CONVERTERS AND 3 LOW-INPUT VOLTAGE LDOs Check for Samples: TPS65053-Q1, TPS650531-Q1 , TPS650532-Q1 FEATURES 1 • • • 2 • • • • • Qualified for Automotive Applications Up To 95% Efficiency Output Current for DC/DC Converters: – TPS65053-Q1 : DCDC1 = 1 A; DCDC2 = 0.6 A – TPS650531-Q1 : DCDC1 = 1 A; DCDC2 = 1 A – TPS650532-Q1: DCDC1 = 1 A; DCDC2 = 1 A DC/DC Converters Externally Adjustable VIN Range for DC/DC Converters From 2.5 V to 6 V 2.25-MHz Fixed Frequency Operation Power Save Mode at Light Load Current 180° Out-of-Phase Operation • • • • • • • • Output Voltage Accuracy in PWM Mode ±1% Total Typical 32-μA Quiescent Current for Both DC/DC Converters 100% Duty Cycle for Lowest Dropout One General-Purpose 400-mA LDO Two General-Purpose 200-mA LDOs VIN Range for LDOs from 1.5 V to 6.5 V Output Voltage for LDO3: – TPS65053-Q1 : VLDO3 = 1.3 V – TPS650531-Q1 : VLDO3 = 1.2 V – TPS650532-Q1: VLDO3 = 1.5 V Available in a 4 mm x 4 mm 24-Pin QFN Package DESCRIPTION The TPS65053x are integrated Power Management ICs for applications powered by one Li-Ion or Li-Polymer cell, which require multiple power rails. The TPS65053x provide two highly efficient, 2.25MHz step-down converters targeted at providing the core voltage and I/O voltage in a processor based system. Both step-down converters enter a low power mode at light load for maximum efficiency across the widest possible range of load currents. For low noise applications the devices can be forced into fixed frequency PWM mode by pulling the MODE pin high. Both converters allow the use of small inductors and capacitors to achieve a small solution size. TPS65053-Q1 provides an output current of up to 1A on the DCDC1 converter and up to 0.6A on the DCDC2 converter. TPS650531-Q1 and TPS650532-Q1 provide up to 1A on both DCDC1 and DCDC2. The TPS65053x also integrate one 400mA LDO and two 200mA LDO voltage regulators, which can be turned on/off using separate enable pins on each LDO. Each LDO operates with an input voltage range between 1.5V and 6.5V allowing them to be supplied from one of the step-down converters or directly from the main battery. LDO1 and LDO2 are externally adjustable while LDO3 has a fixed output voltage of 1.3V on TPS65053-Q1 , 1.2V on TPS650531-Q1 and 1.5V on TPS650532-Q1. The TPS65053x come in a small 24-pin leadless package (4mm × 4mm QFN) with a 0,5mm pitch. ORDERING INFORMATION (1) TA PACKAGE –40°C to 85°C QFN - RGE (1) OUTPUT VOLTAGE ON LDO3 ORDERABLE PART NUMBER TOP-SIDE MARKING 1.3V TPS65053IRGERQ1 65053Q 1.2V TPS650531IRGERQ1 PREVIEW 1.5V TPS650532IRGERQ1 PREVIEW For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNITS –0.3 V to 7 V Input voltage range on all pins except AGND, PGND, and EN_LDO1 pins with respect to AGND VI –0.3 V to VCC + 0.5 V Input voltage range on EN_LDO1 pin with respect to AGND Current at VINDCDC1/2, L1, PGND1, L2, PGND2 II 1800 mA Current at all other pins 1000 mA –0.3 V to 4.0 V VO Output voltage range for LDO1, LDO2 and LDO3 TA Operating free-air temperature –40°C to 85°C Tstg Storage temperature range –65°C to 150°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS PACKAGE RGE (1) RθJA (1) TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING 2.8 W 28 mW/K 1.57 W 1.14 W 35 K/W The thermal resistance junction to case of the RGE package is 2 K/W measured on a high K board. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VINDCDC1/2 Input voltage range for step-down converters 2.5 6 V VDCDC1 Output voltage range for VDCDC1 step-down converter 0.6 VINDCDC1 V VDCDC2 Output voltage range for VDCDC2 step-down converter 0.6 VINDCDC2 V VINLDO1, VINLDO2/3 Input voltage range for LDOs 1.5 6.5 V VLDO1-2 Output voltage range for LDO1 and LDO2 3.6 V VLDO3 IOUTDCDC1 1.3 Output voltage for LDO3 on TPS650531-Q1 1.2 Output voltage for LDO3 on TPS650532-Q1 1.5 Output current at L1 V 1000 (1) L1 Inductor at L1 CINDCDC1/2 Input capacitor at VINDCDC1/2 COUTDCDC1 Output capacitor at VDCDC1 IOUTDCDC2 1 Output voltage for LDO3 on TPS65053-Q1 1.5 (1) 10 μF 600 Output current at L2 for TPS650531-Q1 , TPS650532-Q1 Inductor at L2 (1) COUTDCDC2 Output capacitor at VDCDC2 (1) (1) CVCC Input capacitor at VCC Cin1-2 Input capacitor at VINLDO1, VINLDO2/3 COUT1 Output capacitor at VLDO1 μF 22 Output current at L2 for TPS65053-Q1 L2 μH 2.2 22 (1) (1) (1) (1) mA mA 1000 1.5 2.2 μH 10 22 μF 1 μF 2.2 μF 4.7 μF μF COUT2-3 Output capacitor at VLDO2-3 ILDO1 Output current at VLDO1 400 mA ILDO2,3 Output current at VLDO2,3 200 mA (1) 2 2.2 See the Application Information section of this data sheet for more details. Copyright © 2011, Texas Instruments Incorporated TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS (continued) MIN NOM MAX UNIT TA Operating ambient temperature range –40 85 °C TJ Operating junction temperature range –40 125 °C RCC Resistor from battery voltage to VCC used for filtering (2) 10 Ω (2) 1 Up to 2 mA can flow into VCC when both converters are running in PWM, this resistor causes the UVLO threshold to be shifted accordingly. ELECTRICAL CHARACTERISTICS Vcc = VINDCDC1/2 = 3.6V, EN = Vcc, MODE = GND, L = 2.2μH, COUT = 22μF, TA = –40°C to 85°C typical values are at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT Vcc IQ IQ Input voltage range 2.5 Operating quiescent current Total current into VCC, VINDCDC1/2, VINLDO1, VINLDO2/3 Operating quiescent current into VCC 6 V 20 30 μA Two converters, IOUT = 0 mA, PFM mode enabled (Mode = 0) device not switching, EN_DCDC1 = Vin AND EN_DCDC2 = Vin; EN_LDO1 = EN_LDO2 = EN_LDO3 = GND 32 40 μA One converter, IOUT = 0 mA, PFM mode enabled (Mode = GND) device not switching, EN_DCDC1 = Vin OR EN_DCDC2 = Vin; EN_LDO1 = EN_LDO2 = EN_LDO3 = Vin 145 210 μA One converter, IOUT = 0 mA, Switching with no load (Mode = Vin), PWM operation EN_DCDC1 = Vin OR EN_DCDC2 = Vin; EN_LDO1 = EN_LDO2 = EN_LDO3 = GND 0.85 mA Two converters, IOUT = 0 mA, Switching with no load (Mode = Vin), PWM operation EN_DCDC1 = Vin AND EN_DCDC2 = Vin; EN_LDO1 = EN_LDO2 = EN_LDO3 = GND 1.25 mA One converter, IOUT = 0 mA.PFM mode enabled (Mode = GND) device not switching, EN_DCDC1 = Vin OR EN_DCDC2 = Vin; EN_LDO1= EN_LDO2 = EN_LDO3 = GND I(SD) Shutdown current EN_DCDC1 = EN_DCDC2 = GND EN_LDO1 = EN_LDO2 = EN_LDO3 = GND UVLO Undervoltage lockout threshold for DCDC converters and LDOs Voltage at VCC 9 12 μA 1.8 2 V EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3, MODE VIH High-level input voltage MODE, EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3 1.2 VCC V VIL Low-level input voltage MODE, EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3 0 0.4 V IIN Input bias current MODE, EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3, MODE = GND or VIN 0.01 1 μA VINDCDC1/2 = 3.6 V 280 630 VINDCDC1/2 = 2.5 V 400 POWER SWITCH rDS(on) P-channel MOSFET on resistance ILD_PMOS P-channel leakage current V(DS) = 6 V rDS(on) N-channel MOSFET on resistance VINDCDC1/2 = 3.6 V 220 VINDCDC1/2 = 2.5 V 320 ILK_NMOS N-channel leakage current DCDC1, DCDC2 DCDC1, DCDC2 V(DS) = 6 V DCDC1 I(LIMF) TSD Forward Current Limit DCDC2 PMOS (High-Side) (TPS65053-Q1 ) and NMOS (Low DCDC2 side) (TPS650531-Q1 , TPS650532-Q1) 1 450 7 10 1.1 1.4 1.8 0.85 1 1.15 2.5 V ≤ VIN ≤ 6 V mΩ μA mΩ μA A 1.19 1.4 1.65 Thermal shutdown Increasing junction temperature 150 °C Thermal shutdown hysteresis Decreasing junction temperature 20 °C Copyright © 2011, Texas Instruments Incorporated 3 TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Vcc = VINDCDC1/2 = 3.6V, EN = Vcc, MODE = GND, L = 2.2μH, COUT = 22μF, TA = –40°C to 85°C typical values are at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.025 2.25 2.475 MHz OSCILLATOR fSW Oscillator frequency OUTPUT VOUT Output voltage range Vref Reference voltage VOUT DC output voltage accuracy 0.6 VIN 600 DCDC1, DCDC2 (1) V mV VIN = 2.5 V to 6 V, Mode = GND, PFM operation, 0 mA < IOUT < IOUTMAX -2% 0 2% VIN = 2.5 V to 6 V, Mode = VIN, PWM operation, 0 mA < IOUT < IOUTMAX –1% 0 1% ΔVOUT Power save mode ripple voltage (2) IOUT = 1 mA, Mode = GND, VO = 1.3 V, Bandwidth = 20 MHz 25 mVPP tStart Start-up time Time from active EN to Start switching 170 μs tRamp VOUT Ramp up Time Time to ramp from 5% to 95% of VOUT 750 RESET delay time Input voltage at threshold pin rising RESET output low voltage IOL = 1 mA, Vthreshold < 1 V VOL 80 μs 120 0.2 RESET sink current Vth 100 1 RESET output leakage current Vthreshold > 1 V Threshold voltage falling voltage 1 V mA 10 0.98 ms nA 1.02 V VLDO1, VLDO2, VLDO3 LOW DROPOUT REGULATORS VINLDO Input voltage range for LDO1, LDO2, LDO3 1.5 6.5 V VLDO1 LDO1 output voltage range 1 3.6 V VLDO2 LDO2 output voltage range 1 3.6 V VLDO3 V(FB) LDO3 output voltage for TPS650531-Q1 1.2 LDO3 output voltage for TPS650532-Q1 1.5 V 400 Maximum output current for LDO2, LDO3 R(DIS) V 1 Maximum output current for LDO1 I(SC) 4 1.3 Feedback voltage for FB_LDO1, FB_LDO2 IO (1) (2) LDO3 output voltage for TPS65053-Q1 mA 200 mA LDO1 short-circuit current limit VLDO1 = GND 850 mA LDO2 & LDO3 short-circuit current limit VLDO2 = GND, VLDO3 = GND 420 mA Dropout voltage at LDO1 IO = 400 mA, VINLDO1 = 1.8 V 280 mV Dropout voltage at LDO2, LDO3 IO = 200 mA, VINLDO2/3 = 1.8 V 280 mV Output voltage accuracy for LDO1, LDO2, LDO3(1) IO = 10 mA –2% 1% Line regulation for LDO1, LDO2, LDO3 VINLDO1,2 = VLDO1,2 + 0.5 V (min. 2.5 V) to 6.5V, IO = 10 mA –1% 1% Load regulation for LDO1, LDO2, LDO3 IO = 0 mA to 400 mA for LDO1 IO = 0 mA to 200 mA for LDO2, LDO3 –1% 1% Regulation time for LDO1, LDO2, LDO3 Load change from 10% to 90% Internal discharge resistor at VLDO1, VLDO2, VLDO3 25 μs Active when LDO is disabled 350 Ω Thermal shutdown Increasing junction temperature 140 °C Thermal shutdown hysteresis Decreasing junction temperature 20 °C Output voltage specification does not include tolerance of external voltage programming resistors. In Power Save Mode, operation is typically entered at IPSM = VIN / 32 Ω. Copyright © 2011, Texas Instruments Incorporated TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com PIN ASSIGNMENTS PGND1 L1 VINDCDC1/2 L2 PGND2 FB_DCDC2 RGE PACKAGE (TOP VIEW) 18 17 16 15 14 13 FB_DCDC1 EN_DCDC1 EN_DCDC2 EN_LDO1 MODE AGND 12 11 10 9 8 7 19 20 21 22 23 24 EN_LDO3 EN_LDO2 RESET VLDO3 VINLDO2/3 VLDO2 Vcc VIN_LDO1 VLDO1 FB_LDO1 THRESH FB_LDO2 1 2 3 4 5 6 PIN FUNCTIONS PIN NAME NO. I/O DESCRIPTION VCC 1 I Power supply for digital and analog circuitry of DCDC1, DCDC2 and LDOs. This pin must be connected to the same voltage supply as VINDCDC1/2. FB_DCDC1 19 I Input to adjust output voltage of converter 1 between 0.6 V and VI. Connect external resistor divider between VOUT1, this pin and GND. MODE 23 I Select between Power Save Mode and forced PWM Mode for DCDC1 and DCDC2. In Power Save Mode, PFM is used at light loads, PWM for higher loads. If PIN is set to high level, forced PWM Mode is selected. If Pin has low level, then the device operates in Power Save Mode. VINDCDC1/2 16 I Input voltage for VDCDC1 and VDCDC2 step-down converter. This must be connected to the same voltage supply as VCC. FB_DCDC2 13 I Input to adjust output voltage of converter 2 between 0.6V and VIN. Connect external resistor divider between VOUT2, this pin and GND. L1 17 O Switch pin of converter 1. Connected to Inductor PGND1 18 I GND for converter 1 PGND2 14 I GND for converter 2 AGND 24 I Analog GND, connect to PGND and PowerPAD™ L2 15 O Switch Pin of converter 2. Connected to Inductor. EN_DCDC1 20 I Enable Input for converter 1, active high EN_DCDC2 21 I Enable Input for converter 2, active high VINLDO1 2 I Input voltage for LDO1 VINLDO2/3 8 I Input voltage for LDO2 and LDO3 VLDO1 3 O Output voltage of LDO1 VLDO2 7 O Output voltage of LDO2 VLDO3 9 O Output voltage of LDO3 FB_LDO1 4 1 Feedback input for the external voltage divider. FB_LDO2 6 I Feedback input for the external voltage divider. EN_LDO1 22 I Enable input for LDO1. Logic high enables the LDO, logic low disables the LDO. EN_LDO2 11 I Enable input for LDO2. Logic high enables the LDO, logic low disables the LDO. EN_LDO3 12 I Enable input for LDO3. Logic high enables the LDO, logic low disables the LDO. THRESHOLD 5 I Reset input RESET 10 O Open drain active low reset output, 100 ms reset delay time. PowerPAD™ – Connect to GND Copyright © 2011, Texas Instruments Incorporated 5 TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM TPS65053 VINDCDC1/2 1W VCC VIN 22 mF 1 mF 2.2 mH DCDC1 (I/O) ENABLE EN_DCDC1 STEP-DOWN CONVERTER L1 R1 FB_DCDC1 PGND1 10 mF Cff 10 mF R2 1000 mA MODE Cff 2.2 mH L2 DCDC2 (core) FB_DCDC2 EN_DCDC2 ENABLE VIN 2.2 mF ENABLE STEP-DOWN CONVERTER 600mA R4 PGND2 VLDO1 VIN_LDO1 EN_LDO1 R3 VLDO1 400 mA LDO FB1 R5 4.7 mF R6 VIN VIN_LDO2/3 VLDO2 2.2 mF ENABLE EN_LDO2 200 mA LDO VLDO2 FB2 R7 2.2 mF R8 ENABLE EN_LDO3 VLDO3 VLDO3 2.2 mF 200 mA LDO I/O voltage THRESHOLD Reset R19 RESET AGND 6 Copyright © 2011, Texas Instruments Incorporated TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS Table of Graphs FIGURE η Efficiency converter 1 vs Load current PWM/PFM mode 1 η Efficiency converter 1 vs Load current PWM mode 2 η Efficiency converter 2 vs Load current PWM/PFM mode 3 η Efficiency converter 2 vs Load current PWM mode 4 Output voltage ripple in PFM mode Scope plot 5 Output voltage ripple in PWM mode Scope plot 6 DCDC1, DCDC2, LDO1 startup timing Scope plot 7 LDO1 to LDO3 startup timing Scope plot 8 DCDC1 Load transient response in PWM mode Scope plot 9 DCDC1 Load transient response in PFM mode Scope plot 10 DCDC2 Load transient response in PWM mode Scope plot 11 DCDC2 Load transient response in PFM mode Scope plot 12 DCDC1 Line transient response in PWM mode Scope plot 13 DCDC2 Line transient response in PWM mode Scope plot 14 LDO1 Load transient response Scope plot 15 LDO3 Load transient response Scope plot 16 LDO1 Line transient response Scope plot 17 LDO1 Power supply rejection ratio vs frequency 18 EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 90 90 80 70 5V 60 4.2 V 50 3.8 V 70 Efficiency − % Efficiency − % 80 3.4 V 40 30 5V 50 3.4 V 40 4.2 V 30 VO = 3.3 V o TA = 25 C PWM/PFM Mode 20 10 0 0.0001 3.8 V 60 0.1 0.001 0.01 IO − Output Current − A Figure 1. Copyright © 2011, Texas Instruments Incorporated 1 VO = 3.3 V o TA = 25 C PWM Mode 20 10 10 0 0.0001 0.1 0.001 0.01 IO − Output Current − A 1 10 Figure 2. 7 TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 90 3.8 V 80 80 4.2 V 5V 50 40 30 VO = 1.3 V, TA = 25°C, PFM Mode 10 4.2 V 40 10 0 0.0001 1 0.001 0.01 0.1 IO - Output Current - A Figure 3. Figure 4. OUTPUT VOLTAGE RIPPLE PWM/PFM MODE = LOW OUTPUT VOLTAGE RIPPLE PWM MODE = HIGH 1 o VI = 4.2 V, TA = 25 C CH1 (VDCDC1 = 3.3 V) o VI = 4.2 V, TA = 25 C CH1 (VDCDC2 = 1.5 V) CH4 (IL DCDC1 = 600 mA) 200 mA/div 100 mA/div 20 mV/div CH1 (VDCDC1 = 3.3 V) 20 mV/div 20 mV/div 50 20 0.001 0.01 0.1 IO - Output Current - A CH2 (VDCDC2 = 1.5 V) CH3 (IL DCDC2 = 600 mA) CH4 (IL DCDC1 = 80 mA) t − Time = 2 ms/div Figure 5. 200 mA/div CH3 (IL DCDC2 = 80 mA) 8 3.8 V 30 20 0 0.0001 5V 60 20 mV/div 60 3.3 V 70 Efficiency - % Efficiency - % 70 VO = 1.3 V, TA = 25°C, PWM Mode 100 mA/div 90 100 3.3 V t − Time = 500 ns/div Figure 6. Copyright © 2011, Texas Instruments Incorporated TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) CH1: EN_DCDC1/2, ENLDO1, Load = 600 mA LDO1 TO LDO3 STARTUP TIMING 5 V/div DCDC1 STARTUP TIMING CH4 (ENLDO1,2,3) CH1 (VLDO1) CH4: VLDO1 TA = 25°C, VDCDC1 = 3.3 V, VDCDC2 = 1.5 V, Mode = low CH2 (VLDO2) 1 V/div VI = 3.6 V, 1 V/div CH3: VDCD2 CH3 (VLDO3) VI = 3.6 V TA = 25oC 1 V/div CH2: VDCDC1 ILDO1/2/3/ = 100 mA Mode = Low Figure 7. Figure 8. DCDC1 LOAD TRANSIENT RESPONSE DCDC1 LOAD TRANSIENT RESPONSE 50 mV/div 50 mV/div t − Time = 40 ms/div CH1 (VDCDC1) CH1 (VDCDC1) VI = 4.2 V o TA = 25 C VI = 4.2 V o TA = 25 C Mode = Low Mode = High CH2 I(DCDC1) VDCDC1 = 3.3 V ENDCDC1 = High ENDCDC2 = Low Load Current = 60 mA to 540 mA 200 mA/div 200 mA/div CH2 I(DCDC1) VDCDC1 = 3.3 V ENDCDC1 = High ENDCDC2 = Low Load Current = 60 mA to 540 mA t − Time = 100 ms/div t − Time = 100 ms/div Figure 9. Figure 10. Copyright © 2011, Texas Instruments Incorporated 9 TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) CH1 (VDCDC2) VI = 3.6 V TA = 25oC DCDC2 LOAD TRANSIENT RESPONSE 50 mV/div 50 mV/div DCDC2 LOAD TRANSIENT RESPONSE CH1 (VDCDC2) VI = 3.6 V o TA = 25 C Mode = High Mode = Low VDCDC2 = 1.5 V ENDCDC1 = Low ENDCDC2 = High Load Current = 60 mA to 540 mA t − Time = 100 ms/div t − Time = 100 ms/div Figure 11. Figure 12. DCDC1 LINE TRANSIENT RESPONSE DCDC2 LINE TRANSIENT RESPONSE CH1 VIN (VDCDC1) VI = 3.6 V to 4.5 V to 3.6 V o TA = 25 C Mode = High VDCDC1 = 3.3 V ENDCDC1 = High ENDCDC2 = Low Load Current = 600 mA CH1 VIN (VDCDC2) 20 mV/div 20 mV/div 200 mA/div VDCDC2 = 1.5 V ENDCDC1 = Low ENDCDC2 = High Load Current = 60 mA to 540 mA CH2 I(DCDC2) 500 mV/div 500 mV/div 200 mA/div CH2 I(DCDC2) CH2 (VDCDC1) CH2 (VDCDC2) VI = 3.4 V to 4.4 V to 3.4 V TA = 25oC Mode = High 10 VDCDC2 = 1.5 V ENDCDC1 = Low ENDCDC2 = High Load Current = 600 mA t − Time = 100 ms/div t − Time = 100 ms/div Figure 13. Figure 14. Copyright © 2011, Texas Instruments Incorporated TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) LDO3 LOAD TRANSIENT RESPONSE 50 mV/div 50 mV/div LDO1 LOAD TRANSIENT RESPONSE CH1 (VLDO1) CH1 (VLDO3) VI = 3.6 V o TA = 25 C VI = 3.6 V VLDO3 = 1.3 V I(LDO3) = 20 mA to 180 mA o TA = 25 C CH2 I(LDO1) 200 mA/div 200 mA/div VLDO1 = 3.3 V I(LDO1) = 40 mA to 360 mA CH2 I(LDO3) t − Time = 200 ms/div t − Time = 100 ms/div Figure 15. Figure 16. LDO1 LINE TRANSIENT RESPONSE LDO1 POWER SUPPLY REJECTION RATIO vs FREQUENCY 100 VIN = 3.8 V, VOUT = 3.3 V, IOUT = 10 mA, TA = 25°C, 90 80 Rejection Ratio - dB 20 mV/div 500 mV/div CH1 VIN (LDO1) CH2 (VLDO1) 50 40 30 20 VLDO1 = 3.3 V VLDO1 = 100 mA Mode = High 10 Figure 17. Copyright © 2011, Texas Instruments Incorporated COUT = 4.7 mF 60 VI = 3.6 V to 4.2 V to 3.6 V o TA = 25 C t − Time = 100 ms/div CIN = 2.2 mF, 70 0 10 100 1k 10 k 100 k f - Frequency - Hz 1M 10 M Figure 18. 11 TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com DETAILED DESCRIPTION OPERATION The TPS65053x include two synchronous step-down converters. The converters operate with 2.25MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents the converters automatically enter Power Save Mode and operate with PFM (Pulse Frequency Modulation). During PWM operation the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator will also turn off the switch in case the current limit of the P-channel switch is exceeded. After the adaptive dead time prevents shoot through current, the N-channel MOSFET rectifier is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off the N-channel rectifier and turning on the P-channel switch. The two DC-DC converters operate synchronized to each other, with converter 1 as the master. A 180° phase shift between Converter 1 and Converter 2 decreases the input RMS current. Therefore smaller input capacitors can be used. The converters output voltage is set by an external resistor divider connected to FB_DCDC1 or FB_DCDC2, respectively. See application section for more details. POWER SAVE MODE The Power Save Mode is enabled with Mode Pin set to low. If the load current decreases, the converters will enter Power Save Mode operation automatically. During Power Save Mode the converters operate with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. The converter will position the output voltage typically 1% above the nominal output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step. In order to optimize the converter efficiency at light load the average current is monitored and if in PWM mode the inductor current remains below a certain threshold, then Power Save Mode is entered. The typical threshold can be calculated according to: Equation 1: Average output current threshold to enter PFM mode. VINDCDC I PFM_enter + 32 W (1) Equation 2: Average output current threshold to leave PFM mode. VINDCDC I PFM_leave + 24 W (2) During the Power Save Mode the output voltage is monitored with a comparator. As the output voltage falls below the skip comparator threshold (skip comp) of VOUTnominal +1%, the P-channel switch will turn on and the converter effectively delivers a constant current as defined above. If the load is below the delivered current then the output voltage will rise until the same threshold is crossed again, whereupon all switching activity ceases, hence reducing the quiescent current to a minimum until the output voltage has dropped below the threshold again. If the load current is greater than the delivered current then the output voltage will fall until it crosses the skip comparator low (Skip Comp Low) threshold set to 1% below nominal Vout, whereupon Power Save Mode is exited and the converter returns to PWM mode. These control methods reduce the quiescent current typically to 12μA per converter and the switching frequency to a minimum thereby achieving the highest converter efficiency. The PFM mode operates with very low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor; increasing capacitor values will make the output ripple tend to zero. The Power Save Mode can be disabled by driving the MODE pin high. Both converters will operate in fixed PWM mode. Power Save Mode Enable/Disable applies to both converters. 12 Copyright © 2011, Texas Instruments Incorporated TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com Dynamic Voltage Positioning This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is activated in Power Save Mode operation when the converter runs in PFM Mode. It provides more headroom for both the voltage drop at a load step increase and the voltage increase at a load throw-off. This improves load transient behavior. At light loads, in which the converters operate in PFM Mode, the output voltage is regulated typically 1% higher than the nominal value. In case of a load transient from light load to heavy load, the output voltage will drop until it reaches the skip comparator low threshold set to –1% below the nominal value and enters PWM mode. During a load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation turning on the N-channel switch. Smooth increased load +1% PFM Mode light load Fast load transient PFM Mode light load VOUT_NOM PWM Mode medium/heavy load PWM Mode medium/heavy load -1% COMP_LOW threshold Figure 19. Dynamic Voltage Positioning Soft Start The two converters have an internal soft start circuit that limits the inrush current during start-up. During soft start, the output voltage ramp up is controlled as shown in Figure 20. EN 95% 5% VOUT tStart tRAMP Figure 20. Soft Start Copyright © 2011, Texas Instruments Incorporated 13 TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com 100% Duty Cycle Low Dropout Operation The converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range, i.e. The minimum input voltage to maintain regulation depends on the load current and output voltage and can be calculated as: Vin min + Vout max ) Iout max ǒRDSonmax ) R LǓ (3) with: Ioutmax = maximum output current plus inductor ripple current RDSonmax = maximum P-channel switch rDS(on) RL = DC resistance of the inductor Voutmax = nominal output voltage plus maximum output voltage tolerance With decreasing load current, the device automatically switches into pulse skipping operation in which the power stage operates intermittently based on load demand. By running cycles periodically the switching losses are minimized and the device runs with a minimum quiescent current maintaining high efficiency. In power save mode the converter only operates when the output voltage trips below its nominal output voltage. It ramps up the output voltage with several pulses and goes again into power save mode once the output voltage exceeds the nominal output voltage. Undervoltage Lockout The undervoltage lockout circuit prevents the device from malfunctioning by disabling the converter at low input voltages and from excessive discharge of the battery. The undervoltage lockout threshold is typically 1.8 V, max 2 V. MODE SELECTION The MODE pin allows mode selection between forced PWM Mode and power Save Mode for both converters. Connecting this pin to GND enables the automatic PWM and power save mode operation. The converters operate in fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, maintaining high efficiency over a wide load current range. Pulling the MODE pin high forces both converters to operate constantly in the PWM mode even at light load currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power save mode during light loads. For additional flexibility it is possible to switch from power save mode to forced PWM mode during operation. This allows efficient power management by adjusting the operation of the converter to the specific system requirements. ENABLE The devices have a separate enable pin for each of the dcdc converters and for each of the LDO to start up independently. If EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3 are set to high, the corresponding converter starts up with soft start as previously described. Pulling the enable pin low forces the device into shutdown, with a shutdown quiescent current as defined in the electrical characteristics. In this mode, the P and N-Channel MOSFETs are turned-off, the and the entire internal control circuitry is switched-off. If disabled, the outputs of the LDOs are pulled low by internal 350Ω resistors, actively discharging the output capacitor. For proper operation the enable pins must be terminated and must not be left unconnected. RESET The TPS65053x contain circuitry that can generate a reset pulse for a processor with a 100ms delay time. The input voltage at a comparator is sensed at an input called THRESHOLD. When the voltage exceeds the 1V threshold, the output goes high after a 100ms delay time. This circuitry is functional as soon as the supply voltage at Vcc exceeds the undervoltage lockout threshold. The RESET circuitry is active even if all DCDC converters and LDOs are disabled. 14 Copyright © 2011, Texas Instruments Incorporated TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com Vbat threshold Reset + - 100 ms delay Vref =1 V Vbat Threshold Comparator Output (Internal) Reset TNRESPWRON Figure 21. RESET Pulse Circuit SHORT-CIRCUIT PROTECTION All outputs are short circuit protected with a maximum output current as defined in the Electrical Characteristics. THERMAL SHUTDOWN As soon as the junction temperature, TJ, exceeds typically 150°C for the DCDC converters, the device goes into thermal shutdown. In this mode, the P and N-Channel MOSFETs are turned-off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdown for one of the DCDC converters will disable both converters simultaneously. The thermal shutdown temperature for the LDOs are set to typically 140°C. Therefore a LDO which may be used to power an external voltage will never heat up the chip high enough to turn off the DCDC converters. If one LDO exceeds the thermal shutdown temperature, all LDOs will turn off simultaneously. Low Dropout Voltage Regulators The low dropout voltage regulators are designed to be stable with low value ceramic input and output capacitors. They operate with input voltages down to 1.5V. The LDOs offer a maximum dropout voltage of 280mV at rated output current. Each LDO supports a current limit feature. The LDOs are enabled by the EN_LDO1, EN_LDO2, and EN_LDO3 pin. The output voltage of LDO1 and LDO2 is set using an external resistor divider whereas LDO3 has a fixed output voltage of 1.30 V for TPS65053-Q1 , 1.20V for TPS650531-Q1 and 1.50V for TPS650532-Q1. Copyright © 2011, Texas Instruments Incorporated 15 TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com APPLICATION INFORMATION TYPICAL APPLICATION CIRCUIT TPS 65053 VINDCDC1/2 1W Vbat Vbat VCC 2.2 mH 1 mF Vbat 22 mF L1 2.8 V DCDC1(I/O) EN_DCDC1 STEP- DOWN CONVERTER 1A MODE FB_DCDC1 R 1 PGND1 Cff 10 mF R2 2.2 mH L2 DCDC2(core) EN_DCDC2 VDCDC1 Vbat STEP- DOWN CONVERTER 600mA VIN_LDO1 VLDO1 EN_LDO1 400mA LDO FB_DCDC2 R 3 PGND2 10 mF R4 VLDO1 FB1 1.8 V Cff 1.6 V R5 4.7 mF R6 VIN_LDO2/3 VLDO2 EN_LDO2 200mA LDO VLDO2 FB2 3.3 V R7 2.2 mF R8 EN_LDO3 VLDO3 VLDO3 200mA LDO 2.2 mF I/O voltage VDCDC1 R9 THRESHOLD Reset RESET 1.3 V R19 R10 AGND Output Voltage Setting The output voltage of the DCDC converters can be set by an external resistor network and can be calculated to: V OUT + VREF Ǔ ǒ1 ) R1 R2 (4) with an internal reference voltage Vref, 0.6 V (typical). It is recommended to set the total resistance of R1 + R2 to less than 1MΩ. The resistor network connects to the input of the feedback amplifier; therefore, need some small feedforward capacitor in parallel to R1. A typical value of 47pF is sufficient. R1 + R2 16 ǒ V OUT VFB_DCDC1 Ǔ * R2 (5) Copyright © 2011, Texas Instruments Incorporated TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com Table 1. Typical Resistor Values OUTPUT VOLTAGE R1 R2 NOMINAL VOLTAGE TYPICAL CFF 3.3 V 680 kΩ 150 kΩ 3.32 V 47 pF 3.0 V 510 kΩ 130 kΩ 2.95 V 47 pF 2.85 V 560 kΩ 150 kΩ 2.84 V 47 pF 2.5 V 510 kΩ 160 kΩ 2.51 V 47 pF 1.8 V 300 kΩ 150 kΩ 1.80 V 47 pF 1.6 V 200 kΩ 120 kΩ 1.60 V 47 pF 1.5 V 300 kΩ 200 kΩ 1.50 V 47 pF 1.2 V 330 kΩ 330 kΩ 1.20 V 47 pF OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR) Inductor Selection The two converters operate typically with 2.2μH output inductor. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. For output voltages higher than 2.8V, an inductor value of 3.3μH minimum should be selected, otherwise the inductor current will ramp down too fast causing imprecise internal current measurement and therefore increased output voltage ripple under some operating conditions in PFM mode. The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the inductance will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance should be selected for highest efficiency. Equation 6 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 6. This is recommended because during heavy load transient the inductor current will rise above the calculated value. 1 * Vout DI Vin DI L + Vout I Lmax + I out max ) L 2 L ƒ (6) with: f = Switching Frequency (2.25-MHz typical) L = Inductor Value Δ IL = Peak-to-peak inductor ripple current ILmax = Maximum Inductor current The highest inductor current occurs at maximum Vin. Open core inductors have a soft saturation characteristic, and they can normally handle higher inductor currents versus a comparable shielded inductor. A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. It must be considered, that the core material from inductor to inductor differs and will have an impact on the efficiency especially at high switching frequencies. Refer to Table 2 and the typical applications for possible inductors. Table 2. Tested Inductors Inductor Type Inductor Value Supplier LPS3010 2.2 μH Coilcraft LPS3015 3.3 μH Coilcraft LPS4012 2.2 μH Coilcraft VLF4012 2.2 μH TDK Copyright © 2011, Texas Instruments Incorporated 17 TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com Output Capacitor Selection The advanced Fast Response voltage mode control scheme of the two converters allow the use of small ceramic capacitors with a typical value of 10μF, without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low ESR values result in lowest output voltage ripple and are therefore recommended. See the recommended components in Table 4. If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application requirements. Just for completeness, the RMS ripple current is calculated as: 1 * Vout 1 Vin I RMSCout + Vout L ƒ 2 Ǹ3 (7) At nominal load current, the inductive converters operate in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: 1 * Vout 1 Vin DVout + Vout ) ESR 8 Cout ƒ L ƒ (8) ǒ Ǔ Where the highest output voltage ripple occurs at the highest input voltage Vin. At light load currents, the converters operate in Power Save Mode and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage. Input Capacitor Selection Because of the nature of the buck converter, having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. The converters need a ceramic input capacitor of 10 μF. The input capacitor can be increased without any limit for better input voltage filtering. Table 3. Possible Capacitors For DCDC Converters And LDOs Capacitor Value Size Supplier Type 2.2 μF 0805 TDK C2012X5R0J226MT Ceramic 2.2 μF 0805 Taiyo Yuden JMK212BJ226MG Ceramic 10 μF 0805 Taiyo Yuden JMK212BJ106M Ceramic 10 μF 0805 TDK C2012X5R0J106M Ceramic Low Drop Out Voltage Regulators (LDOs) The output voltage of LDO1 and LDO2 can be set by an external resistor network and can be calculated to: V OUT + VREF Ǔ ǒ1 ) R5 R6 (9) with an internal reference voltage, VREF, typical 1 V. It is recommended to set the total resistance of R5 + R6 to less than 1MΩ. Typically, there is no feedforward capacitor needed at the voltage dividers for the LDOs. V OUT + VFB_LDOx 18 R5 ) R6 R6 R5 + R6 ǒ VOUT VFB_LDOx Ǔ * R6 (10) Copyright © 2011, Texas Instruments Incorporated TPS65053-Q1 TPS650531-Q1 TPS650532-Q1 SLVSAW1 – JUNE 2011 www.ti.com Table 4. Typical Resistor Values OUTPUT VOLTAGE R5 R6 NOMINAL VOLTAGE 3.3 V 300 kΩ 130 kΩ 3.31 V 3V 300 kΩ 150 kΩ 3.00 V 2.85 V 240 kΩ 130 kΩ 2.85 V 2.80 V 360 kΩ 200 kΩ 2.80 V 2.5 V 300 kΩ 200 kΩ 2.50 V 1.8 V 240 kΩ 300 kΩ 1.80 V 1.5 V 150 kΩ 300 kΩ 1.50 V 1.3 V 36 kΩ 120 kΩ 1.30 V 1.2 V 100 kΩ 510 kΩ 1.19 V 1.1 V 33 kΩ 330 kΩ 1.1 V Input Capacitor and Output Capacitor Selection for the LDOs The minimum input capacitor on VIN_LDO1 and on VIN_LDO2/3 is 2.2 μF minimum. LDO1 is designed to be stable with an output capacitor of 4.7 μF minimum; whereas, LDO2 and LDO3 are stable with a minimum capacitor value of 2.2 μF. Copyright © 2011, Texas Instruments Incorporated 19 PACKAGE OPTION ADDENDUM www.ti.com 5-Jul-2012 PACKAGING INFORMATION Orderable Device TPS65053IRGERQ1 Status (1) Package Type Package Drawing ACTIVE VQFN RGE Pins Package Qty 24 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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