CSP-6 TPS62619, TPS62612 TPS62615, TPS62616 www.ti.com SLVS936 – NOVEMBER 2009 350-mA, 6-MHz HIGH-EFFICIENCY STEP-DOWN CONVERTER IN LOW PROFILE CHIP SCALE PACKAGING (HEIGHT < 0.4mm) Check for Samples: TPS62619 TPS62612 TPS62615 TPS62616 FEATURES 1 • • • • 90% Efficiency at 6MHz Operation 31μA Quiescent Current Wide VIN Range From 2.3V to 5.5V 6MHz Regulated Frequency Operation Best in Class Load and Line Transient ±2% Total DC Voltage Accuracy Automatic PFM/PWM Mode Switching Low Ripple Light-Load PFM Mode >50dB VIN PSRR (1kHz to 10kHz) Internal Soft-Start, 100-μs Start-Up Time Integrated Active Power-Down Sequencing (Optional) Three Surface-Mount External Components Required (One 0603 MLCC Inductor, Two 0402 Ceramic Capacitors) Complete Sub 0.4-mm Component Profile Solution Total Solution Size <10 mm2 Available in a 6-Pin NanoFree™ (CSP) Ultra-Thin Packaging APPLICATIONS • • • • Cell Phones, Smart-Phones WLAN, GPS and Bluetooth™ Applications DTV Tuner Applications DC/DC Micro Modules l l DESCRIPTION The TPS6261x device is a high-frequency synchronous step-down dc-dc converter optimized for battery-powered portable applications. Intended for low-power applications, the TPS6261x supports up to 350-mA load current, and allows the use of low cost chip inductor and capacitors. With a wide input voltage range of 2.3V to 5.5V, the device supports applications powered by Li-Ion batteries with extended voltage range. Different fixed voltage output versions are available from 1.2V to 2.3V. The TPS6261x operates at a regulated 6-MHz switching frequency and enters the power-save mode operation at light load currents to maintain high efficiency over the entire load current range. The PFM mode extends the battery life by reducing the quiescent current to 31μA (typ) during light load operation. For low-frequency noise-sensitive applications, the device can be forced into fixed frequency PWM mode by pulling the MODE pin high. These features, combined with high PSRR and AC load regulation performance, make this device suitable to replace a linear regulator to obtain better power conversion efficiency. The TPS6261x is available in an 6-pin thin chip-scale package (CSP, 0.4mm max. height). 100 90 VIN L SW VOUT 1.8 V @ 350mA 0.47 mH Efficiency - % TPS6261x 60 CI EN FB 2.2 mF GND Efficiency PFM/PWM Operation 180 140 120 100 50 80 40 30 200 160 80 70 VBAT 2.9 V .. 5.5 V VI = 3.6 V, VO = 1.8 V Power Loss PFM/PWM Operation 60 CO 20 40 4.7 mF 10 20 MODE Figure 1. Smallest Solution Size Application 0 0.1 1 10 100 IO - Load Current - mA Power Loss - mW • • • • • • • • • • • 23 0 1000 Figure 2. Efficiency vs. Load Current 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. Bluetooth is a trademark of Bluetooth SIG, Inc. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TPS62619, TPS62612 TPS62615, TPS62616 SLVS936 – NOVEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) TA -40°C to 85°C (1) (2) (3) (4) DEVICE SPECIFIC FEATURE PACKAGE MARKING CHIP CODE PART NUMBER OUTPUT VOLTAGE TPS62619 (4) 1.8V TPS62619YFD TPS62612 (4) 1.5V TPS62612YFD NA TPS62615 1.2V TPS62615YFD NC TPS62616 (4) 2.15V TPS62616YFD TPS62617 (4) 1.3V TPS62617YFD ORDERING (2) (3) GD For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. The YFD package is available in tape and reel. Add a R suffix (e.g. TPS62619YFDR) to order quantities of 3000 parts. Add a T suffix (e.g. TPS62619YFDT) to order quantities of 250 parts. Internal tap points are available to facilitate output voltages in 25mV increments. Product preview. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Voltage at VIN, SW (2) –0.3 V to 7 V Voltage at FB (2) VI –0.3 V to 3.6 V Voltage at EN, MODE IO (2) –0.3 V to VI + 0.3 V Peak output current 350 mA Power dissipation Internally limited TA Operating temperature range (3) TJ (max) Maximum operating junction temperature Tstg Storage temperature range ESD rating (4) –40°C to 85°C 150°C –65°C to 150°C Human body model 2 kV Charge device model 1 kV Machine model (1) (2) (3) (4) 200 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA(max)= TJ(max)–(θJA X PD(max)). To achieve optimum performance, it is recommended to operate the device with a maximum junction temperature of 105°C. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF capacitor discharged directly into each pin. DISSIPATION RATINGS (1) PACKAGE YFD-6 (1) (2) 2 RθJA (2) 125°C/W RθJB (2) 53°C/W POWER RATING TA ≤ 25°C DERATING FACTOR ABOVE TA = 25°C 800mW 8mW/°C Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = [TJ(max)–TA] / θJA. This thermal data is measured with high-K board (4 layers board according to JESD51-7 JEDEC standard). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 TPS62619, TPS62612 TPS62615, TPS62616 www.ti.com SLVS936 – NOVEMBER 2009 ELECTRICAL CHARACTERISTICS Minimum and maximum values are at VI = 2.3V to 5.5V, VO = 1.8V, EN = 1.8V, AUTO mode and TA = –40°C to 85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VI = 3.6V, VO = 1.8V, EN = 1.8V, AUTO mode and TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VI Input voltage range 2.3 IQ Operating quiescent current I(SD) Shutdown current UVLO Undervoltage lockout threshold 5.5 V 55 μA IO = 0mA. Device not switching 31 IO = 0mA, PWM mode 6.6 EN = GND 0.2 1 μA 2.05 2.1 V mA ENABLE, MODE VIH High-level input voltage VIL Low-level input voltage Ilkg Input leakage current 1.0 V 0.4 V 1 μA Input connected to GND or VIN 0.01 VI = V(GS) = 3.6V. PWM mode 480 mΩ VI = V(GS) = 2.5V. PWM mode 640 mΩ VI = V(GS) = 3.6V. PWM mode 270 mΩ VI = V(GS) = 2.5V. PWM mode 350 POWER SWITCH rDS(on) P-channel MOSFET on resistance TPS62612 TPS62615 TPS62617 TPS62619 TPS62616 Ilkg P-channel leakage current, PMOS V(DS) = 5.5V, -40°C ≤ TJ ≤ 85°C rDS(on) N-channel MOSFET on resistance VI = V(GS) = 3.6V. PWM mode 140 VI = V(GS) = 2.5V. PWM mode 200 Ilkg N-channel leakage current, NMOS rDIS Discharge resistor for power-down sequence TPS6261x V(DS) = 5.5V, -40°C ≤ TJ ≤ 85°C 2.3V ≤ VI ≤ 4.8V. Open loop P-MOS current limit mΩ 1 850 Thermal shutdown Thermal shutdown hysteresis μA mΩ mΩ 1 μA 15 50 Ω 1100 1200 mA 140 °C 10 °C OSCILLATOR fSW Oscillator frequency TPS6261x IO = 0mA. PWM mode 5.4 6 6.6 MHz 2.3V ≤ VI ≤ 2.5V, 0mA ≤ IO ≤ 200 mA 2.5V ≤ VI ≤ 2.9V, 0mA ≤ IO ≤ 300 mA 2.9V ≤ VI ≤ 4.8V, 0mA ≤ IO ≤ 350 mA PFM/PWM operation 0.98×VNOM VNOM 1.03×VNOM V 2.9V ≤ VI ≤ 5.5V, 0mA ≤ IO ≤ 350 mA PFM/PWM operation 0.98×VNOM VNOM 1.04×VNOM V 2.3V ≤ VI ≤ 2.5V, 0mA ≤ IO ≤ 200 mA 2.5V ≤ VI ≤ 2.9V, 0mA ≤ IO ≤ 300 mA 2.9V ≤ VI ≤ 4.8V, 0mA ≤ IO ≤ 350 mA PWM operation 0.98×VNOM VNOM 1.02×VNOM V OUTPUT Regulated DC output voltage V(OUT) TPS62612 TPS62615 TPS62617 TPS62619 Line regulation VI = VO + 0.5V (min 2.3V) to 5.5V, IO = 200 mA Load regulation IO = 0mA to 350 mA 0.13 –0.0002 Feedback input resistance %/V %/mA 480 kΩ TPS62619 IO = 1mA 18 mVPP ΔVO Power-save mode ripple voltage TPS62615 IO = 1mA 22 mVPP PSRR Power Supply Rejection Ratio TPS62619 f = 10kHz, IO = 150mA. PWM mode 50 dB Start-up time TPS62619 IO = 0mA, Time from active EN to VO 96 μs Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 3 TPS62619, TPS62612 TPS62615, TPS62616 SLVS936 – NOVEMBER 2009 www.ti.com PIN ASSIGNMENTS TPS6261x CSP-6 (TOP VIEW) TPS6261x CSP-6 (BOTTOM VIEW) MODE A1 A2 VIN VIN A2 SW B1 B2 EN EN C2 GND GND FB C1 A1 MODE B2 B1 SW C2 C1 FB TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. FB C1 I Output feedback sense input. Connect FB to the converter’s output. VIN A2 I Power supply input. SW B1 I/O EN B2 I This is the switch pin of the converter and is connected to the drain of the internal Power MOSFETs. This is the enable pin of the device. Connecting this pin to ground forces the device into shutdown mode. Pulling this pin to VI enables the device. This pin must not be left floating and must be terminated. This is the mode selection pin of the device. This pin must not be left floating and must be terminated. MODE A1 I GND C2 – MODE = LOW: The device is operating in regulated frequency pulse width modulation mode (PWM) at high-load currents and in pulse frequency modulation mode (PFM) at light load currents. MODE = HIGH: Low-noise mode enabled, regulated frequency PWM operation forced. Ground pin. FUNCTIONAL BLOCK DIAGRAM MODE VIN Undervoltage Lockout Bias Supply Bandgap EN Soft-Start V REF = 0.8 V Negative Inductor Current Detect Power Save Mode Switching Logic Thermal Shutdown VIN Current Limit Detect Frequency Control R1 FB Gate Driver R2 SW Anti Shoot-Through VREF + GND 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 TPS62619, TPS62612 TPS62615, TPS62616 www.ti.com SLVS936 – NOVEMBER 2009 PARAMETER MEASUREMENT INFORMATION TPS6261x VI CI L VIN SW EN FB VO CO GND MODE List of components: • L = MURATA LQM21PN1R0MC0 • CI = MURATA GRM155R60J475M (4.7μF, 6.3V, 0402, X5R) • CO = MURATA GRM155R60J475M (4.7μF, 6.3V, 0402, X5R) Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 5 TPS62619, TPS62612 TPS62615, TPS62616 SLVS936 – NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS Table of Graphs FIGURE η Efficiency Peak-to-peak output ripple voltage vs Load current 3, 4, 5 vs Input voltage 6 vs Load current 7, 8 Combined line/load transient response 9, 10 11, 12, 13, 14, 15, 16, 17 Load transient response AC load transient response VO IQ fs rDS(on) 18 DC output voltage vs Load current 19, 20 PFM/PWM boundaries vs Input voltage 21 Quiescent current vs Input voltage 22 PWM switching frequency vs Input voltage 23 PFM switching frequency vs Load current 24 P-channel MOSFET rDS(on) vs Input voltage 25 N-channel MOSFET rDS(on) vs Input voltage 26 PWM operation 27 Power-save mode operation 28 Mode change response 29, 30 Start-up PSRR 31 Power supply rejection ratio vs. Frequency 32 Spurious output noise (PFM mode) vs. Frequency 33 Spurious output noise (PWM mode) vs. Frequency 34 EFFICIENCY vs LOAD CURRENT 100 EFFICIENCY vs LOAD CURRENT 100 VI = 2.7 V PFM/PWM Operation VO = 1.8 V 90 VO = 1.2 V 80 80 50 VI = 4.2 V PFM/PWM Operation 40 VI = 3.6 V Forced PWM Operation 60 VI = 3.6 V PFM/PWM Operation 50 40 30 30 20 20 10 10 0 0.1 1 10 100 IO - Load Current - mA Figure 3. 6 Efficiency - % 60 70 VI = 3.6 V PFM/PWM Operation VI = 4.2 V PFM/PWM Operation VI = 3.6 V Forced PWM Operation 0 Efficiency - % 70 VI = 2.7 V PFM/PWM Operation 90 Submit Documentation Feedback 1000 0.1 1 10 100 IO - Load Current - mA 1000 Figure 4. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 TPS62619, TPS62612 TPS62615, TPS62616 www.ti.com SLVS936 – NOVEMBER 2009 EFFICIENCY vs LOAD CURRENT 91 90 100 96 L = muRata LQM21PN1R0MC0 88 94 92 86 90 Efficiency - % 87 85 84 83 82 81 86 IO = 10 mA 84 82 78 79 IO = 1 mA 76 VI = 3.6 V VO = 1.8 V PFM/PWM Operation 78 77 76 100 10 IO - Load Current - mA 1 74 72 70 2.3 1000 2.7 3.1 3.5 3.9 4.3 4.7 VI - Input Voltage - V 5.1 Figure 5. Figure 6. PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE vs LOAD CURRENT PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE vs LOAD CURRENT 26 5.5 20 VO = 1.8 V 24 VO - Peak-to-Peak Output ripple Voltage - mV VO - Peak-to-Peak Output Ripple Voltage - mV IO = 100 mA 88 80 L = muRata LQM18PN1R5-B35 80 22 VI = 4.2 V 20 18 VI = 3.6 V 16 VI = 2.9 V 14 12 10 8 6 4 2 0 VO = 1.8 V PFM/PWM Operation 98 L = muRata LQM21PN1R0NGR 89 Efficiency - % EFFICIENCY vs INPUT VOLTAGE 16 50 100 150 200 250 IO - Load Current - mA Figure 7. Copyright © 2009, Texas Instruments Incorporated 300 350 VI = 4.8 V 14 VI = 3.6 V 12 10 VI = 2.5 V 8 6 4 2 0 0 VO = 1.8 V L = muRata LQM21PN1R5MC0 18 0 50 100 150 200 250 IO - Load Current - mA 300 350 Figure 8. Submit Documentation Feedback Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 7 TPS62619, TPS62612 TPS62615, TPS62616 SLVS936 – NOVEMBER 2009 www.ti.com 3.3 to 3.9 V Line Step VI = 3.6 V, VO = 1.8 V MODE = Low 2.7 to 3.3 V Line Step VI = 3.6 V, VO = 1.8 V MODE = Low t - Time - 10 ms/div LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION VO - 20 mV/div - 1.8 V Offset Figure 10. IO - 100 mA/div Figure 9. 0 to 50 mA Load Step VI = 3.6 V, VO = 1.8 V MODE = Low IO - 100 mA/div 30 to 150 mA Load Step 30 to 150 mA Load Step IL - 200 mA/div VO - 10 mV/div - 1.8 V Offset IO - 50 mA/div t - Time - 10 µs/div VI - 500 mV/div - 2.7 V Offset VO - 20 mV/div - 1.8 V Offset 30 to 150 mA Load Step COMBINED LINE/LOAD TRANSIENT RESPONSE IO - 100 mA/div VI - 500 mV/div - 3.3 V Offset V - 20 mV/div - 1.8 V Offset O COMBINED LINE/LOAD TRANSIENT RESPONSE VI = 3.6 V, VO = 1.8 V MODE = Low t - Time - 5 µs/div t - Time - 2 ms/div Figure 11. 8 Submit Documentation Feedback Figure 12. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 TPS62619, TPS62612 TPS62615, TPS62616 www.ti.com SLVS936 – NOVEMBER 2009 MODE = Low VO - 20 mV/div - 1.8 V Offset IO - 100 mA/div IL - 200 mA/div VO - 20 mV/div - 1.8 V Offset 30 to 150 mA Load Step VI = 2.7 V, VO = 1.8 V LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION 30 to 150 mA Load Step VI = 4.8 V, VO = 1.8 V MODE = Low Figure 14. LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION 50 to 350 mA Load Step VI = 3.6 V, VO = 1.8 V MODE = Low t - Time - 5 µs/div Figure 15. Copyright © 2009, Texas Instruments Incorporated VO - 20 mV/div - 1.8 V Offset Figure 13. IO - 200 mA/div t - Time - 5 µs/div VO - 20 mV/div - 1.8 V Offset t - Time - 5 µs/div IL - 200 mA/div IL - 200 mA/div IO - 200 mA/div IL - 200 mA/div IO - 100 mA/div LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION 50 to 350 mA Load Step VI = 2.9 V, VO = 1.8 V MODE = Low t - Time - 5 µs/div Figure 16. Submit Documentation Feedback Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 9 TPS62619, TPS62612 TPS62615, TPS62616 SLVS936 – NOVEMBER 2009 www.ti.com VI = 4.8 V, VO = 1.8 V MODE = Low 5 to 300 mA Load Sweep MODE = Low t - Time - 10 µs/div t - Time - 5 µs/div 1.836 Figure 17. Figure 18. DC OUTPUT VOLTAGE vs LOAD CURRENT DC OUTPUT VOLTAGE vs LOAD CURRENT 1.224 VO = 1.8 V VO = 1.2 V PFM/PWM Operation VI = 3.6 V PFM/PWM Operation 1.8 VI = 3.6 V, PWM Operation VI = 2.5 V 1.782 1.764 0.1 1 10 100 IO - Load Current - mA Figure 19. 10 VO - DC Output Voltage - V VO - DC Output Voltage - V VI = 4.8 V 1.818 VO - 20 mV/div - 1.8 V Offset VI = 3.6 V, VO = 1.8 V IL - 200 mA/div IO - 200 mA/div 50 to 350 mA Load Step IL - 200 mA/div AC LOAD TRANSIENT RESPONSE VO - 20 mV/div - 1.8 V Offset IO - 200 mA/div LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION Submit Documentation Feedback 1000 VI = 3.6 V 1.212 1.2 VI = 4.8 V VI = 2.5 V VI = 3.6 V, PWM Operation 1.188 1.176 0.1 1 10 100 IO - Load Current - mA 1000 Figure 20. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 TPS62619, TPS62612 TPS62615, TPS62616 www.ti.com SLVS936 – NOVEMBER 2009 QUIESCENT CURRENT vs INPUT VOLTAGE PFM/PWM BOUNDARIES 200 50 VO = 1.8 V TA = 85°C 45 160 40 140 PFM to PWM Mode Change 120 100 The Switching Mode Changes at These Borders 80 60 IQ - Quiescent Current - mA IO - Load Current - mA 180 Always PWM 40 TA = 25°C 35 30 25 TA = -40°C 20 15 10 PWM to PFM Mode Change 20 Always PFM 5 0 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.8 VI - Input Voltage - V 0 2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 VI - Input Voltage - V Figure 21. Figure 22. PWM SWITCHING FREQUENCY vs INPUT VOLTAGE PFM SWITCHING FREQUENCY vs LOAD CURRENT 6.5 6.5 IO = 10 mA 5.2 5.5 VO = 1.8 V PFM/PWM Operation 6 6 4.9 5 4.5 IO = 300 mA IO = 200 mA fs - Switching Frequency - MHz fs - Switching Frequency - MHz 5.5 5.5 IO = 150 mA IO = 100 mA IO = 50 mA 4 3.5 3 2.5 5 VI = 2.5 V 4.5 4 VI = 3.6 V 3.5 VI = 4.8 V 3 2.5 2 1.5 1 VO = 1.8V 2 1.5 0.5 0 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 VI - Input Voltage - V Figure 23. Copyright © 2009, Texas Instruments Incorporated 0 20 40 60 80 100 120 140 160 180 200 IO - Load Current - mA Figure 24. Submit Documentation Feedback Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 11 TPS62619, TPS62612 TPS62615, TPS62616 SLVS936 – NOVEMBER 2009 www.ti.com 750 700 TPS62619 PWM Mode Operation TA = 85°C 650 TA = 25°C 600 550 TA = -40°C 500 450 400 350 300 250 200 150 100 300 TPS62619 PWM Mode Operation 275 250 225 TA = 85°C 200 TA = 25°C 175 TA = -40°C 150 125 100 75 50 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 Figure 26. PWM OPERATION POWER-SAVE MODE OPERATION SW Node - 2 V/div VI = 3.6 V, VO = 1.8 V, IO = 150 mA MODE = High Figure 27. Submit Documentation Feedback VO - 10 mV/div - 1.8 V Offset Figure 25. t - Time - 50 ns/div 12 VI - Input Voltage - V IL - 200 mA/div IL - 200 mA/div VO - 10 mV/div - 1.8 V Offset VI - Input Voltage - V VI = 3.6 V, VO = 1.8 V, IO = 40 mA SW Node - 2 V/div 900 850 800 N-CHANNEL rDS(ON) vs INPUT VOLTAGE rDS(on) - Static Drain-Source On-Resistance - mW rDS(on) - Static Drain-Source On-Resistance - mW P-CHANNEL rDS(ON) vs INPUT VOLTAGE MODE = Low t - Time - 250 ns/div Figure 28. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 TPS62619, TPS62612 TPS62615, TPS62616 www.ti.com SLVS936 – NOVEMBER 2009 VO - 10 mV/div - 1.8 V Offset MODE - 2 V/div IL - 200 mA/div t - Time - 1 µs/div Figure 29. Figure 30. START-UP POWER SUPPLY REJECTION RATIO vs FREQUENCY 60 PSRR - Power Supply Rejection Ratio - dB IL - 200 mA/div VI = 3.6 V, VO = 1.8 V, IO = 40 mA t - Time - 1 µs/div VI = 3.6 V, VO = 1.8 V, IO = 0 mA VO - 1 V/div EN - 2 V/div IL - 200 mA/div VI = 3.6 V, VO = 1.8 V, IO = 40 mA MODE CHANGE RESPONSE VO - 10 mV/div - 1.8 V Offset MODE - 2 V/div MODE CHANGE RESPONSE MODE = Low t - Time - 20 µs/div Figure 31. Copyright © 2009, Texas Instruments Incorporated VI = 3.6 V, VO = 1.8 V 55 50 45 IO = 150 mA 40 35 30 25 20 15 10 5 0 0.1 PFM/PWM Operation 1 10 100 f - Frequency - kHz 1000 10000 Figure 32. Submit Documentation Feedback Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 13 TPS62619, TPS62612 TPS62615, TPS62616 SLVS936 – NOVEMBER 2009 www.ti.com SPURIOUS OUTPUT NOISE (PFM MODE) vs FREQUENCY SPURIOUS OUTPUT NOISE (PWM MODE) vs FREQUENCY 1m VO = 1.8 V RL = 100 Ω VI = 3.6 V 800 m VI = 4.2 V 700 m 600 m 500 m 400 m 300 m 200 m 100 m 10 n 0 Span = 1 MHz f - Frequency - MHz Figure 33. 14 Spurious Output Noise (PWM Mode) - V Spurious Output Noise (PFM Mode) - V 900 m 500 m VI = 2.7 V Submit Documentation Feedback 10 450 m VO = 1.8 V RL = 12 Ω 400 m 350 m 300 m 250 m VI = 2.7 V VI = 3.6 V 200 m 150 m VI = 4.2 V 100 m 50 m 5n 0 Span = 4 MHz f - Frequency - MHz 40 Figure 34. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 TPS62619, TPS62612 TPS62615, TPS62616 www.ti.com SLVS936 – NOVEMBER 2009 DETAILED DESCRIPTION OPERATION The TPS6261x is a synchronous step-down converter typically operates at a regulated 6-MHz frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6261x converter operates in power-save mode with pulse frequency modulation (PFM). The converter uses a unique frequency locked ring oscillating modulator to achieve best-in-class load and line response and allows the use of tiny inductors and small ceramic input and output capacitors. At the beginning of each switching cycle, the P-channel MOSFET switch is turned on and the inductor current ramps up rising the output voltage until the main comparator trips, then the control logic turns off the switch. One key advantage of the non-linear architecture is that there is no traditional feed-back loop. The loop response to change in VO is essentially instantaneous, which explains the transient response. The absence of a traditional, high-gain compensated linear loop means that the TPS6261x is inherently stable over a range of L and CO. Although this type of operation normally results in a switching frequency that varies with input voltage and load current, an internal frequency lock loop (FLL) holds the switching frequency constant over a large range of operating conditions. Combined with best in class load and line transient response characteristics, the low quiescent current of the device (ca. 31μA) allows to maintain high efficiency at light load, while preserving fast transient response for applications requiring tight output regulation. Using the YFD package allows for a low profile solution size (0.4mm max height, including external components). The recommended external components are stated within the application information. The maximum output current is 350mA when these specific low profile external components are used. SWITCHING FREQUENCY The magnitude of the internal ramp, which is generated from the duty cycle, reduces for duty cycles either set of 50%. Thus, there is less overdrive on the main comparator inputs which tends to slow the conversion down. The intrinsic maximum operating frequency of the converter is about 10MHz to 12MHz, which is controlled to circa. 6MHz by a frequency locked loop. When high or low duty cycles are encountered, the loop runs out of range and the conversion frequency falls below 6MHz. The tendency is for the converter to operate more towards a "constant inductor peak current" rather than a "constant frequency". In addition to this behavior which is observed at high duty cycles, it is also noted at low duty cycles. When the converter is required to operate towards the 6MHz nominal at extreme duty cycles, the application can be assisted by decreasing the ratio of inductance (L) to the output capacitor's equivalent serial inductance (ESL). This increases the ESL step seen at the main comparator's feed-back input thus decreasing its propagation delay, hence increasing the switching frequency. POWER-SAVE MODE If the load current decreases, the converter will enter Power Save Mode operation automatically. During power-save mode the converter operates in discontinuous current (DCM) single-pulse PFM mode, which produces low output ripple compared with other PFM architectures. When in power-save mode, the converter resumes its operation when the output voltage trips below the nominal voltage. It ramps up the output voltage with a minimum of one pulse and goes into power-save mode when the inductor current has returned to a zero steady state. The PFM on-time varies inversely proportional to the input voltage and proportional to the output voltage giving the regulated switching frequency when in steady-state. PFM mode is left and PWM operation is entered as the output current can no longer be supported in PFM mode. As a consequence, the DC output voltage is typically positioned ca. 0.5% above the nominal output voltage and the transition between PFM and PWM is seamless. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 15 TPS62619, TPS62612 TPS62615, TPS62616 SLVS936 – NOVEMBER 2009 www.ti.com PFM Mode at Light Load PFM Ripple Nominal DC Output Voltage PWM Mode at Heavy Load Figure 35. Operation in PFM Mode and Transfer to PWM Mode MODE SELECTION The MODE pin allows to select the operating mode of the device. Connecting this pin to GND enables the automatic PWM and power-save mode operation. The converter operates in regulated frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, which maintains high efficiency over a wide load current range. Pulling the MODE pin high forces the converter to operate in the PWM mode even at light load currents. The advantage is that the converter operates with a fixed frequency that allows simple filtering of the switching frequency for low frequency noise-sensitive applications. In this mode, the efficiency is lower compared to the power-save mode during light loads. For additional flexibility, it is possible to switch from power-save mode to forced PWM mode during operation. This allows efficient power management by adjusting the operation of the converter to the specific system requirements. ENABLE The device starts operation when EN is set high and starts up with the soft start as previously described. For proper operation, the EN pin must be terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown, with a shutdown quiescent current of typically 0.1μA. In this mode, the P and N-channel MOSFETs are turned off, the internal resistor feedback divider is disconnected, and the entire internal-control circuitry is switched off. SOFT START The TPS6261x has an internal soft-start circuit that limits the inrush current during start-up. This limits input voltage drops when a battery or a high-impedance power source is connected to the input of the converter. The soft-start system progressively increases the on-time from a minimum pulse-width of 35ns as a function of the output voltage. This mode of operation continues for c.a. 100μs after enable. Should the output voltage not have reached its target value by this time, such as in the case of heavy load, the soft-start transitions to a second mode of operation. The converter then operates in a current limit mode, specifically the P-MOS current limit is set to half the nominal limit, and the N-channel MOSFET remains on until the inductor current has reset. After a further 100 μs, the device ramps up to the full current limit operation if the output voltage has risen above 0.5V (approximately). Therefore, the start-up time mainly depends on the output capacitor and load current. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 TPS62619, TPS62612 TPS62615, TPS62616 www.ti.com SLVS936 – NOVEMBER 2009 OUTPUT CAPACITOR DISCHARGE The TPS6261x device can actively discharge the output capacitor when it turns off. The integrated discharge resistor has a typical resistance of 15 Ω. The required time to discharge the output capacitor at the output node depends on load current and the output capacitance value. UNDERVOLTAGE LOCKOUT The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the converter from turning on the switch or rectifier MOSFET under undefined conditions. The TPS6261x device have a UVLO threshold set to 2.05V (typical). Fully functional operation is permitted down to 2.1V input voltage. SHORT-CIRCUIT PROTECTION The TPS6261x integrates a P-channel MOSFET current limit to protect the device against heavy load or short circuits. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is turned off and the N-channel MOSFET is turned on. The regulator continues to limit the current on a cycle-by-cycle basis. As soon as the output voltage falls below ca. 0.4V, the converter current limit is reduced to half of the nominal value. Because the short-circuit protection is enabled during start-up, the device does not deliver more than half of its nominal current limit until the output voltage exceeds approximately 0.5V. This needs to be considered when a load acting as a current sink is connected to the output of the converter. THERMAL SHUTDOWN As soon as the junction temperature, TJ, exceeds typically 140°C, the device goes into thermal shutdown. In this mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction temperature again falls below typically 130°C. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 17 TPS62619, TPS62612 TPS62615, TPS62616 SLVS936 – NOVEMBER 2009 www.ti.com APPLICATION INFORMATION INDUCTOR SELECTION The TPS6261x series of step-down converters have been optimized to operate with an effective inductance value in the range of 0.3μH to 1.8μH and with output capacitors in the range of 4.7μF to 10μF. The internal compensation is optimized to operate with an output filter of L = 0.47μH and CO = 4.7μF. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. For more details, see the CHECKING LOOP STABILITY section. The inductor value affects its peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage ripple and the efficiency. The selected inductor has to be rated for its dc resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VI or VO. V V *V DI I O DI + O DI +I ) L L L(MAX) O(MAX) 2 V L ƒ sw I (1) with: fSW = switching frequency (6 MHz typical) L = inductor value ΔIL = peak-to-peak inductor ripple current IL(MAX) = maximum inductor current In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (i.e. quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, care should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor size, increased inductance usually results in an inductor with lower saturation current. The total losses of the coil consist of both the losses in the DC resistance (DC)) and the following frequency-dependent components: • The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies) • Additional losses in the conductor from the skin effect (current displacement at high frequencies) • Magnetic field losses of the neighboring windings (proximity effect) • Radiation losses The following inductor series from different suppliers have been used with the TPS6261x converters. Table 1. List of Inductors MANUFACTURER MURATA SERIES DIMENSIONS (in mm) LQM21PNR47MC0 2.0 x 1.2 x 0.55 max. height LQM21PN1R0MC0 2.0 x 1.2 x 0.55 max. height LQM21PN1R5MC0 2.0 x 1.2 x 0.55 max. height LQM21P-SAMPLE02 2.0 x 1.2 x 0.4 max. height 1.6 x 0.8 x 0.55 max. height LQM18PN1R5-B35SAMPLE01 1.6 x 0.8 x 0.4 max. height 1.6 x 0.8 x 0.33 max. height TAIYO YUDEN TDK 18 Submit Documentation Feedback BRC1608T1R0 1.6 x 0.8 x 0.9 max. height BRC1608T1R5 1.6 x 0.8 x 0.9 max. height MLP2012SR82T 2.0 x 1.2 x 0.55 max. height Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 TPS62619, TPS62612 TPS62615, TPS62616 www.ti.com SLVS936 – NOVEMBER 2009 OUTPUT CAPACITOR SELECTION The advanced fast-response voltage mode control scheme of the TPS6261x allows the use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. For best performance, the device should be operated with a minimum effective output capacitance of 1.6μF. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the voltage step caused by the output capacitor ESL and the ripple current flowing through the output capacitor impedance. At light loads, the output capacitor limits the output ripple voltage and provides holdup during large load transitions. A 4.7μF capacitor typically provides sufficient bulk capacitance to stabilize the output during large load transitions. The typical output voltage ripple is 1% of the nominal output voltage VO. The output voltage ripple during PFM mode operation can be kept very small. The PFM pulse is time controlled, which allows to modify the charge transferred to the output capacitor by the value of the inductor. The resulting PFM output voltage ripple and PFM frequency depend in first order on the size of the output capacitor and the inductor value. The PFM frequency decreases with smaller inductor values and increases with larger once. Increasing the output capacitor value and the effective inductance will minimize the output ripple voltage. INPUT CAPACITOR SELECTION Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required to prevent large voltage transients that can cause misbehavior of the device or interferences with other circuits in the system. For most applications, a 2.2-μF capacitor is sufficient. If the application exhibits a noisy or erratic switching frequency, the remedy will probably be found by experimenting with the value of the input capacitor. Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed between CI and the power source lead to reduce ringing than can occur between the inductance of the power source leads and CI. CHECKING LOOP STABILITY The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals: • Switching node, SW • Inductor current, IL • Output ripple voltage, VO(AC) These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination. As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply all of the current required by the load. VO immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR is the effective series resistance of CO. ΔI(LOAD) begins to charge or discharge CO generating a feedback error signal used by the regulator to return VO to its steady-state value. The results are most easily interpreted when the device operates in PWM mode. During this recovery time, VO can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range, load current range, and temperature range. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 19 TPS62619, TPS62612 TPS62615, TPS62616 SLVS936 – NOVEMBER 2009 www.ti.com LAYOUT CONSIDERATIONS As for all switching power supplies, the layout is an important step in the design. High-speed operation of the TPS6261x devices demand careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability and switching frequency issues as well as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. In order to get an optimum ESL step, the output voltage feedback point (FB) should be taken in the output capacitor path, approximately 1mm away for it. The feed-back line should be routed away from noisy components and traces (e.g. SW line). MODE CI L VIN ENABLE CO GND VOUT Figure 36. Suggested Layout (Top) 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 TPS62619, TPS62612 TPS62615, TPS62616 www.ti.com SLVS936 – NOVEMBER 2009 APPLICATION CIRCUITS The following are example circuits. 100Ω 1 mF VIN 2.9 V .. 5.5 V TPS62616 L VIN SW EN FB VOUT(DC/DC) = 2.3 V TPS72018 IN 1 mH VOUT(LDO) = 1.8 V @ 350 mA BIAS OUT CI 2.2 mF CO EN 4.7 mF CO GND 4.7 mF MODE GND L = muRata LQM21PN1R0MC0 CI = muRata GRM155R60J225ME15 CO = muRata GRM155R60J475M Figure 37. 1.8V Power Rail Featuring Very Low Noise Performance EFFICIENCY vs LOAD CURRENT SPURIOUS OUTPUT NOISE (PFM MODE) vs. FREQUENCY 90 13 m VOUT(DC/DC) = 2.3 V, 85 V OUT(LDO) = 1.8 V Spurious Output Noise (PFM Mode) - V 80 VI = 3.6 V 75 VI = 3.3 V Efficiency - % 70 65 60 VI = 4.2 V 55 50 45 40 35 11 m VIN = 3.6 V VOUT(LDO) = 1.8 V 10 m RL = 100 Ω 12 m L = muRata LQM21PN1R0MC0 9m 8m 7m 6m 5m 4m 3m 2m 1m 30 1 10 100 IO - Load Current - mA Figure 38. Copyright © 2009, Texas Instruments Incorporated 1000 0 Span = 1 MHz f - Frequency - MHz 10 Figure 39. Submit Documentation Feedback Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 21 TPS62619, TPS62612 TPS62615, TPS62616 SLVS936 – NOVEMBER 2009 www.ti.com SPURIOUS OUTPUT NOISE (PWM MODE) vs. FREQUENCY 60 m VIN = 3.6 V VOUT(LDO) = 1.8 V Spurious Output Noise (PWM Mode) - V 55 m 50 m RL = 12 Ω 45 m 40 m 35 m 30 m 25 m 20 m 15 m 10 m 5m 0 Span = 4 MHz f - Frequency - Mhz 40 Figure 40. 22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 TPS62619, TPS62612 TPS62615, TPS62616 www.ti.com SLVS936 – NOVEMBER 2009 THERMAL INFORMATION Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below: • Improving the power dissipation capability of the PCB design • Improving the thermal coupling of the component to the PCB • Introducing airflow into the system The maximum recommended junction temperature (TJ) of the TPS6261x devices is 105°C. The thermal resistance of the 6-pin CSP package (YFD-6) is RθJA = 125°C/W. Regulator operation is specified to a maximum steady-state ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about 160 mW. PD(MAX) = TJ(MAX) - TA 105°C - 85°C = = 160mW RqJA 125°C/W (2) PACKAGE SUMMARY CHIP SCALE PACKAGE (BOTTOM VIEW) D A2 A1 B2 B1 CHIP SCALE PACKAGE (TOP VIEW) YMSCC LLLL A1 C1 C2 Code: E • YM — Year Month date Code • S — Assembly site code • CC— Chip code • LLLL — Lot trace code CHIP SCALE PACKAGE DIMENSIONS The TPS6261x device is available in an 6-bump chip scale package (YFD, NanoFree™). The package dimensions are given as: • D = 1.30 ±0.03 mm • E = 0.926 ±0.03 mm Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 23 PACKAGE OPTION ADDENDUM www.ti.com 25-Nov-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS62615YFDR PREVIEW DSBGA YFD 6 3000 TBD Call TI Call TI TPS62615YFDT PREVIEW DSBGA YFD 6 250 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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