EM MICROELECTRONIC-MARIN SA H6061 3 V Self Recovering Watchdog Features Typical Operating Configuration n Watchdog fully operational from 2.7 to 5.25 V n Regulated DC voltage monitor, internal voltage reference n Self recovering watchdog function: reset goes active after the 1st timeout period, reset goes inactive again after the 2nd timeout period, repeated active reset signal until the system recovers n Standard timeout period and power-on reset time (100 ms), externally programmable from 3 ms to 3 mins if required n Works down to 1.6 V supply voltage n Low voltage alarm prior to reset on power-down n Reset outputs of both polarities n Open drain outputs n Small footprint SO8 and DIP8 packages 5V H6061 VDD VIN RES TCL SAVE RES VSS NMI µP RES I/O GND Description The H6061 is a combined initialiser, watchdog and voltage monitor. The circuit is a low voltage low power monolithic CMOS device combining a series of voltage comparators and a programmable timer on the same chip. The device is specially suited to telecommunications applications where 3 V working is expected, for functions such as supply voltage and microprocessor monitoring. The reset outputs are self recovering after a watchdog timeout, enabling the circuit to work with standalone systems without any external push-switch or control signal to restart after a watchdog timeout. The circuit provides a reset signal of both polarities. The state of the outputs is defined down to 1.6 V. An internal debouncer ensures power-up perfomance for fast-rise supply lines. Fig. 1 Pin Assignment DIP8 / SO8 Applications n n n n n Microprocessor and microcontroller systems Point of sales equipment Telecom products Automotive subsystems Microcontroller 68HC05 applications VIN TCL RC VSS VDD H6061 RES SAVE RES Fig. 2 1 H6061 Absolute Maximum Ratings Handling Procedures Parameter Voltage VDD to VSS Voltage at any pin to VSS Voltage at any pin to VDD Voltage at VIN to VSS Current at any output Storage temperature Electrostatic discharge max. to MIL-STD-833C method 3015 This device has built-in protection against high static voltages or electric fields; however, it is advised that normal precautions be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level. Symbol Conditions − 0.3 to + 5.6 V VDD VMIN − 0.3 VMAX + 0.3 VINMAX + 12 V IMAX ± 10 mA TSTO −65 to +150 °C VSmax 1000 V Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. Operating Conditions Parameter Symbol Min. Typ. Max. Units Operating temperature TA Industrial VDD Supply voltage Monitored input voltage VIN RC-oscillator programm ing (see Fig. 15) External capacitance∗ C1 External resistance R1 ∗ -40 2.7 0 10 +85 5.25 12 °C V V 1 µF kΩ Table 2 Leakage < 1 µA Electrical Characteristics VDD = 5.0 V, TA = −40 to +85 °C , unless otherwise specified Parameter Symbol Test Conditions VDD activation threshold VDD deactivation threshold Supply current VON VOFF IDD TA = 25 °C TA = 25 °C RC open, TCL at VDD or VSS Input VIN, TCL Leakage current IP TCL input low level TCL input high level VIL VIH VSS < VIP <VDD TA = 80 °C Leakage on pins SAVE , RES , RES O/P drive logic low Min. 2.3 Typ. VON − 0.3 80 VOUT = VDD VOL = 0.4 V VDD = 3.5 V; VOL = 0.4 V VDD = 1.6 V; VOL = 0.4 V 4 2 80 Units 2.7 V V µA 140 0.005 1 0.8 µA 0.050 8 1 µA mA mA µA 2.4 IOLK IOL IOL IOL Max. V V Table 3 VIN Surveillance Voltage thresholds at TA = 25 °C Version No. 25 Thresholds VSH VSL VRL 1.54 1.50 1.46 at VDD Threshold Voltage Tolerance Threshold Ratio* Pin VIN Input 2.7 – 5.0 V ±10% ±2% ∼100 MΩ * Threshold ratio defined as VSH / VSL or VSL / VRL. 2 Table 4 H6061 Timing Characteristics VDD = 5.0 V, TA = −40 to +85 °C (−40 to +125 °C for extended temperature range version), unless otherwise specified Parameter Symbol Test Conditions Propagation delays TCL to output pins VIN to output pins TDIDO TAIDO Logic transition times on all output pins Min. Typ. Max. Units Excluding debounce time TDB 250 4 500 10 ns µs TTR Load 10 kΩ, 100 pF 30 100 ns Timeout period TTCL input pulse width TTO TTCL RC open, unshielded, TA = 25 °C 100 160 ms ns Power-on reset debounce TDB Fastest pulse VIN with debounce TVINL 60 150 TTO/64 −40 to +85 °C 10 ms µs Table 5 Timing Waveforms Voltage Reaction: VDD Monitoring VDD VON VOFF VIN monitoring enabled Fig. 3 Voltage Reaction: VIN Monitoring Conditions: VDD > VON. No timeout sequence. VIN VSH VSL VRL TTO TVINL TDB 0 TTO TDB SAVE RES RES Timer Start Power-on Reset Timer Stop Timer Start Power-on Reset No Power-on Reset (as VIN > VRL) Fig. 4 3 H6061 Timer Reaction TTCL TCL RES TTO Conditions: VIN > VRL after power-up sequence TTO TTO TTO RES Timer Reset Timer Reset Timeout Timer Reset Fig. 5 Combined Voltage and Timer Reaction VIN VSH VSL VRL TDB SAVE TTO RES RES TTO TTO TCL RES Initialisation RES Timer Stop Timer Reset Timeout Recover Fig. 6 Block Diagram VIN Band-Gap Reference VSH + Save Control SAVE Reset Control RES + VSL + VRL + RES VSS RC OSC Timer TCL 4 Fig. 7 H6061 Pin Description Pin Name Function 1 2 3 4 5 6 7 8 Voltage monitoring input Timer clear input signal RC oscillator tuning input GND terminal Reset output, open drain Save output, open drain Positive reset output, open drain Positive supply voltage VIN TCL RC VSS RES SAVE RES VDD Table 6 Functional Description Thresholds and Outputs The H6061 has open-drain outputs and voltage thresholds on pin VIN of typically 1.5 V. Internal Voltage Comparators The voltage comparators detect the voltage applied to pin VIN and compare it with thresholds VSH, VSL and VRL. The H6061 is designed for monitoring regulated DC voltages and has bandgap thresholds independent of VDD. The reaction of the H6061 to voltage changes on pin VIN is given in Fig. 4. During powering-up, the outputs are active. After VIN reaches the VSH level, pin SAVE deactivates after a short debounce time TDB to allow for fast ramp-ups. The initialization time TTO then passes before the two reset outputs go inactive. Thereafter, when the voltage on pin VIN falls below the VSL level, pin SAVE goes active low as a first warning. If VIN then drops below the VRL level, the reset signals go active and are guaranteed down to 1.6 V. The reset outputs react also to timeouts (see “Timer clearing”). Note that when the supply voltage VDD is below the level VOFF (about 2.2 V), all outputs are in the active state for any allowed voltage of VIN. Voltage Programming The H6061 was designed to give the best compromise in normal usage (see Table 3). Its voltage threshold can be programmed by an external resistor divider or a potentiometer to react at proportionally higher voltage levels (see Fig. 8 below). Voltage Programming VIN H6061 +3 V / +5 V VDD Timer Programming A single timeout period TTO is used for the initialization reset duration and the watchdog timeout. With pin RC unconnected, the on-chip RC oscillator and divider chain give a timeout period TTO of typically 100 ms. A resistor to VDD will shorten this time, and a capacitor to VSS will lengthen it (see Fig. 11). An approximation for calculating trial values given in milliseconds by the formula: (32 + C1 ) ⋅ 1.6 TTO = 0.75 + ⋅ 8.192 VDD - 0.8 4.8 + R1 R1 min. = 10 kΩ, C1 max. = 1 µF If R1 is in MΩ and C1 in pF, TTO will be in ms. Choice of component values must be determined in practice. To have a square wave of period 2TTO, simply connect pin TCL to VDD or VSS and take the signal output from a reset pin. Timer Clearing A negative edge or pulse at the TCL input longer than 150 ns will clear the timer and deactivate the reset outputs under normal running conditions (see Fig. 3). TCL will however have no effect either when VDD < VOFF or during the initialization period before the deactivation of the reset pins. Combined Voltage and Timer Action In Fig. 6 is a typical sequence of power-up, watchdog run, and power-down. During initialization the SAVE pin deactivates one debounce delay time TDB after VIN rises above VSH, or when the power line VDD rises above VON, whichever happens last. The reset pins only deactivate one timeout period TTO afterwards to free the watchdog timer and end the initialization. Note that either VIN falling below VRL threshold or VDD below VON will cause an initialization upon recovery. Following initialization, the watchdog timer will time out after time TTO unless at least one TCL pulse clears it. On timeout the reset pins reactivate for a further TTO period before deactivating again for another try. A TCL pulse will deactivate any timeout reset, and another TCL pulse must follow within a time TTO to keep reset inactive. If no TCL pulses come at all, the reset pins go square-wave. Power-down overrides all this however. A falling voltage on VIN gives a warning SAVE = 0 signal at VIN = VSL before activating the reset pins as soon as VIN drops below VRL. The H6061 has fixed thresholds and low hysteresis for monitoring regulated DC lines. Additional protection is provided in case VDD supply falls over about 10% below VON which thereupon activates all outputs at once. VSS Fig. 8 5 H6061 Typical Applications Microprocessor Watchdog with Voltage Monitor Monitored Voltage 5V SEL TCL Latched Address Bus VDD H6061 RC RES VSS RD R1 =470 kΩ C1 = 220 pF SAVE Address Decoder VIN RES Microprocessor CS Disable NMI TTO = ~250 ms Selection of Watchdogs for Each Application The H6061 is designed for monitoring regulated DC voltages anywhere between 2.7 and 5.25 V. Typically, it is used to monitor VDD with pin VIN tied to the midpoint of a voltage divider (see Fig. 8). This arrangement has the advantage of being able to trigger at selectable voltage limits, i. e. it can be used where the regulated voltage is below 5 VDC. Industrial Heavy-Duty Utilisation The H6061 debounce protects against reactions due to fast-rise power lines, but absolute maximum ratings must be respected. With its flexibility of voltage programming and supply voltage the H6061 can allow for voltage drops along supply lines, so it can be placed remotely, like on plug-in boards (see Fig. 9). The H6061 is suitable for supply voltages down to 2.7 VDC. As the H6061 is designed to be sensitive to voltage changes, fast switching lines, like address/data bus lines should not be run between the VDD and VSS supply lines near the H6061 without ground-plane shielding. Tracks from components to pin RC must be kept very short. Pin RC if left free should be shielded with a ground ring in noisy environments. The H6061 has only 40 mV hysteresis specially for monitoring regulated DC. Pin VIN must be protected from any significant mains ripple or RFI (see Fig. 10). It should be placed as near as possible to the point where voltage is to be monitored. Pin VIN is protected by an RAM Fig. 9 internal resistor (nominal 15 kΩ) against voltages in excess of VDD. In some environments this may however pick up enough mains ripple or RFI to distort the voltage detection thresholds or even cause unwanted sporadic resets in the absence of adequate shielding or filtering on VIN. The H6061 has sufficient immunity to ripple and interference on the VDD supply line, but if it is important that a system meet severe criteria for injected spikes and RFI, then care must be taken also decouple VDD from these influences, as system protection must continue even under these conditions. With normal series voltage regulators, the regulated 5 VDC output voltage follows the DC rough voltage within 1.5 V on powering up. If the application has pin VIN monitoring the DC rough, the internal inputs to the on-chip comparators will not rise above VDD if the H6061 is correctly programmed. With switched-mode power supplies however, the DC-rough voltage on power-up rises almost to its working level before the 5 VDC line starts to ramp up. The H6061 has been specially designed to work under these extreme conditions but care must be taken not to exceed absolute maximum ratings. In addition to the voltage monitoring on pin VIN, a final protection is given by the H6061 monitoring its own VDD supply. If a system malfunction causes VDD to fall below VOFF even though pin VIN stays high, then all outputs go active at once. 6 H6061 Combined Supply Monitor, Initializer and Watchdog VIN shield 1) or decoupling 2) optional against interference 3 VDC 33 kΩ Nominal thresholds: VSH 2.84 VSL 2.77 VRL 2.70 VDD VIN 1) SAVE H6061 2) 39 kΩ TCL RES VSS Fig. 10 C1 VSS C1 increases TTO R1 TCL RC RES VSS R1 shortens TTO Note: if external components R1 and C1 are used, a tighter timeout period tolerance can be achieved. VDD TO R1 TCL RC RES C1 VSS H6061 RC VDD TO H6061 TCL H6061 External Programming of RC Oscillator VDD TO RES This circuit provides independent programming of both timeout period and power-on reset delay. Fig. 11 7 H6061 Ordering Information Industrial temperature range (−40 to +85 °C) Type1) Package H6061 25 8P DIP8 H6061 25 8S SO8 Extended temperature range (−40 to +125 °C) Type Package H6061 25X 8P DIP8* H6061 25X 8S SO8* * Non-stock items Chip form on request EM Microelectronic-Marin SA cannot assume any responsibility for use of any circuitry described other than entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. © 2000 EM Microelectronic-Marin SA, 10/00, Rev. F/327 8 EM Microelectronic-Marin SA, CH - 2074 Marin, Switzerland, Tel. (+41) 32 - 755 51 11, Fax (+41) 32 - 755 54 03