Vladimir Ostrerov ® Q1 Si4874 1.5V 4A DC/DC CONVERTER 1.5VOUT R1 10Ω D1 MBR303 Q2 Si4874 1.8V 4A DC/DC CONVERTER 1.8VOUT R2 10Ω D2 MBR303 Q3 Si4874 2.5V 0.25A DC/DC CONVERTER D3 2.5VOUT R3 10Ω RS 1 0.005Ω 2 3.3V 10A DC/DC CONVERTER D4 MBR303 Q4 Si4874 3.3VOUT 4 3 R4 10Ω Q5 Si4874 5V 2A DC/DC CONVERTER R6 931Ω R8 4.02k R10 1.82k R7 1.1k R9 10k R11 2.8k 3 4 SW1 5VOUT 10A R5 10Ω R14 1.8k C1 0.1µF 5 VCC3 VCCA VCC18 RST LTC1728-1.8 GND 11/01/272 D5 MBR303 8 7 VCC SENSE LTC1422 ON GND TIMER CT 0.33µF R15 1.24k 6 GATE FB RESET DN268 F01 TO SYSTEM dVGATE IGATE = dt CG IINRUSH = CLOAD • IGATE CG 1.5V 0 TO A: ALL THREE POWER SUPPLY OUTPUTS MONITORED BY LTC1728-1.8 ARE WITHIN ACCEPTABLE LIMITS 1.8V A TO B: 200ms DELAY IN BEFORE RST IS GENERATED 5.5V C: TIME WHEN 2.5V OUTPUT DIVIDER REACHES ON (LTC1422) THRESHOLD LEVEL 2.5V C TO D: LTC1422 TIMER PERIOD 3.3V D TO D1: GATE VOLTAGE GROWS FROM ZERO TO MOSFET THRESHOLD F: TIME WHEN 2.5V OUTPUT IS IN THE APPROPRIATIVE STATE 1.3V G: RESET GENERATED AFTER TIMING CYCLE TTIMER A1 A2 5.5V 3.3V 2.5V 1.8V 1.5V 200ms OUTPUT VOLTAGES TTIME RESET 0 A B C D D1 F F′ G DN268 F03 dn272f 1101 34K • PRINTED IN JAPAN LINEAR TECHNOLOGY CORPORATION 2001