OKI Semiconductor ML87V2104 PEDL87V2104DIGEST-01 Issue Date: Jan. 20, 2003 Preliminary Video Signal Noise Reduction and Field Rate Conversion IC with a Built-in 4M Bit Field Memory GENERAL DESCRIPTION The ML87V2104 consists of a 3-port type (1 input port and 2 output ports) 4.4 Mbit (960 × 288 × 16bits) field memory and logic circuits for signal processing and memory control. The device can reduce field-recursive noise. Noise reduction auto mode can be set by detecting the noise in the vertical blanking period and by setting the noise reduction setting value according to the detected noise state. Moreover, an internal memory controller controls flicker-free conversion that doubles the vertical and horizontal direction frequencies. FEATURES • Memory capacity : 4.4 Mbit (960 × 288 × 16 bits) × 1 unit • Maximum input operating frequencies (16 bits/8 bits, ITU-R BT.656): 18/36 MHz (at 960 effective horizontal pixels) • Maximum output operating frequencies (normal/flicker-free): 18/36 MHz (at 960 effective horizontal pixels) • Power supply voltage : 3.3 V ± 0.3 V • Input pin: TTL-5V tolerant (5 V withstand voltage) • Input/output pins: Input TTL- output LVCMOS-5V tolerant (5 V withstand voltage) • Output pin: LVCMOS (3.3 V) • Input data format: YCbCr (8 bits (Y) + 8 bits (CbCr)) (4:2:2): Input 16-bit mode YCbCr (8 bits (YCbCr)) (4:2:2): Input 8-bit mode ITU-R656 (8 bits (YCbCr)): Input ITU-R BT.656 mode • Output data format: YCbCr (8 bits (Y) + 8 bits (CbCr)) (4:2:2) • Serial bus: I2C-bus interface: (400 kHz, 100 kHz) • Memory controller functions: Input: Compliant to 525/60 Hz 2:1, 625/50 Hz 2:1 Output: 625/50 Hz 2:1, 525/60 Hz 2:1, 625/100 Hz 2:1, 525/120 Hz 2:1 • Sync generator functions: Can generate sync signals of 625/50 Hz 2:1, 525/60 Hz 2:1, 625/100 Hz 2:1, 525/120 Hz 2:1. • Field-recursive type noise reduction function: Noise detection and noise subtraction type (with horizontal motion compensation) Auto mode noise reduction (noise is detected during vertical blanking period) • Package: 100 pin QFP (QFP100-P-1420-0.65-BK4) 1/13 IVS_dly YO0-7 CO0-7 2 I C-bus I/F Register Output Sync. Generator IF IHS_dly INT OKI Semiconductor RESET TEST1-5 MTEST1-7 SCL SDA SLA1 SLA2 MODE0-2 SSG Control Signal Memory Controller HREF CLKO x16 DNR IVS IHS x16 R_Port1 3 ports Field Memory 4.4 Mbits (960 × 288 × 16) R_Port2 x16 OCLK OE OVS OHS x16 x16 W_Port ICLK YI0-7 CI0-7 Input Process Block + 3D NR PEDL87V2104DIGEST-01 ML87V2104 BLOCK DIAGRAM 2/13 PEDL87V2104DIGEST-01 OKI Semiconductor ML87V2104 VSS MTEST1 MTEST2 MTEST3 MTEST4 MTEST5 TEST1 TEST2 TEST3 TEST4 VDD TEST5 N.C. N.C. N.C. N.C. OE MTEST6 MTEST7 VSS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PIN CONFIGURATION (TOP VIEW) VDD 1 80 VDD N.C. 2 79 RESET N.C. 3 78 N.C. VSS 4 77 N.C. SDA 5 76 N.C. SCL 6 75 N.C. SLA1 7 74 N.C. SLA2 8 73 VSS YI7 9 72 YO7 YI6 10 71 YO6 YI5 11 70 YO5 YI4 12 69 YO4 YI3 13 68 VDD YI2 14 67 YO3 66 YO2 65 YO1 ML87V2104 YI1 15 YI0 16 (QFP100-P-1420-0.65-BK4) 64 YO0 ICLK 18 63 VSS VDD 17 VSS 19 62 OCLK CI7 20 61 VDD CI6 21 60 CO7 CI5 22 59 CO6 CI4 23 58 CO5 CI3 24 57 CO4 CI2 25 56 VSS CI1 26 55 CO3 VSS 50 HREF 49 OVS 48 OHS 47 INT 46 SSG 45 N.C. 44 DNR 43 VDD 42 N.C. 41 VSS 40 VDD 39 VDD CLKO 38 51 MODE2 37 VDD 30 N.C. 36 CO0 MODE0 34 52 MODE1 35 CO1 N.C. 29 IVS 32 CO2 53 IHS 33 54 VSS 31 CI0 27 N.C. 28 3/13 PEDL87V2104DIGEST-01 OKI Semiconductor ML87V2104 PIN DESCRIPTIONS No. 1 2 3 4 Symbol VDD N.C. N.C. VSS I/O — — — — 5 SDA I/O 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCL SLA1 SLA2 YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 VDD ICLK VSS CI7 CI6 CI5 CI4 CI3 CI2 CI1 CI0 N.C. N.C. VDD VSS I I I I I I I I I I I — I — I I I I I I I I — — — — 32 IVS I/O 33 IHS I/O 34 35 36 37 38 39 40 41 MODE0 MODE1 N.C. MODE2 CLKO VDD VSS N.C. I I — I O — — — Pad Remarks Pin Description Power supply 3.3 V Unused pin Unused pin Ground Schmitt(IN)/ OpenDrain(OUT) Schmitt pull-down 50k pull-down 50k Schmitt(IN) pull-down 50k Schmitt(IN) pull-down 50k pull-down 50k pull-down 50k pull-down 50k I2C-bus data pin I2C-bus clock pin Slave address setting pin Slave address setting pin Luminance signal input pin bit 7 (MSB) Luminance signal input pin bit 6 Luminance signal input pin bit 5 Luminance signal input pin bit 4 Luminance signal input pin bit 3 Luminance signal input pin bit 2 Luminance signal input pin bit 1 Luminance signal input pin bit 0 (LSB) Power supply 3.3 V Input system clock pin Ground Chrominance signal input pin bit 7 (MSB) Chrominance signal input pin bit 6 Chrominance signal input pin bit 5 Chrominance signal input pin bit 4 Chrominance signal input pin bit 3 Chrominance signal input pin bit 2 Chrominance signal input pin bit 1 Chrominance signal input pin bit 0 (LSB) Unused pin Unused pin Power supply 3.3 V Ground Input vertical sync signal input/output pin Input horizontal sync signal input/output pin Mode setting pin – bit 0 Mode setting pin – bit 1 Unused pin Mode setting pin – bit 2 Clock output (I2C-bus control possible) Power supply 3.3 V Ground Unused pin 4/13 PEDL87V2104DIGEST-01 OKI Semiconductor ML87V2104 No. 42 Symbol VDD I/O — Pad Remarks 43 DNR I pull-down 50k 44 45 N.C. SSG — I pull-down 50k 46 INT I pull-down 50k 47 OHS I/O Schmitt(IN) pull-down 50k Output system horizontal sync signal input/output pin 48 OVS I/O Schmitt(IN) pull-down 50k Output system vertical sync signal input/output pin 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 HREF VSS VDD CO0 CO1 CO2 CO3 VSS CO4 CO5 CO6 CO7 VDD OCLK VSS YO0 YO1 YO2 YO3 VDD O — — O O O O — O O O O — I — O O O O — Data output horizontal reference signal output pin Ground Power supply 3.3 V Chrominance signal output pin – bit 0 (LSB) Chrominance signal output pin – bit 1 Chrominance signal output pin – bit 2 Chrominance signal output pin – bit 3 Ground Chrominance signal output pin – bit 4 Chrominance signal output pin – bit 5 Chrominance signal output pin – bit 6 Chrominance signal output pin – bit 7(MSB) Ground Output system clock pin Ground Luminance signal output pin – bit 0 (LSB) Luminance signal output pin – bit 1 Luminance signal output pin – bit 2 Luminance signal output pin – bit 3 Power supply 3.3 V 69 70 71 72 73 74 75 76 77 78 YO4 YO5 YO6 YO7 VSS N.C. N.C. N.C. N.C. N.C. O O O O — — — — — — Luminance signal output pin – bit 4 Luminance signal output pin – bit 5 Luminance signal output pin – bit 6 Luminance signal output pin – bit 7 (MSB) Ground Unused pin Unused pin Unused pin Unused pin Unused pin 79 RESET I Pin Description Power supply 3.3 V Noise reduction output mode setting pin 0: Normal operation 1: Direct noise reduction mode Unused pin Internally generated sync signal mode setting pin Output system sync signal input/output select setting pin 0: OVS, OHS input mode 1: OVS, OHS internally generated output mode System reset input pin (0 active) 0: System reset 1: Normal operation Apply ICLK cycle one and more time during “0” level after VDD voltage has reached the specified level in System reset operation. 5/13 PEDL87V2104DIGEST-01 OKI Semiconductor ML87V2104 No. 80 81 82 83 Symbol VDD VSS MTEST7 MTEST6 I/O — — I I Pad Remarks pull-down 50k pull-down 50k 84 OE I pull-down 50k 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 N.C. N.C. N.C. N.C. TEST5 VDD TEST4 TEST3 TEST2 TEST1 MTEST5 MTEST4 MTEST3 MTEST2 MTEST1 VSS — — — — I — I I I I I I I I I — pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k pull-down 50k Pin Description Power supply 3.3 V Ground Memory test input pin – bit 7 (1: test mode) Memory test input pin – bit 6 (1: test mode) Output enable input pin (normally set to 1) 0: YO[7:0], CO[7:0] disable (Hi-z) 1: YO[7:0], CO[7:0] enable (drive) Equivalent operation to setting fixed to 1 in RESET=0 or DNR=1 Unused pin Unused pin Unused pin Unused pin Test input pin – bit 5 (1: test mode) Power supply 3.3 V Test input pin – bit 4 (1: test mode) Test input pin – bit 3 (1: test mode) Test input pin – bit 2 (1: test mode) Test input pin – bit 1 (1: test mode) Memory test input pin – bit 5 (1: test mode) Memory test input pin – bit 4 (1: test mode) Memory test input pin – bit 3 (1: test mode) Memory test input pin – bit 2 (1: test mode) Memory test input pin – bit 1 (1: test mode) Ground Notes: In 8-bit YcbCr and ITU-R BT. 656 mode, CI0-7 pin should be connected to the Vss level. 6/13 PEDL87V2104DIGEST-01 OKI Semiconductor ML87V2104 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Power supply voltage VDD Ta = 25°C –0.3 to 4.6 V Input pin voltage VI Ta = 25°C –0.3 to 7.0 V Output pin short-circuit current IOS Ta = 25°C 50 mA Power dissipation PD Ta = 25°C 1 W Operating temperature Topr — 0 to 70 °C Storage temperature Tstg — –50 to 150 °C Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Power supply voltage VDD 3.0 3.3 3.6 V Power supply voltage VSS 0 0 0 V Operating temperature Ta 0 — 70 °C Pin Capacitance (VCC = 3.3 V ± 0.3 V, f = 1 MHz, Ta = 25°C) Parameter Symbol Min. Max. Unit Ci — 10 pF Input/output capacitance (IVS, IHS, OVS, OHS) Cio1 — 10 pF Input/output capacitance (SDA) Cio2 — 10 pF Output capacitance Co — 10 pF Input capacitance 7/13 PEDL87V2104DIGEST-01 OKI Semiconductor ML87V2104 DC Characteristics (Ta = 0 to 70°C) Parameter Symbol Condition Min. Max. Unit H level input voltage VIH — 2.0 5.5 V L level input voltage VIL — –0.3 0.8 V Vt+ — — 2.0 V Vt– — 0.8 — V Schmitt trigger threshold voltage (SDA, SCL, IVS, IHS, OVS, OHS) Schmitt trigger threshold voltage (SDA, SCL, IVS, IHS, OVS, OHS) Hysteresis voltage width Vh — 0.1 — V H level input current (pull-down) IIH 50 kΩ Pull Down 20 200 µA IIL TTL –10 10 µA H level output voltage (other than SDA) VOH IOH = –4 mA 2.2 VDD V L level output voltage (other than SDA) VOL IOL = 4 mA 0 0.4 V VOOL IOL = 4 mA 0 0.4 V –10 10 µA — 100 mA mA Input leakage current L level output voltage (N-Ch.OD) (SDA) Output leakage current IOL Supply current (during operation) IDD1 0 ≤ Vout ≤ VDD Output is disabled ICLK: 36 MHz OCLK: 36 MHz Output open Supply current (during standby) IDD2 Input pin = VIL — 10 Symbol Condition Min. Max. Unit tICLK Input 16-bit mode 54 — Ns ICLK clock cycle time tICLK Input 8-bit mode 27 — Ns ICLK clock duty ratio dtICLK — 45 55 % tIISU — 5 — ns AC Characteristics (Ta = 0 to 70°C) Parameter ICLK clock cycle time ICLK system input set-up time ICLK system input hold time tIIH — 3 — ns ICLK system output delay time tIOD CL = 20 pF 5 22 ns OCLK clock cycle time tOCLK — 27 — ns OCLK clock duty ratio dtOCLK — 45 55 % tOISU — 5 — ns OCLK system input set-up time OCLK system input hold time tOIH — 3 — ns OCLK system output delay time tOOD CL = 20 pF 5 22 ns CL = 20 pF (OCLK output) 5 22 CLKO delay time tCKD CL = 20 pF (IICLK output) 6 25 CL = 20 pF (ICLK output) 6 22 CL = 20 pF 3 20 Data through time tDIDO ns ns Notes: 1. Input signal reference levels for the parameter measurement are VIH = 3.0 V and VIL = 0 V. Output reference levels are VOH = 1.5 V and VOL = 1.5 V. 8/13 PEDL87V2104DIGEST-01 OKI Semiconductor ML87V2104 Notes: 2. On power-up, the device is designed to begin proper operation after at least 100 µs after VCC has stabilized to a value within the range of recommended operating conditions. After this 100 µs stabilization interval, a minimum of 1-field dummy write operations and read operations must be performed. 9/13 PEDL87V2104DIGEST-01 OKI Semiconductor ML87V2104 Application Example1 Mode setting: ALL Pin Open Slave address: 1011100 Input format: 16bit YcbCr (Register setting: DISEL=0,R656=0) 3.3V OE 32 33 RGB CONVERTER DEFLECTION / SCAN CONVERTER / MPEG ENCODER DATA OUT CLK 62 OCLK System Reset 79 18 GND ICLK YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 CO7 CO6 CO5 CO4 CO3 CO2 CO1 CO0 HREF OVS OHS CLKO RESET IVS IHS 72 71 70 69 67 66 65 64 60 59 58 57 55 54 53 52 49 48 47 38 NR-FIFO ML87V2104 RESET DEGITAL VIDEO DECODER 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 4,19,31, 40,50,56, 63,73,81, 100 VIDEO IN YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 CI7 CI6 CI5 CI4 CI3 CI2 CI1 CI0 84 5 6 1,17,30, 39,51,61 , 68,80,90 SDA SCL VDD I2C-bus MATER CONTROLLER CX Application Example2 Mode setting: DNR=1(Direct Noise Reduction Mode), Others Pin:OPEN Slave address: 1011100 Input format: ITU-R BT.656(Register setting: DISEL=0,R656=1) Output format: ITU-R BT.656(Register setting: DOSEL=1) 3.3V DNR OE RGB CONVERTER DEFLECTION / SCAN CONVERTER / MPEG ENCODER DATA OUT RESET 62 OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN CLK 43 84 1,17,30, 39,51,61 , 68,80,90 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 OCLK System Reset 18 79 ICLK 32 33 RESET OPEN OPEN ITU-R BT.656 Format 72 71 70 69 67 66 65 64 60 59 58 57 55 54 53 52 49 48 47 38 NR-FIFO ML87V2104 4,19,31, 40,50,56, 63,73,81, 100 DEGITAL VIDEO DECODER 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 GND VIDEO IN YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 CI7 CI6 CI5 CI4 CI3 CI2 CI1 CI0 5 6 ITU-R BT.656 Format VDD SDA SCL I2C-bus MATER CONTROLLER 10/13 PEDL87V2104DIGEST-01 OKI Semiconductor ML87V2104 PACKAGE DIMENSIONS (Unit: mm) QFP100-P-1420-0.65-BK4 Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 1.54 TYP. 4/Nov. 28, 1996 Notes for Mounting the Surface Mount Type Package The QFP is a surface mount type package, which is very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 11/13 PEDL87V2104DIGEST-01 OKI Semiconductor ML87V2104 REVISION HISTORY Document No. Date PEDL87V2104DIGEST-01 Jan.20. 2003 Page Previous Current Edition Edition Description Preliminary edition 1 12/13 PEDL87V2104DIGEST-01 OKI Semiconductor ML87V2104 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd. 13/13