SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES582D – JULY 2004 – REVISED AUGUST 2005 • FEATURES • • • • • • Available in the Texas Instruments NanoStar™ and NanoFree™ Packages Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range I/Os Are 4.6-V Tolerant Ioff Supports Partial-Power-Down Mode Operation Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors • • Max Data Rates – 500 Mbps (1.8-V to 3.3-V Translation) – 320 Mbps (<1.8-V to 3.3-V Translation) – 320 Mbps (Translate to 2.5 V or 1.8 V) – 180 Mbps (Translate to 1.5 V) – 240 Mbps (Translate to 1.2 V) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) YEP OR YZP PACKAGE (BOTTOM VIEW) DCT OR DCU PACKAGE (TOP VIEW) VCCA A1 A2 GND 1 8 2 7 3 6 4 5 GND A2 A1 VCCA VCCB B1 B2 DIR 4 5 3 6 2 7 1 8 DIR B2 B1 VCCB DESCRIPTION/ORDERING INFORMATION This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVCH2T45 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes. The SN74AVCH2T45 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. ORDERING INFORMATION PACKAGE (1) TA NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YEP –40°C to 85°C (1) (2) (3) NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) ORDERABLE PART NUMBER TOP-SIDE MARKING (2) SN74AVCH2T45YEPR (3) Tape and reel SN74AVCH2T45YZPR (3) SSOP – DCT Tape and reel SN74AVCH2T45DCTR ET2_ _ _ VSSOP – DCU Tape and reel SN74AVCH2T45DCUR ET2_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Package preview Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES582D – JULY 2004 – REVISED AUGUST 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The SN74AVCH2T45 is designed so that the DIR input is powered by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, then both outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. FUNCTION TABLE (EACH TRANSCEIVER) INPUT DIR OPERATION L B data to A bus H A data to B bus LOGIC DIAGRAM (POSITIVE LOGIC) DIR A1 5 2 7 A2 3 6 VCCA 2 B1 VCCB B2 www.ti.com SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES582D – JULY 2004 – REVISED AUGUST 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCCA VCCB Supply voltage range VI Input voltage range (2) MIN MAX –0.5 4.6 I/O ports (A port) –0.5 4.6 I/O ports (B port) –0.5 4.6 Control inputs –0.5 4.6 A port –0.5 4.6 B port –0.5 4.6 A port –0.5 VCCA + 0.5 B port –0.5 VCCB + 0.5 UNIT V V VO Voltage range applied to any output in the high-impedance or power-off state (2) VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCCA, VCCB, or GND θJA Package thermal impedance (4) Tstg Storage temperature range DCT package 220 DCU package 227 YEP/YZP package (1) (2) (3) (4) V V °C/W 102 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. The package thermal impedance is calculated in accordance with JESD 51-7. 3 SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES582D – JULY 2004 – REVISED AUGUST 2005 Recommended Operating Conditions (1) (2) (3) (4) (5) VCCI VCCO MIN MAX UNIT VCCA Supply voltage 1.2 3.6 V VCCB Supply voltage 1.2 3.6 V High-level input voltage VIH Low-level input voltage VIL High-level input voltage VIH VIL Low-level input voltage VI Input voltage VO Output voltage IOH Data inputs (4) Data inputs (4) DIR (referenced to VCCA) (5) DIR (referenced to VCCA) (5) 2 V 1.2 V to 1.95 V VCCI × 0.35 1.95 V to 2.7 V 0.7 2.7 V to 3.6 V 0.8 1.2 V to 1.95 V VCCA × 0.65 1.95 V to 2.7 V 1.6 2.7 V to 3.6 V 2 1.2 V to 1.95 V VCCA × 0.35 1.95 V to 2.7 V 0.7 2.7 V to 3.6 V 3-state 0 3.6 Operating free-air temperature V 0.8 3.6 Low-level output current V V VCCO TA 4 1.6 2.7 V to 3.6 V 0 Input transition rise or fall rate (4) (5) 1.95 V to 2.7 V Active state ∆t/∆v (1) (2) (3) VCC × 0.65 0 High-level output current IOL 1.2 V to 1.95 V 1.2 V –3 1.4 V to 1.6 V –6 1.65 V to 1.95 V –8 2.3 V to 2.7 V –9 3 V to 3.6 V –12 1.2 V 3 1.4 V to 1.6 V 6 1.65 V to 1.95 V 8 2.3 V to 2.7 V 9 3 V to 3.6 V 12 –40 V V mA mA 5 ns/V 85 °C VCCI is the VCC associated with the data input port. VCCO is the VCC associated with the output port. All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V. For VCCA values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V. SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES582D – JULY 2004 – REVISED AUGUST 2005 Electrical Characteristics (1) (2) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 1.2 V to 3.6 V 1.2 V to 3.6 V IOH = –3 mA 1.2 V 1.2 V IOH = –6 mA 1.4 V 1.4 V 1.05 1.65 V 1.65 V 1.2 IOH = –9 mA 2.3 V 2.3 V 1.75 IOH = –12 mA 3V 3V 2.3 IOL = 100 µA 1.2 V to 3.6 V 1.2 V to 3.6 V IOL = 3 mA 1.2 V 1.2 V IOL = 6 mA 1.4 V 1.4 V 0.35 1.65 V 1.65 V 0.45 2.3 V 2.3 V 0.55 IOH = –8 mA VOL IOL = 8 mA VI = VIH VI = VIL IOL = 9 mA IOL = 12 mA II DIR input VI = VCCA or GND VI = 0.42 V IBHL (3) IBHH (4) IBHLO (5) IBHHO (6) (1) (2) (3) (4) (5) (6) –40°C to 85°C VCCB IOH = –100 µA VOH TA = 25°C VCCA 3V 3V 1.2 V to 3.6 V 1.2 V to 3.6 V 1.2 V 1.2 V MIN TYP MAX MIN MAX VCCO – 0.2 V 0.95 0.15 V 0.7 ±0.025 ±0.25 ±1 µA 25 1.4 V 1.4 V 15 VI = 0.58 V 1.65 V 1.65 V 25 VI = 0.7 V 2.3 V 2.3 V 45 VI = 0.8 V 3.3 V 3.3 V VI = 0.78 V 1.2 V 1.2 V µA 100 –25 VI = 0.91 V 1.4 V 1.4 V –15 VI = 1.07 V 1.65 V 1.65 V –25 VI = 1.6 V 2.3 V 2.3 V –45 VI = 2 V 3.3 V 3.3 V –100 1.2 V 1.2 V VI = 0 to VCC V 0.2 VI = 0.49 V VI = 0 to VCC UNIT µA 50 1.6 V 1.6 V 125 1.95 V 1.95 V 200 2.7 V 2.7 V 300 3.6 V 3.6 V 1.2 V 1.2 V µA 500 –50 1.6 V 1.6 V –125 1.95 V 1.95 V –200 2.7 V 2.7 V –300 3.6 V 3.6 V –500 µA VCCO is the VCC associated with the output port. VCCI is the VCC associated with the input port. The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. An external driver must source at least IBHLO to switch this node from low to high. An external driver must sink at least IBHHO to switch this node from high to low. 5 SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES582D – JULY 2004 – REVISED AUGUST 2005 Electrical Characteristics (1) (2) over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER Ioff IOZ A port B port A or B port ICCA TEST CONDITIONS VI = VCCI or GND, ICCB VI = VCCI or GND, ICCA + ICCB VI = VCCI or GND, 0V 0 to 3.6 V ±0.1 ±1 ±5 0 to 3.6 V 0V ±0.1 ±1 ±5 1.2 V to 3.6 V 1.2 V to 3.6 V ±0.5 ±2.5 1.2 V to 3.6 V 1.2 V to 3.6 V 10 IO = 0 MIN TYP MAX MIN MAX ±5 0V 3.6 V –2 3.6 V 0V 10 1.2 V to 3.6 V 1.2 V to 3.6 V 10 IO = 0 IO = 0 –40°C to 85°C VCCB VI or VO = 0 to 3.6 V VO = VCCO or GND TA = 25°C VCCA 0V 3.6 V 10 3.6 V 0V –2 1.2 V to 3.6 V 1.2 V to 3.6 V 20 UNIT µA µA µA µA µA Ci Control inputs VI = 3.3 V or GND 3.3 V 3.3 V 2.5 pF Cio A or B port VO = 3.3 V or GND 3.3 V 3.3 V 6 pF (1) (2) VCCO is the VCC associated with the output port. VCCI is the VCC associated with the input port. Switching Characteristics over recommended operating free-air temperature range, VCCA = 1.2 V (see Figure 11) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) 6 FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V TYP TYP TYP TYP TYP 3.1 2.6 2.4 2.2 2.2 3.1 2.6 2.4 2.2 2.2 3.4 3.1 3 2.9 2.9 3.4 3.1 3 2.9 2.9 5.2 5.2 5.1 5 4.8 5.2 5.2 5.1 5 4.8 5 4 3.8 2.8 3.2 5 4 3.8 2.8 3.2 8.4 7.1 6.8 5.7 6.1 8.4 7.1 6.8 5.7 6.1 8.3 7.8 7.5 7.2 7 8.3 7.8 7.5 7.2 7 The enable time is a calculated value derived using the formula shown in the enable times section. UNIT ns ns ns ns ns ns SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES582D – JULY 2004 – REVISED AUGUST 2005 Switching Characteristics over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 11) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.2 V VCCB = 1.5 V ± 0.1 V VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V TYP MIN MAX MIN MAX MIN MAX MIN MAX 2.8 0.7 5.4 0.5 4.6 0.4 3.7 0.3 3.5 2.8 0.7 5.4 0.5 4.6 0.4 3.7 0.3 3.5 2.7 0.8 5.4 0.7 5.2 0.6 4.9 0.5 4.7 2.7 0.8 5.4 0.7 5.2 0.6 4.9 0.5 4.7 3.9 1.3 8.5 1.3 7.1 1.1 5.5 1.4 4.6 3.9 1.3 8.5 1.3 7.1 1.1 5.5 1.4 4.6 4.7 1.1 7 1.4 6.9 1.2 6.9 1.7 7.1 4.7 1.1 7 1.4 6.9 1.2 6.9 1.7 7.1 7.4 12.4 12.1 11.8 11.8 7.4 12.4 12.1 11.8 11.8 6.7 13.9 11.6 9.1 7.8 6.7 13.9 11.6 9.1 7.8 UNIT ns ns ns ns ns ns The enable time is a calculated value derived using the formula shown in the enable times section. Switching Characteristics over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 11) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.2 V VCCB = 1.5 V ± 0.1 V VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V TYP MIN MAX MIN MAX MIN MAX MIN MAX 2.7 0.5 5.2 0.4 4.3 0.2 3.4 0.2 3.1 2.7 0.5 5.2 0.4 4.3 0.2 3.4 0.2 3.1 2.4 0.7 4.7 0.5 4.4 0.5 4 0.4 3.8 2.4 0.7 4.7 0.5 4.4 0.5 4 0.4 3.8 3.7 1.3 8.1 0.7 6.9 1.4 5.3 1.1 4.5 3.7 1.3 8.1 0.7 6.9 1.4 5.3 1.1 4.5 4.4 1.3 5.8 1.3 5.9 0.8 5.7 1.5 5.9 4.4 1.3 5.8 1.3 5.9 0.8 5.7 1.5 5.9 6.8 10.4 10.3 9.7 9.7 6.8 10.4 10.3 9.7 9.7 6.4 13.3 11.2 8.6 7.4 6.4 13.3 11.2 8.6 7.4 UNIT ns ns ns ns ns ns The enable time is a calculated value derived using the formula shown in the enable times section. 7 SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES582D – JULY 2004 – REVISED AUGUST 2005 Switching Characteristics over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 11) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.2 V VCCB = 1.5 V ± 0.1 V VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V TYP MIN MAX MIN MAX MIN MAX MIN MAX 2.6 0.4 4.9 0.2 4 0.2 3 0.2 2.6 2.6 0.4 4.9 0.2 4 0.2 3 0.2 2.6 2.1 0.6 3.8 0.5 3.4 0.4 3 0.3 2.8 2.1 0.6 3.8 0.5 3.4 0.4 3 0.3 2.8 2.4 0.7 7.9 0.8 6.4 0.8 5 0.5 4.3 2.4 0.7 7.9 0.8 6.4 0.8 5 0.5 4.3 3.8 1 4.3 0.6 4.3 0.5 4.2 1.1 4.1 3.8 1 4.3 0.6 4.3 0.5 4.2 1.1 4.1 5.9 7.9 7.7 7.2 6.9 5.9 7.9 7.7 7.2 6.9 5 12.8 10.4 7.9 6.8 5 12.8 10.4 7.9 6.8 UNIT ns ns ns ns ns ns The enable time is a calculated value derived using the formula shown in the enable times section. Switching Characteristics over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 11) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) 8 (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.2 V VCCB = 1.5 V ± 0.1 V VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V TYP MIN MAX MIN MAX MIN MAX MIN MAX 2.5 0.3 4.7 0.2 3.8 0.2 2.8 0.2 2.4 2.5 0.3 4.7 0.2 3.8 0.2 2.8 0.2 2.4 2.1 0.6 3.6 0.4 3.1 0.3 2.6 0.3 2.4 2.1 0.6 3.6 0.4 3.1 0.3 2.6 0.3 2.4 2.9 1.1 8 1 6.5 1.3 4.7 1.2 4 2.9 1.1 8 1 6.5 1.3 4.7 1.2 4 3.4 0.5 6.6 0.3 5.6 0.3 4.6 1.1 3.5 3.4 0.5 6.6 0.3 5.6 0.3 4.6 1.1 3.5 5.5 6.9 6.6 6.2 5.9 5.5 6.9 6.6 6.2 5.9 5.4 12.7 10.3 7.4 6.3 5.4 12.7 10.3 7.4 6.3 The enable time is a calculated value derived using the formula shown in the enable times section. UNIT ns ns ns ns ns ns SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES582D – JULY 2004 – REVISED AUGUST 2005 Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER CpdA CpdB (1) (1) A-port input, B-port output VCCA = VCCB = 1.5 V VCCA = VCCB = 1.8 V VCCA = VCCB = 2.5 V VCCA = VCCB = 3.3 V TYP TYP TYP TYP TYP 3 3 3 3 4 13 13 14 15 15 13 13 14 15 15 3 3 3 3 4 CL = 0, f = 10 MHz, tr = tf = 1 ns B-port input, A-port output (1) VCCA = VCCB = 1.2 V A-port input, B-port output pF CL = 0, f = 10 MHz, tr = tf = 1 ns B-port input, A-port output UNIT pF Power dissipation capacitance per transceiver POWER-UP CONSIDERATIONS A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies. To guard against such power-up problems, take the following precautions: 1. Connect ground before any supply voltage is applied. 2. Power up VCCA. 3. VCCB can be ramped up along with or after VCCA. Table 1. Typical Total Static Power Consumption (ICCA + ICCB) VCCB VCCA 0V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 0V 0 <0.5 <0.5 <0.5 <0.5 <0.5 1.2 V <0.5 <1 <1 <1 <1 1 1.5 V <0.5 <1 <1 <1 <1 1 1.8 V <0.5 <1 <1 <1 <1 <1 2.5 V <0.5 1 <1 <1 <1 <1 3.3 V <0.5 1 <1 <1 <1 <1 UNIT µA 9 SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES582D – JULY 2004 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25°C, VCCA = 1.2 V 6 5 tPLH - ns 4 3 2 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V 1 VCCB = 2.5 V VCCB = 3.3 V 0 0 10 20 30 40 50 60 CL - pF Figure 1. 6 5 tPHL - ns 4 3 2 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V 1 VCCB = 2.5 V VCCB = 3.3 V 0 0 10 20 30 CL - pF 40 Figure 2. CL - pF - 1.5 10 50 60 60 SCES582D – JULY 2004 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25°C, VCCA = 1.5 V 6 5 tPLH - ns 4 3 2 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V 1 VCCB = 2.5 V VCCB = 3.3 V 0 0 10 20 30 40 50 60 60 CL - pF Figure 3. 6 5 4 tPHL - ns www.ti.com SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 3 2 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V 1 VCCB = 2.5 V VCCB = 3.3 V 0 0 10 20 30 CL - pF 40 50 60 Figure 4. CL - pF - 1.5 11 SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES582D – JULY 2004 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25°C, VCCA = 1.8 V 6 5 tPLH - ns 4 3 2 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V 1 VCCB = 2.5 V VCCB = 3.3 V 0 0 10 20 30 40 50 60 CL - pF Figure 5. 6 5 tPHL - ns 4 3 2 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V 1 VCCB = 2.5 V VCCB = 3.3 V 0 0 10 20 30 CL - pF 40 Figure 6. CL - pF - 1.5 12 50 60 60 SCES582D – JULY 2004 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25°C, VCCA = 2.5 V 6 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V 5 VCCB = 2.5 V VCCB = 3.3 V tPLH - ns 4 3 2 1 0 0 10 20 30 40 50 60 40 50 60 60 CL - pF Figure 7. 6 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V 5 VCCB = 2.5 V VCCB = 3.3 V 4 tPHL - ns www.ti.com SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 3 2 1 0 0 10 20 30 CL - pF Figure 8. CL - pF - 1.5 13 SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES582D – JULY 2004 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25°C, VCCA = 3.3 V 6 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V 5 VCCB = 2.5 V VCCB = 3.3 V tPLH - ns 4 3 2 1 0 0 10 20 30 40 50 60 40 50 60 CL - pF Figure 9. 6 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V 5 VCCB = 2.5 V VCCB = 3.3 V tPHL - ns 4 3 2 1 0 0 10 20 30 CL - pF Figure 10. CL - pF - 1.5 14 60 SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES582D – JULY 2004 – REVISED AUGUST 2005 PARAMETER MEASUREMENT INFORMATION 2 × VCCO S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCCO GND RL tw LOAD CIRCUIT VCCI VCCI/2 Input VCCO CL RL VTP 1.2 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 15 pF 15 pF 15 pF 15 pF 15 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 2 kΩ 0.1 V 0.1 V 0.15 V 0.15 V 0.3 V VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCCA Output Control (low-level enabling) VCCA/2 VCCA/2 0V tPZL VCCI Input VCCI/2 VCCI/2 0V tPLH Output tPHL VCCO/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOH VCCO/2 VOL tPLZ VCCO Output Waveform 1 S1 at 2 × VCCO (see Note B) VCCO/2 VOL + VTP VOL tPZH Output Waveform 2 S1 at GND (see Note B) tPHZ VCCO/2 VOH - VTP VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. VCCI is the VCC associated with the input port. I. VCCO is the VCC associated with the output port. Figure 11. Load Circuit and Voltage Waveforms 15 SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES582D – JULY 2004 – REVISED AUGUST 2005 APPLICATION INFORMATION Figure 12 is an example of the SN74AVCH2T45 circuit used in a bidirectional logic level-shifting application. VCC1 VCC2 VCC1 VCC2 1 8 2 7 3 6 4 5 VCC2 VCC1 SYSTEM-1 SYSTEM-2 Figure 12. Bidirectional Logic Level-Shifting Application 16 PIN NAME FUNCTION 1 VCCA VCC1 SYSTEM-1 supply voltage (1.2 V to 3.6 V) 2 A1 OUT1 Output level depends on VCC1 voltage. 3 A2 OUT2 Output level depends on VCC1 voltage. 4 GND GND Device GND 5 DIR DIR GND (low level) determines B-port to A-port direction. 6 B2 IN2 Input threshold value depends on VCC2 voltage. Input threshold value depends on VCC2 voltage. 7 B1 IN1 8 VCCB VCC2 DESCRIPTION SYSTEM-2 supply voltage (1.2 V to 3.6 V) SN74AVCH2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES582D – JULY 2004 – REVISED AUGUST 2005 APPLICATION INFORMATION Figure 13 shows the SN74AVCH2T45 used in a bidirectional logic level-shifting application. Since the SN74AVCH2T45 does not have an output-enable (OE) pin, system designers should take precautions to avoid bus contention between SYSTEM-1 and SYSTEM-2 when changing directions. VCC1 VCC1 VCC2 VCC2 I/O-1 I/O-2 1 8 2 7 3 6 4 5 DIR CTRL SYSTEM-1 SYSTEM-2 Figure 13. Bidirectional Logic Level-Shifting Application Following is a sequence that shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1. STATE DIR CTRL I/O-1 I/O-2 DESCRIPTION 1 H Out In 2 H Hi-Z Hi-Z SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on bus hold. 3 L Hi-Z Hi-Z DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on bus hold. 4 L Out In SYSTEM-1 data to SYSTEM-2 SYSTEM-2 data to SYSTEM-1 Enable Times Calculate the enable times for the SN74AVCH2T45 using the following formulas: • tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A) • tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A) • tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B) • tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74AVCH2T45 initially is transmitting from A to B, the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 17 PACKAGE OPTION ADDENDUM www.ti.com 7-Feb-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74AVCH2T45DCURE4 ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AVCH2T45DCUTE4 ACTIVE US8 DCU 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AVCH2T45DCTR ACTIVE SM8 DCT 8 3000 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM SN74AVCH2T45DCTT ACTIVE SM8 DCT 8 250 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM SN74AVCH2T45DCUR ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AVCH2T45DCUT ACTIVE US8 DCU 8 250 CU NIPDAU Level-1-260C-UNLIM SN74AVCH2T45YEPR PREVIEW WCSP YEP 8 3000 TBD Call TI SN74AVCH2T45YZPR ACTIVE WCSP YZP 8 3000 Pb-Free (RoHS) SNAGCU Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) Call TI Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 MECHANICAL DATA MPDS049B – MAY 1999 – REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0° – 8° 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. B. C. D. 4188781/C 09/02 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion Falls within JEDEC MO-187 variation DA. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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