TI SN75ALS171

SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
DW OR J PACKAGE
(TOP VIEW)
Three Bidirectional Transceivers
Driver Meets or Exceeds the Requirements
of ANSI EIA/TIA-422-B and RS-485 and ITU
Recommendation V.11
Two Skew Limits Available
Designed to Operate Up to 20 Million Data
Transfers per Second (FAST-20 SCSI)
High-Speed Advanced Low-Power Schottky
Circuitry
Low Pulse Skew . . . 5 ns Max
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
Features Independent Driver Enables and
Combined Receiver Enables
Wide Positive and Negative Input/Output
Bus Voltages Ranges
Driver Output Capacity . . . ± 60 mA
Thermal Shutdown Protection
Driver Positive- and Negative-Current
Limiting
Receiver Input Impedances . . . 12 kΩ Min
Receiver Input Sensitivity . . . ± 300 mV Max
Receiver Input Hysteresis . . . 60 mV Typ
Operates From a Single 5-V Supply
Glitch-Free Power-Up and Power-Down
Protection
1R
1DE
1D
GND
GND
2R
2DE
2D
3R
3DE
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
1B
1A
RE
CDE
VCC
2B
2A
3B
3A
3D
description
The SN75ALS171 and the SN75ALS171A triple differential bus transceivers are monolithic integrated circuits
designed for bidirectional data communication on multipoint bus transmission lines. They are designed for
balanced transmission lines, and each driver meets ANSI Standards EIA/TIA-422-B and RS-485 and both the
drivers and receivers meet ITU Recommendation V.11. The SN75ALS171A is designed for FAST-20 SCSI and
can transmit or receive data pulses as short as 30 ns with a maximum skew of 5 ns.
The SN75ALS171 and the SN75ALS171A operate from a single 5-V power supply. The drivers and receivers
have individual active-high and active-low enables, respectively, which can be externally connected together
to function as a direction control. The driver differential output and the receiver differential input pairs are
connected internally to form differential input/output (I/O) bus ports that are designed to offer minimum loading
to the bus when the driver is disabled or VCC is at 0 V. These ports feature wide positive and negative
common-mode voltage ranges making the device suitable for party-line applications.
The SN75ALS171 and the SN75ALS171A are characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
Function Tables
EACH DRIVER
ENABLES
OUTPUTS
INPUT
D
DE
CDE
A
H
H
H
H
L
L
H
H
L
H
X
L
X
Z
Z
X
X
L
Z
Z
B
EACH RECEIVER
DIFFERENTIAL INPUTS
A–B
ENABLE
RE
OUTPUT
R
VID ≥ 0.3 V
– 0.3 V < VID < 0.3 V
L
H
L
?
VID ≤ – 0.3 V
X
L
L
H
Z
Open
L
H
H = high level, L = low level, ? = indeterminate, X = irrelevant,
Z = high impedance (off)
AVAILABLE OPTIONS
SKEW LIMIT
10 ns
5 ns
2
PART NUMBER
SN75ALS171DW
SN75ALS171J
SN75ALS171ADW
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
logic symbol†
CDE
1DE
2DE
3DE
RE
1D
1R
2D
2R
3D
3R
17
2
7
10
18
logic diagram (positive logic)
CDE
G5
1DE
5EN1
1D
5EN2
RE
5EN3
1R
EN4
19
1
3
1
4
14
2
2B
3DE
3D
19 1A
20 1B
3
18
7
14
8
15
2A
2B
Bus
6
10
12
11
13
3A
3B
Bus
3A
13
3
Bus
1
12
3
4
2R
1
11
9
2D
2A
15
2
4
2DE
1B
2
1
8
6
1A
20
1
17
3B
3R
9
1
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC
TYPICAL OF A AND B I/O PORTS
TYPICAL OF RECEIVER OUTPUT
VCC
R(eq)
Input
180 kΩ
NOM
Connected
on A Port
A or B
18 kΩ
NOM
Driver Input: R(eq) = 12 kΩ NOM
Enable Inputs: R(eq) = 8 kΩ NOM
R(eq) = equivalent resistor
85 Ω
NOM
180 kΩ
NOM
Connected
on B Port
POST OFFICE BOX 655303
3 kΩ
NOM
VCC
Output
1.1 kΩ
NOM
• DALLAS, TEXAS 75265
3
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 7 V to 12 V
Enable input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW package . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
DW
1125 mW
9.0 mW/°C
720 mW
J
1025 mW
8.2 mW/°C
656 mW
recommended operating conditions
Supply voltage, VCC
Voltage at any bus terminal (separately or common mode), VI or VIC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
12
V
–7
High-level input voltage, VIH
D, CDE, DE, and RE
Low-level input voltage, VIL
D, CDE, DE, and RE
2
Differential input voltage, VID (see Note 2)
Driver
High level output current,
current IOH
High-level
V
0.8
Receiver
±12
V
– 60
mA
– 400
µA
Driver
Low level output current,
Low-level
current IOL
60
Receiver
Operating free-air temperature, TA
8
0
NOTE 2: Differential-input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
70
mA
°C
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST CONDITIONS†
PARAMETER
VIK
VO
Input clamp voltage
VOH
High-level output voltage
VCC = 4.75 V,
VIL = 0.8 V,
VIH = 2 V,
IOH = – 55 mA
VOL
Low-level output voltage
VCC = 4.75 V,
VIL = 0.8 V,
VIH = 2 V,
IOL = 55 mA
| VOD1 |
Differential output voltage
IO = 0
| VOD2 |
II = – 18 mA
IO = 0
Output voltage
g
Differential output voltage
VOD3
Differential output voltage
∆ | V OD|
Change in magnitude of differential
output voltage¶
VOC
Common mode output voltage
Common-mode
∆ | V OC |
Change in magnitude of common-mode
output voltage¶
IO
Output current
IIH
High level enable
High-level
enable-input
input current
IIL
IOS
ICC
Low level enable-input
Low-level
enable input current
Short circuit output current
Short-circuit
Supply current
MIN
TYP‡
0
UNIT
– 1.5
V
6
V
2.7
V
1.5
RL = 100 Ω,
See Figure 1
1/2 VOD1
or 2§
RL = 54 Ω,
See Figure 1
1.5
Vtest = – 7 V to 12 V,
See Figure 2
1.5
RL = 54 Ω or 100 Ω
Ω,
MAX
1.7
V
6
V
2.5
5
2.5
5
5
V
± 0.2
V
3
See Figure 1
–1
± 0.2
Output disabled,,
See Note 3
D and DE
CDE
D and DE
CDE
VO = 12 V
VO = – 7 V
1
– 0.8
V
V
mA
20
VIH = 2
2.7
7V
60
– 100
VIL = 0
0.4
4V
µA
– 900
VO = – 6 V
VO = 0
– 250
VO = VCC
VO = 8 V
250
No load
V
– 150
mA
250
Outputs enabled
69
90
Outputs disabled
57
78
mA
† The power-off measurement in ANSI Standard EIA/TIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.
‡ All typical values are at VCC = 5 V and TA = 25°C.
§ The minimum VOD2 with 100-W load is either 1/2 VOD2 or 2 V, whichever is greater.
¶ ∆ | V OD| and ∆ | V OC | are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a
low level.
NOTE 3: This applies for both power on and off; refer to EIA Standard RS-485 for exact conditions. The EIA/TIA-422-B limit does not apply for
a combined driver and receiver terminal.
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SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ALS171
ALS171A
td(OD)
Differential output delay time
ALS171
ALS171A
tsk(p)
k( )
Pulse skew‡
ALS171
tsk(lim)
k(li )
ALS171A
Skew limit§
ALS171
ALS171A
tt(OD)
Differential-output transition time
MIN
TYP†
MAX
UNIT
RL = 54 Ω,,
CL = 50 pF
See Figure
g
3,,
RL1 = RL3 = 165 Ω,
CL = 60 pF,
pF
RL2 = 75 Ω,
VTERM = 5 V,
See Figure 6
RL = 54 Ω,
See Figure 3
CL = 50 pF,
RL1 = RL3 = 165 Ω,
CL = 60 pF,
RL2 = 75 Ω,
See Figure 6
RL = 54 Ω,,
See Figure 3
CL = 50 pF,,
RL1 = RL3 = 165 Ω,,
CL = 60 pF,
RL2 = 75 Ω,,
See Figure 6
RL = 54 Ω,
See Figure 3
CL = 50 pF,
3
8
13
RL1 = RL3 = 165 Ω,
CL = 60 pF,
See Figure 6
RL2 = 75 Ω,
VTERM = 5 V,
3
8
13
30
50
ns
3
13
6
11
3
13
6
11
ns
1
5
ns
1
5
ns
10
5
10
ns
5
ns
tPZH
tPZL
Output enable time to high level
RL = 110 Ω,
See Figure 4
Output enable time to low level
RL = 110 Ω,
See Figure 5
30
50
ns
tPHZ
tPLZ
Output disable time from high level
RL = 110 Ω,
See Figure 4
3
8
13
ns
Output disable time from low level
RL = 110 Ω,
See Figure 5
3
8
13
ns
tPDE
Differential-output enable time
8
30
45
ns
RL1 = RL3 = 165 Ω,
RL2 = 75 Ω,
CL = 60 pF,
See Figure 7
tPDZ
Differential-output disable time
5
10
45
ns
† All typical values are at VCC = 5 V and TA = 25°C.
‡ Pulse skew is defined as the | td(ODH) – td(ODL) | of each channel.
§ Skew limit is the maximum difference in propagation delay times between any two channels of one device and between any two devices. This
parameter is applicable at one VCC and operating temperature within the recommended operating conditions.
SYMBOL EQUIVALENTS
DATA-SHEET PARAMETER
EIA/TIA-422-B
RS-485
VO
| VOD1 |
Voa, Vob
Vo
Voa, Vob
Vo
| VOD2 |
Vt (RL = 100 Ω)
| VOD3 |
Vt (RL = 54 Ω)
Vt (Test Termination
Measurement 2)
Vtest
∆ | V OD |
||V t|–|V t||
Vtst
||V t|–|V t||
| Vos |
| Vos |
| Vos – Vos |
| Vos – Vos |
VOC
∆ | V OC |
IOS
IO
6
| I sa |, | Isb |
| I xa |, | Ixb |
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Iia, Iib
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
VIT +
VIT –
Positive-going input threshold voltage
Vhys
VIK
Hysteresis voltage (VIT + – VIT –)
TEST CONDITIONS
Negative-going input threshold voltage
VO = 2.7 V,
VO = 0.5 V,
IO = – 0.4 mA
IO = 8 mA
MIN
TYP†
MAX
0.3
– 0.3 ‡
II = – 18 mA
VID = 300 mV,
See Figure 8
VOH
High-level output voltage
VOL
Low-level output voltage
VID = – 300 mV,
See Figure 8
IOZ
High-impedance-state output current
VO = 0.4 V to 2.4 V
Other input = 0 V,,
See Note 4
II
Line input current
IIH
IIL
High-level enable-input current
ri
Input resistance
IOS
Short-circuit output current
VID = 300 mV,
ICC
Supply current
No load
2.7
IOL = 8 mA,
VI = 12 V
VI = – 7 V
0.45
V
± 20
µA
1
– 0.8
60
– 300
12
VO = 0
Outputs enabled
mA
µA
µA
kΩ
– 15
Outputs disabled
V
V
VIH = 2.7 V
VIL = 0.4 V
Low-level enable-input current
mV
– 1.5
IOH = – 400 µA,
V
V
60
Enable-input clamp voltage
UNIT
– 85
69
90
57
78
mA
mA
† All typical values are at VCC = 5 V and TA = 25°C.
‡ The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 4: This applies for both power on and off; refer to EIA Standard RS-485 for exact conditions.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time,
time lowlow to high-level
high level output
tPHL
Propagation delay time,
time highhigh to low-level
low level output
tsk(p)
Pulse skew§
tsk(lim)
k(li )
Ske limit¶
Skew
tPZH
tPZL
Output enable time to high level
ALS171
ALS171A
ALS171
ALS171A
ALS171
ALS171A
Output enable time to low level
VID = – 1
1.5
5 V to 1.5
1 5 V,
V
CL = 15 pF,,
TA = 25°C,
See
9
S Figure
Fi
MIN
TYP†
MAX
9
19
11
16
9
19
11
16
5
UNIT
ns
ns
VID = – 1.5 V to 1.5 V,
CL = 15 pF,
See Figure 9
2
CL = 15 pF,,
See Figure 10
7
14
ns
7
14
ns
10
5
ns
ns
tPHZ
Output disable time from high level
20
35
ns
CL = 15 pF,
See Figure 10
tPLZ
Output disable time from low level
8
17
ns
† All typical values are at VCC = 5 V and TA = 25°C.
§ Pulse skew is defined as the | tPLH – t PHL| of each channel.
¶ Skew limit is the maximum difference in propagation delay times between any two channels of one device and between any two devices. This
parameter is applicable at one VCC and operating temperature within the recommended operating conditions.
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SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
RL
2
VOD2
RL
2
VOC
Figure 1. Driver VOD and VOC
375 Ω
VOD3
60 Ω
Vtest
375 Ω
Figure 2. Driver VOD3
3V
RL = 54 Ω
Generator
(see Note A)
CL= 50 pF
(see Note B)
Output
50 Ω
1.5 V
Input
1.5 V
0V
td(ODL)
td(ODH)
≈ 2.5 V
90% 90%
Output
3V
50%
10%
tt(OD)
TEST CIRCUIT
50%
10%
≈ – 2.5 V
tt(OD)
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 3. Driver Test Circuit and Voltage Waveforms
8
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SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
Output
3V
S1
1.5 V
0V
RL = 110 Ω
CL = 50 pF
(see Note B)
Generator
(see Note A)
1.5 V
Input
0 V or 3 V
tPZH
0.5 V
VOH
50 Ω
Output
2.3V
tPHZ
TEST CIRCUIT
Voff ≈ 0 V
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 4. Driver Test Circuit and Voltage Waveforms
5V
3V
RL = 110 Ω
S1
Input
1.5 V
1.5 V
Output
0V
0 V or 3 V
CL = 50 pF
(see Note B)
Generator
(see Note A)
50 Ω
tPZL
tPLZ
2.3 V
Output
5V
0.5 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 5. Driver Test Circuit and Voltage Waveforms
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SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
5V
S1
0V
CL = 60 pF
(see Note B)
RL1 = 165 Ω
Generator
(see Note A)
RL 2 = 75 Ω
Output
RL 3 = 165 Ω
CL = 60 pF
(see Note B)
50 Ω
3V
5V
0V
S2
TEST CIRCUIT
3V
Input
1.5 V
1.5 V
0V
td(ODL)
td(ODH)
Output
S1 to 5 V
S2 to 0 V
0V
10%
90% 90%
3V
Input
1.5 V
≈ – 2.9 V
tt(OD)
tt(OD)
Output
0V
10%
90% 90%
≈ 2.3 V
0V
10%
tt(OD)
VOLTAGE WAVEFORMS
S1 to 0 V
S2 to 5 V
0V
td(ODL)
td(ODH)
≈ 2.9 V
0V
10%
1.5 V
≈ – 2.9 V
tt(OD)
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 6. Driver Test Circuit and Voltage Waveforms
With Double-Differential-SCSI Termination for the Load
10
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• DALLAS, TEXAS 75265
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
5V
S2
0V
CL = 60 pF
(see Note B)
RL1 = 165 Ω
Generator
(see Note A)
RL 2 = 75 Ω
Output
RL 3 = 165 Ω
CL = 60 pF
(see Note B)
50 Ω
3V
5V
0V
3V
Input
1.5 V
1.5 V
0V
tPZH
S3
S1 to 3 V
S2 to 0 V
S3 to 5 V
0V
1.5 V
1.5 V
0V
tPZL
≈ 2.3 V
tPZL
≈–1V
Output
Output
0V
3V
Input
S1 to 0 V
S2 to 5 V
S3 to 0 V
tPZH
0V
0V
≈1V
≈ – 2.3 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 7. Driver Differential-Enable and Disable Times With a Double-SCSI Termination
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SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
VID
VOH
+ IOL
– IOH
VOL
Figure 8. Receiver VOH and VOL
3V
Generator
(see Note A)
Output
Input
1.5 V
1.5 V
51 Ω
0V
1.5 V
tPLH
CL = 15 pF
(see Note B)
0V
tPHL
VOH
Output
1.3 V
1.3 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 9. Receiver Test Circuit and Voltage Waveforms
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
S1
1.5 V
2 kΩ
– 1.5 V
S2
5V
CL = 15 pF
(see Note B)
Generator
(see Note A)
5 kΩ
1N916 or Equivalent
50 Ω
S3
TEST CIRCUIT
3V
Input
3V
S1 to 1.5 V
S2 Open
S3 Closed
1.5 V
Input
1.5 V
0V
tPZH
tPZL
VOH
Output
1.5 V
0V
S1 to – 1.5 V
0 V S2 Closed
S3 Open
≈ 4.5 V
Output
1.5 V
VOL
3V
Input
1.5 V
0V
3V
S1 to 1.5 V
S2 Closed
S3 Closed
Input
1.5 V
0V
tPHZ
tPLZ
≈ 1.3 V
VOH
Output
S1 to – 1.5 V
S2 Closed
S3 Closed
0.5 V
Output
0.5 V
≈ 1.3 V
VOL
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 10. Receiver Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
DRIVER
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
5
VCC = 5 V
TA = 25°C
VCC = 5 V
TA = 25°C
4.5
VOL – Low-Level Output Voltage – V
VOH – High-Level Output Voltage – V
4.5
4
3.5
3
2.5
2
1.5
1
0.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
0
– 80
– 100
– 20
– 40
– 60
IOH – High-Level Output Current – mA
– 120
0
80
100
20
40
60
IOL – Low-Level Output Current – mA
Figure 11
Figure 12
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VOD – Differential Output Voltage – V
4
VCC = 5 V
TA = 25°C
3.5
3
2.5
2
1.5
1
0.5
0
0
10
20
30 40 50 60 70 80
IO – Output Current – mA
Figure 13
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
90
100
120
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
RECEIVER
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
VID = 0.3 V
TA = 25°C
4.5
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
5
4
3.5
3
VCC = 5.25 V
2.5
VCC = 5 V
2
1.5
VCC = 4.75 V
1
0.5
4.5
4
VCC = 5 V
VID = 300 mV
IOH = – 440 µA
3.5
3
2.5
2
1.5
1
0.5
0
– 40
0
0
– 40
–10
– 20
– 30
IOH – High-Level Output Current – mA
– 50
– 20
0
20
40
60
80
TA – Free-Air Temperature – °C
Figure 14
120
Figure 15
RECEIVER
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
0.6
VCC = 5 V
TA = 25°C
VID = – 300 mV
0.5
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
100
0.4
0.3
0.2
0.1
0
0
5
10
15
20
25
IOL – Low-Level Output Current – mA
30
0.5
VCC = 5 V
VID = – 300 mA
IOL = 8 mA
0.4
0.3
0.2
0.1
0
– 40
– 20
0
20
40
60
80
100
TA – Free-Air Temperature – °C
Figure 16
120
Figure 17
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
RECEIVER
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
5
6
VID = 0.3 V
Load = 8 kΩ to GND
TA = 25°C
VCC = 5.25 V
VO – Output Voltage – V
4
3.5
VCC = 4.75 V
3
VID = 0.3 V
Load = 1 kΩ to VCC
TA = 25°C
5
VO – Output Voltage – V
4.5
VCC = 5 V
2.5
2
1.5
1
VCC = 5.25 V
VCC = 4.75 V
4
VCC = 5 V
3
2
1
0.5
0
0
0
0.5
1
1.5
2
2.5
3
0
0.5
VI – Enable Voltage – V
Figure 18
16
1
1.5
2
VI – Enable Voltage – V
Figure 19
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2.5
3
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
APPLICATION INFORMATION
1/3 SN75ALS170
1/3 SN75ALS170
See Note A
Up to 32
Transceivers
• • •
NOTE A: The line should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short
as possible.
Figure 20. Typical Application Circuit
4 V to 5.25 V
4 V to 5.25 V
330 Ω
330 Ω
150 Ω
150 Ω
330 Ω
330 Ω
Up to 16
Transceivers
• • •
Figure 21. Typical Differential SCSI Application CIrcuit
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
APPLICATION INFORMATION
1
2
4
5
9
10
12
13
VCC
15
14
13
12
11
10
9
7
1 BIN/OCT
2
3
6
4
5
&
&
2
1
8
EN
5
4
&
3
EN
7
6
6
2
1
EN
5
4
2
4
6
8
10
12
1
SN74LS04
7
6
EN
EN
EN
1
8
9
EN
5
4
10 DB(0)
11
–DB(0)
1
8
9
EN
10 ATN
11
–ATN
1
8
9
EN
5
4
EN
10 I/O
11
–I/O
1
8
9
EN
VCC
17
2
7
10
18
EN
1
19 BSY
20
–BSY
1
14 SEL
15
–SEL
8
6
1
12 RST
13
–RST
11
To Reset Logic
9
1
SN75ALS171
Figure 22. Typical Differential SCSI Bus Interface Implementation
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
REQ
–REQ
SN75ALS170
G5
5EN1
5EN2
5EN3
EN4
3
1
13 C/D
14
–C/D
1
EN
7
6
MSG
–MSG
1
SN75ALS170
EN
2
1
13 ACK
14
–ACK
1
EN
EN
DB(P)
–DB(P)
1
EN
7
6
13 DB(1)
14
–DB(1)
1
SN75ALS170
EN
2
1
DB(2)
–DB(2)
1
EN
EN
To SCSI Bus
Controller
10 DB(3)
11
–DB(3)
EN
7
6
13 DB(4)
14
–DB(4)
1
SN75ALS170
EN
2
1
DB(5)
–DB(5)
1
EN
5
4
SB7
SB6
SB5
SB4
SB3
SB2
SB1
SB0
SBP
INIT
ACK
ATN
TARGET
MSG
C/D
I/O
REQ
BSYOUT
BSYIN
SELOUT
SELIN
SBEN
ARB
8
9
EN
EN
1
3
5
9
11
13
1
SN75ALS170
EN
11
SN74LS00
10 DB(6)
11
–DB(6)
EN
EN
8
1
EN
11
1
2
4
5
9
10
12
13
13 DB(7)
14
–DB(7)
EN
6
SN74LS00
SN74LS138
ID0
ID1
ID2
3
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN75ALS171ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75ALS171ADWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75ALS171ADWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75ALS171ADWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75ALS171DW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75ALS171DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75ALS171DWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75ALS171DWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75ALS171J
OBSOLETE
CDIP
J
20
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
30-Apr-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN75ALS171ADWR
DW
20
TAI
330
24
10.8
13.1
2.65
12
24
Q1
SN75ALS171DWR
DW
20
TAI
330
24
10.8
13.1
2.65
12
24
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN75ALS171ADWR
DW
20
TAI
346.0
346.0
41.0
SN75ALS171DWR
DW
20
TAI
346.0
346.0
41.0
Pack Materials-Page 2
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