ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 DUAL DIGITAL ISOLATORS FEATURES • • • 1, 25, and 150-Mbps Signaling Rate Options – Low Channel-to-Channel Output Skew; 1 ns max – Low Pulse-Width Distortion (PWD); 1 ns max – Low Jitter Content; 1 ns Typ at 150 Mbps Typical 25-Year Life at Rated Voltage (see app. note SLLA197 and Figure 19) 4000-Vpeak Isolation, 560 V peak VIORM – UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2), IEC 61010-1 – 50 kV/μs Typical Transient Immunity • • • • Operates with 3.3-V or 5-V Supplies 4 kV ESD Protection High Electromagnetic Immunity –40°C to 125°C Operating Range APPLICATIONS • • • • Industrial Fieldbus – Modbus – Profibus™ – DeviceNet™ Data Buses Computer Peripheral Interface Servo Control Interface Data Acquisition DESCRIPTION The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are oriented in the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a logic input and output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to 4000 V. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, and prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received every 4 μs, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state. The small capacitance and resulting time constant provide very fast operation with signaling rates available from 0 Mbps (DC) to 150 Mbps. (1)The A- and C-option devices have TTL input thresholds and a noise filter at the input that prevents transient pulses from being passed to the output of the device. The M-option devices have CMOS Vcc/2 input thresholds and do not have the input noise-filter and the additional propagation delay. These devices require two supply voltages of 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when supplied from a 3.3-V supply and all outputs are 4-mA CMOS. These devices are characterized for operation over the ambient temperature range of –40°C to 125°C. (1) 1 INA INB 2 GND1 4 3 8 Isolation VCC1 7 6 5 VCC2 OUTA OUTB GND2 VCC1 1 OUTA INB 2 GND1 4 3 Isolation ISO7221xD ISO7220xD 8 VCC2 7 INA OUTB GND2 6 5 The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DeviceNet is a trademark of Open DeviceNet Vendors Association. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. SINGLE-CHANNEL FUNCTION DIAGRAM Galvanic Isolation Barrier DC Channel Filter OSC + PWM IN Pulse Width Demodulation Vref Carrier Detect Input + Filter Data MUX AC Detect Vref OUT Output Buffer AC Channel AVAILABLE OPTIONS PRODUCT SIGNALING RATE PACKAGE INPUT THRESHOLD CHANNEL DIRECTION MARKED AS ISO7220A 1 Mbps SOIC-8 ≈ 1.5 V (TTL) (CMOS compatible) ISO7220C 25 Mbps SOIC-8 ≈ 1.5 V (TTL) (CMOS compatible) ISO7220M 150 Mbps SOIC-8 VCC/2 (CMOS) I7220M ISO7221A 1 Mbps SOIC-8 ≈ 1.5 V (TTL) (CMOS compatible) I7221A ISO7221C 25 Mbps SOIC-8 ≈ 1.5 V (TTL) (CMOS compatible) ISO7221M 150 Mbps SOIC-8 VCC/2 (CMOS) I7220A Same direction Opposite directions I7220C TI7221C I7221M ORDERING NUMBER ISO7220AD (rail) ISO7220ADR (reel) ISO7220CD (rail) ISO7220CDR (reel) ISO7220MD (rail) ISO7220MDR (reel) ISO7221AD (rail) ISO7221ADR (reel) ISO7221CD (rail) ISO7221CDR (reel) ISO7221MD (rail) ISO7221MDR (reel) REGULATORY INFORMATION VDE UL Certified according to IEC 60747-5-2 Recognized under 1577 Component Recognition Program (1) File Number: 40014131 File Number: 1698195 File Number: E181974 (1) 2 CSA Approved under CSA Component Acceptance Notice Production tested ≥3000 VRMS for 1 second in accordance with UL 1577. Submit Documentation Feedback ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 ABSOLUTE MAXIMUM RATINGS (2) VCC Supply voltage VI Voltage at IN, OUT IO Output current , VCC1, VCC2 Human Body Model Electrostatic discharge JEDEC Standard 22, Test Method A114-C.01 Field-Induced-Charged Device Model JEDEC Standard 22, Test Method C101 Machine Model ANSI/ESDS5.2-1996 ESD Electrostatic discharge TJ Maximum junction temperature (1) (2) (1) VALUE UNIT –0.5 to 6 V –0.5 to 6 V ±15 mA ±4 kV All pins ±1 ±200 V 170 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. RECOMMENDED OPERATING CONDITIONS MIN VCC Supply voltage, VCC1, VCC2 IOH High-level output current IOL Low-level output current tui 1/tui MAX 5.5 3 3.6 4 Input pulse width Signaling rate UNIT V mA –4 mA ISO722xA 1 μs ISO722xC 40 ISO722xM 6.67 5 ISO722xA 0 250 1000 ISO722xC 0 30 25 ISO722xM 0 200 (1) 150 VIH High-level input voltage VIL Low-level input voltage VIH High-level input voltage VIL Low-level input voltage TJ Junction temperature H External magnetic field-strength immunity per IEC 61000-4-8 & IEC 61000-4-9 certification (1) TYP 4.5 ISO722xA, ISO722xC ISO722xM ns kbps Mbps 2 VCC V 0 0.8 V 0.7 VCC VCC V 0 0.3 VCC V –40 150 °C 1000 A/m Typical sigalling rate under ideal conditions at 25°C. Submit Documentation Feedback 3 ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 5-V operatjion, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 1 2 8.5 17 UNIT SUPPLY CURRENT ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M ISO7220A ICC1 ISO7221A ISO7220C, ISO7220M ISO7221C, ISO7221M ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M ISO7220A ICC2 Quiescent 1 Mbps VI = VCC or 0 V, no load 25 Mbps VI = VCC or 0 V, no load Quiescent VI = VCC or 0 V, no load 1 Mbps ISO7221A ISO7220C, ISO7220M VOH High-level output voltage VOL Low-level output voltage VI = VCC or 0 V, no load 25 Mbps ISO7221C, ISO7221M VI = VCC or 0 V, no load VI = VCC or 0 V, no load 2 3 10 18 4 9 12 22 16 31 8.5 17 17 32 10 18 20 34 12 22 IOH = –4 mA, See Figure 1 VCC – 0.8 4.6 IOH = –20 μA, See Figure 1 VCC – 0.1 5 V IOL = 4 mA, See Figure 1 0.2 0.4 IOL = 20 μA, See Figure 1 0 0.1 VI(HYS) Input voltage hysteresis 150 IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 IN from 0 V to VCC V mV 10 –10 25 mA μA 1 pF 50 kV/μs SWITCHING CHARACTERISTICS VCC1 and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER tpLH, tpHL Propagation delay ISO722xA Pulse-width distortion |tpHL – tpLH| tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL – tpLH| (1) tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL – tpLH| (1) Part-to-part skew MIN TYP MAX 280 405 475 1 14 32 42 1 2 10 16 (1) PWD tsk(pp) TEST CONDITIONS ISO722xC See Figure 1 6 ISO722xM (2) 22 0.5 tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tfs Failsafe output delay time from input power loss (1) (2) (3) 4 ns 1 ISO722xA 180 ISO722xC 10 ISO722xM (3) UNIT ns 3 ISO7220A ISO7220C/M See Figure 1 See Figure 2 3 15 0.2 1 1 1 3 ns ns μs Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 SWITCHING CHARACTERISTICS (continued) VCC1 and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER tjit(pp) TEST CONDITIONS Peak-to-peak eye-pattern jitter ISO722xM MIN TYP 150 Mbps PRBS NRZ data, 5-bit max same polarity input, both channels, See Figure 4, Figure 16 1 150 Mbps unrestricted bit run length data input, both channels, See Figure 4 2 MAX UNIT ns ELECTRICAL CHARACTERISTICS VCC1 at 5 V, VCC2 at 3.3 V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M ICC1 ISO7220A ISO7221A ISO7220C, ISO7220M ISO7221C, ISO7221M ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M ICC2 ISO7220A ISO7221A ISO7220C, ISO7220M ISO7221C, ISO7221M VOH High-level output voltage Quiescent VI = VCC or 0 V, no load 1 Mbps VI = VCC or 0 V, no load 25 Mbps VI = VCC or 0 V, no load Quiescent VI = VCC or 0 V, no load 1 Mbps VI = VCC or 0 V, no load 25 Mbps VI = VCC or 0 V, no load ISO7220x IOH = –4 mA, See Figure 1 ISO7221x (5-V side) 1 2 8.5 17 2 3 10 18 4 9 12 22 8 18 4.3 9.5 9 19 5 11 10 20 6 12 VCC – 0.4 VCC – 0.8 IOH = –20 μA, See Figure 1 V VCC – 0.1 IOL = 4 mA, See Figure 1 0.4 IOL = 20 μA, See Figure 1 0.1 VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 150 IN from 0 V to VCC Submit Documentation Feedback mA mV 10 –10 15 V μA 1 pF 40 kV/μs 5 ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 SWITCHING CHARACTERISTICS VCC1 at 5 V, VCC2 at 3.3 V operation, over recommended operating conditions (unless otherwise noted) PARAMETER tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL – tpLH| tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL – tpLH| tpLH, tpHL Propagation delay PWD tsk(pp) Pulse-width distortion |tpHL – tpLH| Part-to-part skew TEST CONDITIONS ISO722xA MIN TYP MAX 285 410 480 1 14 36 48 1 2 12 20 (1) ISO722xC See Figure 1 25 (1) 7 ISO722xM (1) (2) 0.5 180 ISO722xC 10 3 15 0.2 1 tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tfs Failsafe output delay time from input power loss See Figure 2 3 1 Peak-to-peak eye-pattern jitter 150 Mbps PRBS NRZ data, 5-bit max same polarity input, both channels, See Figure 4, Figure 16 150 Mbps unrestricted bit run length data input, both channels, See Figure 4 2 tjit(pp) (1) (2) (3) 6 (3) 5 ISO7220A ISO7220C/M See Figure 1 ISO722xM 2 2 ns 1 ISO722xA ISO722xM UNIT ns ns μs ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 ELECTRICAL CHARACTERISTICS VCC1 at 3.3 V, VCC2 at 5 V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M ISO7220A ICC1 ISO7221A ISO7220C, ISO7220M ISO7221C, ISO7221M ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M ISO7220A ICC2 Quiescent VI = VCC or 0 V, no load 1 Mbps VI = VCC or 0 V, no load 25 Mbps VI = VCC or 0 V, no load Quiescent VI = VCC or 0 V, no load 1 Mbps ISO7221A ISO7220C, ISO7220M 25 Mbps ISO7221C, ISO7221M VI = VCC or 0 V, no load VI = VCC or 0 V, no load ISO7220x VOH ISO7221x (3.3-V side) High-level output voltage 0.6 1 4.3 9.5 1 2 5 11 2 4 6 12 16 31 8.5 17 18 32 10 18 20 34 12 22 mA VCC – 0.8 IOH = –4 mA, See Figure 1 IOH = –20 μA, See Figure 1 VCC – 0.4 V VCC – 0.1 IOL = 4 mA, See Figure 1 VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 0.4 IOL = 20 μA, See Figure 1 0 0.1 150 IN from 0 V or VCC mV 10 –10 15 μA 1 pF 40 kV/μs SWITCHING CHARACTERISTICS VCC1 at 3.3 V, VCC2 at 5 V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL – tpLH| (1) tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL – tpLH| tpLH, tpHL Propagation delay PWD tsk(pp) Pulse-width distortion |tpHL – tpLH| Part-to-part skew ISO722xA ISO722xC See Figure 1 MIN TYP MAX 285 395 480 1 18 36 48 1 3 12 21 25 (1) ISO722xM 7 (1) (2) 0.5 190 ISO722xC 10 ISO722xM (3) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tfs Failsafe output delay time from input power loss (3) ns 5 ISO7220A tsk(o) (1) (2) 1 ISO722xA UNIT ISO7220C/M See Figure 1 See Figure 2 3 15 0.2 1 1 1 3 μs Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback 7 ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 SWITCHING CHARACTERISTICS (continued) VCC1 at 3.3 V, VCC2 at 5 V operation, over recommended operating conditions (unless otherwise noted) PARAMETER tjit(pp) Peak-to-peak eye-pattern jitter TEST CONDITIONS ISO722xM MIN TYP 150 Mbps PRBS NRZ data, 5-bit max same polarity input, both channels, See Figure 4, Figure 16 1 150 Mbps unrestricted bit run length data input, both channels, See Figure 4 2 MAX UNIT ns ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 3.3 V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M ICC1 ISO7220A ISO7221A ISO7220C, ISO7220M ISO7221C, ISO7221M ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M ICC2 ISO7220A ISO7221A ISO7220C, ISO7220M ISO7221C, ISO7221M VOH 8 High-level output voltage Quiescent VI = VCC or 0 V, no load 1 Mbps VI = VCC or 0 V, no load 25 Mbps VI = VCC or 0 V, no load Quiescent VI = VCC or 0 V, no load 1 Mbps VI = VCC or 0 V, no load 25 Mbps VI = VCC or 0 V, no load 0.6 1 4.3 9.5 1 2 5 11 2 4 6 12 8 18 4.3 9.5 9 19 5 11 10 20 6 12 IOH = –4 mA, See Figure 1 VCC – 0.4 3 IOH = –20 μA, See Figure 1 VCC – 0.1 3.3 IOL = 4 mA, See Figure 1 VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 IOL = 20 μA, See Figure 1 0.2 0.4 0 0.1 150 IN from 0 V or VCC Submit Documentation Feedback 15 V mV 10 –10 mA μA 1 pF 40 kV/μs ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 SWITCHING CHARACTERISTICS VCC1 and VCC2 at 3.3 V operation, over recommended operating conditions (unless otherwise noted) PARAMETER tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL – tpLH| tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL – tpLH| tpLH, tpHL Propagation delay PWD tsk(pp) Pulse-width distortion |tpHL – tpLH| TEST CONDITIONS ISO722xA MIN TYP MAX 290 400 485 1 18 40 52 1 3 16 25 (1) ISO722xC See Figure 1 26 (1) 8 ISO722xM (1) Part-to-part skew (2) 0.5 190 ISO722xC 10 ISO722xM (3) 3 15 0.2 1 Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tfs Failsafe output delay time from input power loss See Figure 2 3 1 Peak-to-peak eye-pattern jitter 150 Mbps PRBS NRZ data, 5-bit max same polarity input, both channels, See Figure 4, Figure 16 150 Mbps unrestricted bit run length data input, both channels, See Figure 4 2 (1) (2) (3) ISO7220C/M See Figure 1 ISO722xM ns 5 ISO7220A tsk(o) tjit(pp) 1 ISO722xA UNIT 2 2 μs ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback 9 ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 ISOLATION BARRIER PARAMETER MEASUREMENT INFORMATION IN Input Generator VI 50 W NOTE A VCC1 VI VCC1/2 VCC1/2 OUT 0V tPHL tPLH CL NOTE B VO VO VOH 90% 50% 50% 10% tr VOL tf A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms VI 0V or VCC1 A. ISOLATION BARRIER VCC1 IN VCC1 OUT VI 2.7 V VO 0V VOH tfs CL NOTE A VO 50% FAILSAFE HIGH VOL CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms VCC1 VCC2 S1 ISOLATION BARRIER C = 0.1 mF± 1% IN GND1 C = 0.1 mF± 1% Pass-fail criteria: Output must remain stable OUT NOTE A VOH or VOL GND2 VCM A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 3. Common-Mode Transient Immunity Test Circuit VCC1 DUT Tektronix HFS9009 IN OUT 0V Tektronix 784D PATTERN GENERATOR VCC/2 Jitter NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. Figure 4. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform 10 Submit Documentation Feedback ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 DEVICE INFORMATION IEC PACKAGE CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (Clearance) Shortest terminal-to-terminal distance through air 4.8 mm L(I02) Minimum external tracking (Creepage) Shortest terminal-to-terminal distance across the SOIC-8 package surface 4.3 mm CTI Tracking resistance (Comparative Tracking Index) DIN IEC 60112 / VDE 0303 Part 1 ≥175 V Minimum Internal Gap (Internal Clearance) Distance through the insulation 0.008 mm RIO Isolation resistance Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device, TA < 100°C >1012 Ω Input to output, VIO = 500 V, 100°C ≤ TA ≤ max >1011 Ω CIO Barrier capacitance Input to output VI = 0.4 sin (4E6πt) 1 pF CI Input capacitance to ground VI = 0.4 sin (4E6πt) 1 pF NOTE: Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. IEC 60664-1 RATINGS TABLE PARAMETER TEST CONDITIONS Basic isolation group Installation classification SPECIFICATION Material group IIIa Rated mains voltage ≤150 VRMS I-IV Rated mains voltage ≤300 VRMS I-III Rated mains voltage ≤400 VRMS I-II IEC 60747-5-2 INSULATION CHARACTERISTICS (1) PARAMETER TEST CONDITIONS SPECIFICATION VIORM Maximum working insulation voltage VPR Input to output test voltage Method b1, VPR = VIORM × 1.875, 100% Production test with t = 1 s, Partial discharge <5 pC 1050 VIOTM Transient overvoltage t = 60 s 4000 RS Insulation resistance VIO = 500 V at TS >109 Pollution degree (1) UNIT 560 V Ω 2 Climatic Classification 40/125/21 Submit Documentation Feedback 11 ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 DEVICE I/O SCHEMATICS Input VCC1 VCC1 VCC1 Output VCC2 750 kW IN 8W 500 W OUT 13 W IEC SAFETY LIMITING VALUES Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER TEST CONDITIONS IS Safety input, output, or supply current SOIC-8 TS Maximum case temperature SOIC-8 MIN TYP MAX θJA = 212°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C 124 θJA = 212°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C 190 150 UNIT mA °C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. 12 Submit Documentation Feedback ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 SOIC-8 PACKAGE THERMAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS θJA Junction-to-air θJB Junction-to-Board Thermal Resistance θJC Junction-to-Case Thermal Resistance PD Device Power Dissipation (1) MIN TYP Low-K Thermal Resistance (1) 212 High-K Thermal Resistance 122 MAX UNIT °C/W 37 69.1 ISO722xM VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 150 Mbps 50% duty cycle square wave 390 mW Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages. 250 Safety Limiting Current - mA 225 VCC1,2 at 3.6 V 200 175 150 125 VCC1,2 at 5.5 V 100 75 50 25 0 0 50 100 150 TC - Case Temperature - °C 200 Figure 5. SOIC-8 θJC THERMAL DERATING CURVE per IEC 60747-5-2 DEVICE FUNCTION TABLE Table 1. ISO7220x or ISO7221x (1) INPUT SIDE VCC PU PD (1) OUTPUT SIDE VCC INPUT IN OUTPUT OUT H H PU L L Open H X H PU PU = Powered Up(Vcc ≥ 3.0V); PD = Powered Down (Vcc ≤ 2.5V); X = Irrelevant; H = High Level; L = Low Level Submit Documentation Feedback 13 ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 TYPICAL CHARACTERISTIC CURVES 3.3-V RMS SUPPLY CURRENT vs SIGNALING RATE (Mbps) 5-V RMS SUPPLY CURRENT vs SIGNALING RATE (Mbps) 20 30 TA = 25°C, 15 pF Load 18 26 ISO7220x ICC2 24 14 ICC - Supply Current - mA 16 ICC - Supply Current - mA TA = 25°C, 15 pF Load 28 ISO7220x ICC2 12 10 ISO7221x ICC1&2 8 6 4 ISO7220x ICC1 22 20 14 12 10 2 0 0 25 50 ISO7220x ICC1 8 6 4 2 0 ISO7221x ICC1&2 18 16 75 100 0 25 Signaling Rate - Mbps 50 75 Signaling Rate - Mbps Figure 6. Figure 7. PROPAGATION DELAY vs FREE-AIR TEMPERATURE, ISO722xA PROPAGATION DELAY vs FREE-AIR TEMPERATURE, ISO722xC 450 30 15 pF Load 440 VCC = 3.3 V 25 430 tpLH & tpHL 420 VCC = 3.3 V 410 Propagation Delay - ns Propagation Delay - ns 100 tpLH & tpHL 400 VCC = 5 V 390 tpLH & tpHL 380 370 20 15 tpLH & tpHL VCC = 5 V 10 5 15 pF Load 360 350 -40 14 -15 10 35 60 85 110 125 0 -40 -15 10 35 60 Temperature - °C Temperature - °C Figure 8. Figure 9. Submit Documentation Feedback 85 110 125 ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 TYPICAL CHARACTERISTIC CURVES (continued) ISO722xA AND ISO722xC INPUT VOLTAGE LOW-TO-HIGH SWITCHING THRESHOLD vs FREE-AIR TEMPERATURE PROPAGATION DELAY vs FREE-AIR TEMPERATURE, ISO722xM 20 1.4 tpLH & tpHL 10 Input Voltage Threshold - V Propagation Delay - ns 15 VCC = 5 V tpLH & tpHL 5-V Vth+ 1.35 VCC = 3.3 V 5 15 pF Load 1.3 3.3-V Vth+ 1.25 15 pF Load 1.2 1.15 5-V Vth1.1 1.05 3.3-V Vth0 -40 1 -15 10 35 60 -40 -25 -10 110 125 85 20 35 50 65 80 Figure 10. Figure 11. ISO722xM INPUT VOLTAGE HIGH-TO-LOW vs FREE-AIR TEMPERATURE VCC FAILSAFE THRESHOLD vs FREE-AIR TEMPERATURE 5-V Vth+ 2.9 15 pF Load VCC = 3.3 V or 5 V 2.88 2 15 pF Load 1.9 1.8 3.3-V Vth+ Failsafe Threshold - V Input Voltage Threshold - V VFS 5-V Vth- 2.1 1.7 110 125 2.92 2.3 2.2 95 Temperature - °C 2.5 2.4 5 Temperature - °C 2.86 2.84 2.82 VFS- 1.6 2.8 1.5 3.3-V Vth- 1.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 2.78 -40 -25 -10 Temperature - °C 5 20 35 50 65 80 95 110 125 Temperature - °C Figure 12. Figure 13. Submit Documentation Feedback 15 ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 TYPICAL CHARACTERISTIC CURVES (continued) HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 70 -80 15 pF Load TA = 25°C -70 15 pF Load TA = 25°C 60 VCC = 5 V -60 50 VCC = 5 V IOUT - mA IOUT - mA -50 -40 -30 VCC = 3.3 V -20 40 VCC = 3.3 V 30 20 10 -10 0 0 0 2 4 0 6 1 2 VOUT - V Figure 14. Figure 15. ISO722xM JITTER vs SIGNALING RATE 2000 15 pF Load TA = 25°C 1800 1600 1400 Jitter − ps 1200 VCC1 = VCC2 = 5 V 1000 800 600 VCC1 = VCC2 = 3.3 V 400 200 0 0 50 100 Signaling Rate - Mbps Figure 16. 16 3 VOUT - V Submit Documentation Feedback 150 200 4 5 ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 APPLICATION INFORMATION Typical Applications V CC 1 V CC 2 0.1mF 20 mm max . from Vcc 1 INA INPUT INB INPUT 1 2 3 4 20 mm max . from Vcc 2 0.1mF 8 OUTA 7 OUTB 6 5 OUTPUT OUTPUT ISO 7220 GND 1 GND 2 Figure 17. Typical ISO7220 Application Circuit V CC 1 V CC 2 0.1mF 20 mm max . from Vcc 1 OUTA OUTPUT INB INPUT 1 2 3 4 20 mm max . from Vcc 2 0.1mF 8 INA 7 OUTB 6 5 INPUT OUTPUT ISO 7221 GND 1 GND 2 Figure 18. Typical ISO7221 Application Circuit WORKING LIFE -- YEARS 100 VIORM at 560 V 28 10 0 120 250 500 750 880 1000 WORKING VOLTAGE (V IORM ) -- V Figure 19. Time Dependent Dielectric Breakdown Test Results Submit Documentation Feedback 17 ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 ISOLATION GLOSSARY Creepage Distance — The shortest path between two conductive input to output leads measured along the surface of the insulation. The shortest distance path is found around the end of the package body. Clearance — The shortest distance between two conductive input to output leads measured through air (line of sight). Input-to Output Barrier Capacitance -- The total capacitance between all input terminals connected together, and all output terminals connected together. Input-to Output Barrier Resistance -- The total resistance between all input terminals connected together, and all output terminals connected together. Primary Circuit -- An internal circuit directly connected to an external supply mains or other equivalent source which supplies the primary circuit electric power. Secondary Circuit -- A circuit with no direct connection to primary power, and derives its power from a separate isolated source. Comparative Tracking Index (CTI) -- CTI is an index used for electrical insulating materials which is defined as the numerical value of the voltage which causes failure by tracking during standard testing. Tracking is the process that produces a partially conducting path of localized deterioration on or through the surface of an insulating material as a result of the action of electric discharges on or close to an insulation surface -- the higher CTI value of the insulating material, the smaller the minimum creepage distance. Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is generated. These sparks often cause carbonization on insulation material and lead to a carbon track between points of different potential. This process is known as tracking. 18 Submit Documentation Feedback ISO7220A, ISO7220C, ISO7220M ISO7221A, ISO7221C, ISO7221M www.ti.com SLLS755F – JULY 2006 – REVISED AUGUST 2007 ISOLATION GLOSSARY (continued) Insulation: Operational insulation -- Insulation needed for the correct operation of the equipment. Basic insulation -- Insulation to provide basic protection against electric shock. Supplementary insulation -- Independent insulation applied in addition to basic insulation in order to ensure protection against electric shock in the event of a failure of the basic insulation. Double insulation -- Insulation comprising both basic and supplementary insulation. Reinforced insulation -- A single insulation system which provides a degree of protection against electric shock equivalent to double insulation. Pollution Degree: Pollution Degree 1 -- No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence. Pollution Degree 2 -- Normally, only nonconductive pollution occurs. However, a temporary conductivity caused by condensation must be expected. Pollution Degree 3 -- Conductive pollution occurs or dry nonconductive pollution occurs which becomes conductive due to condensation which is to be expected. Pollution Degree 4 – Continuous conductivity occurs due to conductive dust, rain, or other wet conditions. Installation Category: Overvoltage Category -- This section is directed at insulation co-ordination by identifying the transient overvoltages which may occur, and by assigning 4 different levels as indicated in IEC 60664. I: Signal Level -- Special equipment or parts of equipment. II: Local Level -- Portable equipment etc. III: Distribution Level -- Fixed installation IV: Primary Supply Level -- Overhead lines, cable systems Each category should be subject to smaller transients than the category above. Submit Documentation Feedback 19 PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2007 PACKAGING INFORMATION (1) Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ISO7220AD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220ADG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220MD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220MDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220MDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220MDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221AD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221ADG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221MD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221MDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221MDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221MDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM The marketing status values are defined as follows: Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2007 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ISO7220ADR D 8 SITE 35 330 12 6.4 5.2 2.1 8 12 Q1 ISO7220CDR D 8 SITE 35 330 12 6.4 5.2 2.1 8 12 Q1 ISO7220MDR D 8 SITE 35 330 12 6.4 5.2 2.1 8 12 Q1 ISO7221ADR D 8 SITE 35 330 12 6.4 5.2 2.1 8 12 Q1 ISO7221CDR D 8 SITE 35 330 12 6.4 5.2 2.1 8 12 Q1 ISO7221MDR D 8 SITE 35 330 12 6.4 5.2 2.1 8 12 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) ISO7220ADR D 8 SITE 35 358.0 335.0 35.0 ISO7220CDR D 8 SITE 35 358.0 335.0 35.0 ISO7220MDR D 8 SITE 35 358.0 335.0 35.0 ISO7221ADR D 8 SITE 35 358.0 335.0 35.0 ISO7221CDR D 8 SITE 35 358.0 335.0 35.0 ISO7221MDR D 8 SITE 35 358.0 335.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Telephony www.ti.com/telephony Low Power Wireless www.ti.com/lpw Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2007, Texas Instruments Incorporated