TI ISO7231MDWR

ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008
HIGH SPEED, TRIPLE DIGITAL ISOLATORS
FEATURES
1
•
•
•
•
•
25 and 150-Mbps Signaling Rate Options
– Low Channel-to-Channel Output Skew;
1 ns max
– Low Pulse-Width Distortion (PWD);
2 ns max
– Low Jitter Content; 1 ns Typ at 150 Mbps
Typical 25-Year Life at Rated Working Voltage
(See Application Note SLLA197 and Figure 14)
4000-Vpeak Isolation, 560-Vpeak VIORM
– UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2),
IE 61010-1 and CSA Approved
4 kV ESD Protection
Operate With 3.3-V or 5-V Supplies
•
•
High Electromagnetic Immunity
(See Application Note SLLA181)
–40°C to 125°C Operating Range
APPLICATIONS
•
•
•
•
Industrial Fieldbus
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
DESCRIPTION
The ISO7230 and ISO7231 are triple-channel digital isolators each with multiple channel configurations and
output enable functions. These devices have logic input and output buffers separated by TI’s silicon dioxide
(SiO2) isolation barrier. Used in conjunction with isolated power supplies, these devices block high voltage,
isolate grounds, and prevent noise currents on a data bus or other circuits from entering the local ground and
interfering with or damaging sensitive circuitry.
The ISO7230 triple-channel device has all three channels in the same direction while the ISO7231 has two
channels in one direction and one channel in opposition. These devices have an active-high output enable that
when driven to a low level, places the output in a high-impedance state.
The ISO7230C and ISO7231C have TTL input thresholds and a noise-filter at the input that prevents transient
pulses of up to 2 ns in duration from being passed to the output of the device, while the ISO7230M and
ISO7231M have CMOS VCC/2 input thresholds and do not have the input noise-filter or the additional propagation
delay.
In each device, a periodic update pulse is sent across the isolation barrier to ensure the proper dc level of the
output. If this dc-refresh pulse is not received, the input is assumed to be unpowered or not being actively driven,
and the failsafe circuit drives the output to a logic high state. (Contact TI for a logic low failsafe option).
These devices require two supply voltages of 3.3-V, 5-V, or any combination. All inputs are 5-V tolerant when
supplied from a 3.3-V supply and all outputs are 4-mA CMOS. These devices are characterized for operation
over the ambient temperature range of –40°C to 125°C.
ISO7230
DW PACKAGE
VCC1
GND1
INA
INB
INC
NC
NC
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ISO7231
DW PACKAGE
VCC2
GND2
OUTA
OUTB
OUTC
NC
EN
GND2
VCC1
GND1
INA
INB
OUTC
NC
EN1
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
INC
NC
EN2
GND2
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008.................................................................................................................................................. www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTION DIAGRAM
Galvanic Isolation
Barrier
DC Channel
Filter
OSC
+
PWM
Pulse Width
Demodulation
Vref
Carrier Detect
EN
Input
+
Filter
IN
Data MUX
AC Detect
Vref
OUT
Output Buffer
AC Channel
Table 1. Device Function Table ISO723x
INPUT VCC
(1)
OUTPUT VCC
(1)
INPUT
(IN)
OUTPUT ENABLE
(EN)
OUTPUT
(OUT)
H
H or Open
H
L
H or Open
L
X
L
Z
PU
PU
Open
H or Open
H
PD
PU
X
H or Open
H
PD
PU
X
L
Z
PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level
AVAILABLE OPTIONS
PRODUCT
SIGNALING
RATE
INPUT
THRESHOLD
CHANNEL
CONFIGURATION
MARKED
AS
ISO7230CDW
25 Mbps
~1.5 V (TTL)
(CMOS compatible)
ISO7230MDW
150 Mbps
Vcc/2 (CMOS)
ISO7230M
ISO7231CDW
25 Mbps
~1.5 V (TTL)
(CMOS compatible)
ISO7231C
ISO7231MDW
150 Mbps
Vcc/2 (CMOS)
ISO7230C
3/0
2/1
(1)
2
ISO7231M
ORDERING
NUMBER (1)
ISO7230CDW (rail)
ISO7230CDWR (reel)
ISO7230MDW (rail)
ISO7230MDWR (reel)
ISO7231CDW (rail)
ISO7231CDWR (reel)
ISO7231MDW (rail)
ISO7231MDWR (reel)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
VCC
Supply voltage (2), VCC1, VCC2
–0.5 to 6
V
VI
Voltage at IN, OUT, EN
–0.5 to 6
V
IO
Output current
±15
mA
ESD
Electrostatic Field-Induced-Charged Device
discharge
Model
TJ
Maximum junction temperature
Human Body Model
Machine Model
(1)
(2)
JEDEC Standard 22, Test Method A114-C.01
JEDEC Standard 22, Test Method C101
±4
All pins
kV
±1
ANSI/ESDS5.2-1996
±200
V
170
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
MIN
VCC
Supply voltage (1), VCC1, VCC2
IOH
High-level output current
IOL
Low-level output current
tui
Input pulse width
1/tui
Signaling rate
VIH
High-level input voltage (IN)
VIL
Low-level input voltage (IN)
VIH
High-level input voltage (IN) (EN on all devices)
VIL
Low-level input voltage (IN) (EN on all devices)
TJ
Junction temperature
H
External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9
certification
(1)
(2)
TYP
3.15
MAX
5.5
4
–4
40
ISO723xM
6.67
5
ISO723xC
0
30 (2)
25
0
(2)
150
ISO723xM
200
ns
0.7 VCC
VCC
0
0.3 VCC
2
VCC
0
0.8
ISO723xC
V
mA
mA
ISO723xC
ISO723xM
UNIT
150
1000
Mbps
V
V
°C
A/m
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Typical sigalling rate under ideal conditions at 25°C.
Copyright © 2007–2008, Texas Instruments Incorporated
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Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
3
ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008.................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
Quiescent
ISO7230C/M
25 Mbps
ICC1
Quiescent
ISO7231C/M
25 Mbps
Quiescent
ISO7230C/M
25 Mbps
ICC2
Quiescent
ISO7231C/M
25 Mbps
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
1
3
7
9.5
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
6.5
11
11
17
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
15
22
17
24
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
13
20
17.5
27
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 4
(1)
4
EN at 0 V, Single channel
µA
0
IOH = –4 mA, See Figure 1
VCC – 0.8
IOH = –20 µA, See Figure 1
VCC – 0.1
V
IOL = 4 mA, See Figure 1
0.4
IOL = 20 µA, See Figure 1
0.1
150
mV
10
IN from 0 V to VCC
–10
25
V
µA
2
pF
50
kV/µs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
tPZH
Propagation delay, high-impedance-to-high-level output
tPLZ
Propagation delay, low-level-to-high-impedance output
tPZL
Propagation delay, high-impedance-to-low-level output
tfs
Failsafe output delay time from input power loss
See Figure 3
tjit(pp)
Peak-to-peak eye-pattern jitter
150 Mbps PRBS NRZ data input,
Same polarity inputon all channels,
See Figure 5
(1)
(2)
(3)
ISO723xC
See Figure 1
MIN
TYP MAX
18
42
2.5
10
ISO723xM
23
1
ISO723xC
(2)
(3)
2
8
ISO723xM
0
3
ISO723xC
0
2
ISO723xM
0
1
2
See Figure 1
ISO723xM
ns
ns
ns
ns
ns
2
See Figure 2
UNIT
15
20
15
20
15
20
15
20
ns
12
µs
1
ns
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2007–2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
5
ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008.................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISO7230C/M
ICC1
ISO7231C/M
ISO7230C/M
ICC2
ISO7231C/M
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
1
3
7
9.5
6.5
11
11
17
9
15
10
17
8
12
10.5
16
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
High-level output voltage
EN at 0 V, Single channel
IOH = –4 mA, See Figure 1
IOH = –20 µA, See Figure 1
VCC – 0.4
ISO7231
(5-V side)
VCC – 0.8
V
VCC – 0.1
0.4
IOL = 20 µA, See Figure 1
0.1
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 4
6
ISO7230
IOL = 4 mA, See Figure 1
VOL
(1)
µA
0
150
mV
10
IN from 0 V to VCC
–10
25
V
µA
2
pF
50
kV/µs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008
SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay, low-to-high-level output
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay, low-to-high-level output
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
tPZH
Propagation delay, high-impedance-to-high-level output
tPLZ
Propagation delay, low-level-to-high-impedance output
tPZL
Propagation delay, high-impedance-to-low-level output
tfs
Failsafe output delay time from input power loss
See Figure 3
tjit(pp)
Peak-to-peak eye-pattern jitter
150 Mbps PRBS NRZ data
input, Same polarity input on
all channels, See Figure 5
(1)
(2)
(3)
ISO723xC
See Figure 1
MIN
TYP MAX
20
50
3
12
ISO723xM
29
1
ISO723xC
(2)
(3)
2
10
ISO723xM
0
5
ISO723xC
0
2.5
ISO723xM
0
1
2
See Figure 1
ISO723xM
ns
ns
ns
ns
ns
2
See Figure 2
UNIT
15
20
15
20
15
20
15
20
ns
18
µs
1
ns
Also known as pulse skew
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2007–2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
7
ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008.................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
1
3
5
UNIT
SUPPLY CURRENT
ISO7230C/M
ICC1
ISO7231C/M
ISO7230C/M
ICC2
ISO7231C/M
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
4.5
7
6.5
11
15
22
17
24
13
20
17.5
27
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, Single channel
IOH = –4 mA, See Figure 1
VOH
High-level output voltage
IOH = –20 µA, See Figure 1
VCC – 0.4
ISO7231
(5-V side)
VCC – 0.8
V
VCC – 0.1
0.4
IOL = 20 µA, See Figure 1
0.1
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 4
8
ISO7230
IOL = 4 mA, See Figure 1
VOL
(1)
µA
0
150
mV
10
IN from 0 V to VCC
–10
25
V
µA
2
pF
50
kV/µs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008
SWITCHING CHARACTERISTICS: VCC1 at 3.3-V and VCC2 at 5-V OPERATION
, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion(1) |tPHL – tPLH|
MIN
ISO723xC
ISO723xM
30
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
tPZH
Propagation delay, high-impedance-to-high-level output
tPLZ
Propagation delay, low-level-to-high-impedance output
tPZL
Propagation delay, high-impedance-to-low-level output
tfs
Failsafe output delay time from input power loss
See Figure 3
Peak-to-peak eye-pattern jitter
150 Mbps PRBS NRZ data input, Same
polarity input on all channels, See Figure 5
(3)
ISO723xM
0
5
ISO723xC
0
2.5
ISO723xM
0
1
2
See Figure 1
ISO723xM
UNIT
ns
ns
ns
2
See Figure 2
ns
2
10
tsk(o)
(3)
12
1
Part-to-part skew
(1)
(2)
51
ISO723xC
(2)
MAX
3
See Figure 1
tsk(pp)
tjit(pp)
TYP
22
15
20
15
20
15
20
15
20
ns
12
µs
1
ns
Also known as pulse skew
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2007–2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
9
ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008.................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V (1) OPERATION
, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
0.5
1
3
5
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
4.5
7
6.5
11
UNIT
SUPPLY CURRENT
Quiescent
ISO7230C/M
25 Mbps
ICC1
Quiescent
ISO7231C/M
25 Mbps
Quiescent
ISO7230C/M
25 Mbps
ICC2
Quiescent
ISO7231C/M
25 Mbps
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
9
15
10
17
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
8
12
10.5
16
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, single channel
VCC – 0.4
IOH = –20 µA, See Figure 1
VCC – 0.1
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 4
(1)
10
µA
0
IOH = –4 mA, See Figure 1
V
IOL = 4 mA, See Figure 1
0.4
IOL = 20 µA, See Figure 1
0.1
150
mV
10
IN from 0 V or VCC
–10
25
V
µA
2
pF
50
kV/µs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tpLH, tpHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 3
Peak-to-peak eye-pattern jitter
150 Mbps PRBS NRZ data input, same
polarity input on all channels, See Figure 5
tjit(pp)
(1)
(2)
(3)
ISO723xC
25
MAX
tPLH, tPHL
See Figure 1
56
4
12
ISO723xM
34
1
ISO723xC
(2)
(3)
2
10
ISO723xM
0
5
ISO723xC
0
3
ISO723xM
0
1
2
See Figure 1
ISO723xM
ns
ns
ns
ns
ns
2
See Figure 2
UNIT
ns
18
µs
1
ns
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2007–2008, Texas Instruments Incorporated
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11
ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008.................................................................................................................................................. www.ti.com
ISOLATION BARRIER
PARAMETER MEASUREMENT INFORMATION
IN
Input
Generator
VI
50 W
NOTE A
VCC1
VI
VCC1/2
VCC1/2
OUT
0V
tPHL
tPLH
CL
NOTE B
VO
VO
VOH
90%
50%
50%
10%
tr
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
Vcc
Vcc
ISOLATION BARRIER
RL = 1 kW ±1%
IN
0V
Input
Generator
VI
OUT
EN
Vcc/2
VI
t PZL
VO
VO
CL
Vcc/2
0V
t PLZ
Vcc
0.5 V
50%
NOTE
B
50 W
VOL
NOTE A
ISOLATION BARRIER
3V
Vcc
IN
Input
Generator
VI
OUT
VO
Vcc/2
VI
Vcc/2
0V
t PZH
EN
50 W
CL
NOTE
B
RL = 1 kW ±1%
VO
VOH
50%
0.5 V
t PHZ
0V
NOTE A
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
12
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Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008
PARAMETER MEASUREMENT INFORMATION (continued)
VI
0V
or
VCC1
ISOLATION BARRIER
VCC1
IN
VCC1
VI
OUT
2.7 V
VO
0V
VOH
tfs
CL
NOTE B
VO
50%
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms
VCC1
VCC2
S1
ISOLATION BARRIER
C = 0.1 mF± 1%
IN
GND1
C = 0.1 mF± 1%
OUT
NOTE B
Pass-fail criteria:
Output must
remain stable
VOH or VOL
GND2
VCM
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 4. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
VCC1
DUT
Tektronix
HFS9009
IN
OUT
0V
Tektronix
784D
PATTERN
GENERATOR
VCC/2
Jitter
NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s
or 0s.
Figure 5. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
Copyright © 2007–2008, Texas Instruments Incorporated
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13
ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008.................................................................................................................................................. www.ti.com
DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER
L(I01)
L(I02)
RIO
TEST CONDITIONS
MIN
TYP MAX
UNIT
Minimum air gap (Clearance)
Shortest terminal-to-terminal distance through air
8.34
mm
Minimum external tracking (Creepage)
Shortest terminal-to-terminal distance across the
package surface
8.1
mm
Minimum Internal Gap (Internal
Clearance)
Distance through the insulation
0.008
mm
Isolation resistance
Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-terminal device,
TA < 100°C
>1012
Input to output, VIO = 500 V, 100°C ≤ TA ≤ TA max
>1011
Ω
Ω
CIO
Barrier capacitance Input to output
VI = 0.4 sin (4E6πt)
2
pF
CI
Input capacitance to ground
VI = 0.4 sin (4E6πt)
2
pF
REGULATORY INFORMATION
VDE
CSA
UL
Certified according to IEC
60747-5-2
Approved under CSA Component
Acceptance Notice
Recognized under 1577
Component Recognition
Program (1)
File Number: 40016131
File Number: 1698195
File Number: E181974
(1)
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
DEVICE I/O SCHEMATICS
Enable
VCC2
Output
Input
VCC2
VCC1
VCC2
VCC1
VCC2
1 MW
500 W
IN
EN
8W
500 W
OUT
13 W
1 MW
THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Low-K Thermal Resistance
MIN
(1)
TYP MAX
168
UNIT
θJA
Junction-to-air
θJB
Junction-to-Board Thermal Resistance
61
°C/W
θJC
Junction-to-Case Thermal Resistance
48
°C/W
PD
Device Power Dissipation
(1)
14
High-K Thermal Resistance
°C/W
96.1
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50% duty cycle square wave
220
mW
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
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Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008
TYPICAL CHARACTERISTIC CURVES
ISO7230 C/M RMS SUPPLY CURRENT
vs
SIGNALING RATE
ISO7231 C/M RMS SUPPLY CURRENT
vs
SIGNALING RATE
45
40
ICC - Supply Current - mA/RMS
ICC - Supply Current - mA/RMS
40
45
TA = 25°C,
Load = 15 pF,
All Channels
35
30
5-V ICC2
3.3-V ICC2
25
20
15
5-V ICC1
10
3.3-V ICC1
5
35
5-V ICC1
30
25
5-V ICC2
20
15
10
25
50
75
100
125
0
0
150
3.3-V ICC2
3.3-V ICC1
5
0
0
25
50
75
100
125
Signaling Rate - Mbps
Signaling Rate - Mbps
Figure 6.
Figure 7.
PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
45
150
1.4
40
Input Voltage Threshold - V
35
C 5-V tpLH, tpHL
30
25
20
M 3.3-V tpLH, tpHL
15
M 5-V tpLH, tpHL
10
TA = 25°C,
Load = 15 pF,
All Channels
5
-25
-10
1.3
3.3 V Vth+
1.25
1.2
Air Flow at 7 cf/m,
Low-K Board
1.15
5 V Vth1.1
1.05
3.3 V Vth-
0
-40
5 V Vth+
1.35
C 3.3-V tpLH, tpHL
Propagation Delay - ns
TA = 25°C,
Load = 15 pF,
All Channels
5
80
65
35
20
50
TA - Free-Air Temperature - °C
Figure 8.
Copyright © 2007–2008, Texas Instruments Incorporated
95
110
125
1
-40
-25
-10
5
20
35
50
65
80
TA - Free-Air Temperature - °C
95
110
125
Figure 9.
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15
ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008.................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTIC CURVES (continued)
VCC1 FAILSAFE THRESHOLD
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
50
3
2.8
VCC at 5 V or 3.3 V,
Load = 15 pF,
Air Flow at 7/cf/m,
Low-K Board
VCC = 5 V
Load = 15 pF,
TA = 25°C
40
2.7
IO - Output Current - mA
VCC1 - Failsafe Threshold - V
2.9
Vfs+
2.6
2.5
Vfs-
2.4
2.3
2.2
VCC = 3.3 V
30
20
10
2.1
2
-40
-25
-10
5
20
35
50
65
80
95
110
0
0
125
2
TA - Free-Air Temperature - °C
4
VO - Output Voltage - V
Figure 10.
6
Figure 11.
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
Load = 15 pF,
TA = 25°C
45
IO - Output Current - mA
40
35
VCC = 3.3 V
30
25
VCC = 5 V
20
15
10
5
0
0
1
2
3
VO - Output Voltage - V
4
5
Figure 12.
16
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Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F – SEPTEMBER 2007 – REVISED JUNE 2008
APPLICATION INFORMATION
20 mm
max. from
VCC1
VCC1
20 mm
max. from
VCC2
VCC2
0.1 mF
0.1 mF
1
16
2
15
IN A
3
14
OUT A
IN B
4
13
OUT B
IN C
5
12
OUT C
NC
6
11
NC
7
10
8
9
GND2
GND1
NC
EN
GND2
GND1
ISO7230
Figure 13. Typical ISO7230 Application Circuit
LIFE EXPECTANCY vs WORKING VOLTAGE
WORKING LIFE -- YEARS
100
VIORM at 560-V
28 Years
10
0
120
250
500
750
880
1000
WORKING VOLTAGE (VIORM) -- V
Figure 14. Time Dependant Dielectric Breakdown Testing Results
Copyright © 2007–2008, Texas Instruments Incorporated
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17
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jun-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ISO7230CDW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7230CDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7230CDWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7230CDWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7230MDW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7230MDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7230MDWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7230MDWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7231CDW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7231CDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7231CDWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7231CDWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7231MDW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7231MDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7231MDWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ISO7231MDWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jun-2008
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO7230CDWR
SOIC
DW
16
2000
330.0
16.4
10.9
10.78
3.0
12.0
16.0
Q1
ISO7230MDWR
SOIC
DW
16
2000
330.0
16.4
10.9
10.78
3.0
12.0
16.0
Q1
ISO7231CDWR
SOIC
DW
16
2000
330.0
16.4
10.9
10.78
3.0
12.0
16.0
Q1
ISO7231MDWR
SOIC
DW
16
2000
330.0
16.4
10.9
10.78
3.0
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7230CDWR
SOIC
DW
16
2000
358.0
335.0
35.0
ISO7230MDWR
SOIC
DW
16
2000
358.0
335.0
35.0
ISO7231CDWR
SOIC
DW
16
2000
358.0
335.0
35.0
ISO7231MDWR
SOIC
DW
16
2000
358.0
335.0
35.0
Pack Materials-Page 2
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