TI SN65HVD05DR

SN65HVD05,, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com
SLLS533D – MAY 2002 – REVISED JULY 2006
HIGH OUTPUT RS-485 TRANSCEIVERS
FEATURES
•
•
•
•
•
•
•
•
•
DESCRIPTION
Minimum Differential Output Voltage of 2.5 V
Into a 54-Ω Load
Open-Circuit, Short-Circuit, and Idle-Bus
Failsafe Receiver
1/8th Unit-Load Option Available (Up to 256
Nodes on the Bus)
Bus-Pin ESD Protection Exceeds 16 kV HBM
Driver Output Slew Rate Control Options
Electrically Compatible With ANSI
TIA/EIA-485-A Standard
Low-Current Standby Mode . . . 1 µA Typical
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
Pin Compatible With Industry Standard
SN75176
APPLICATIONS
•
•
•
•
•
•
•
Data Transmission Over Long or Lossy Lines
or Electrically Noisy Environments
Profibus Line Interface
Industrial Process Control Networks
Point-of-Sale (POS) Networks
Electric Utility Metering
Building Automation
Digital Motor Control
The SN65HVD05, SN75HVD05, SN65HVD06,
SN75HVD06, SN65HVD07, and SN75HVD07
combine a 3-state differential line driver and
differential line receiver. They are designed for
balanced data transmission and interoperate with
ANSI
TIA/EIA-485-A
and
ISO
8482E
standard-compliant devices. The driver is designed
to provide a differential output voltage greater than
that required by these standards for increased noise
margin. The drivers and receivers have active-high
and active-low enables respectively, which can be
externally connected together to function as direction
control.
The driver differential outputs and receiver
differential inputs connect internally to form a
differential input/ output (I/O) bus port that is
designed to offer minimum loading to the bus
whenever the driver is disabled or not powered.
These devices feature wide positive and negative
common-mode voltage ranges, making them suitable
for party-line applications.
D OR P PACKAGE
(TOP VIEW)
R
RE
DE
D
V O - Differential Output Voltage - V
5
4
60 Ω Load
Line
3.5
R
TA = 25°C
DE at VCC
D at VCC
VCC = 5 V
RE
30 Ω Load
Line
3
DE
2.5
8
2
7
3
6
4
5
VCC
B
A
GND
LOGIC DIAGRAM
(POSITIVE LOGIC)
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL OUTPUT CURRENT
4.5
1
1
2
3
6
2
D
1.5
1
4
7
A
B
0.5
0
0
20
40
60
80
100
120
IOD - Differential Output Current - mA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2006, Texas Instruments Incorporated
SN65HVD05,, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com
SLLS533D – MAY 2002 – REVISED JULY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
MARKED AS
DRIVER
OUTPUT SLOPE
CONTROL
SIGNALING
RATE
UNIT
LOAD
40 Mbps
1/2
No
10 Mbps
1/8
Yes
1 Mbps
1/8
Yes
40 Mbps
1/2
No
10 Mbps
1/8
Yes
1 Mbps
1/8
Yes
(1)
(2)
PART NUMBER (2)
TA
40°C to 85°C
0°C to 70°C
PLASTIC
DUAL-IN-LINE
PACKAGE
(PDIP)
SMALL
OUTLINE
IC (SOIC)
PACKAGE
SN65HVD05D
SN65HVD05P
65HVD05
VP05
SN65HVD06D
SN65HVD06P
65HVD06
VP06
SN65HVD07D
SN65HVD07P
65HVD07
VP07
SN75HVD05D
SN75HVD05P
75HVD05
VN05
SN75HVD06D
SN75HVD06P
75HVD06
VN06
SN75HVD07D
SN75HVD07P
75HVD07
VN07
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD05DR).
PACKAGE DISSIPATION RATINGS
(See Figure 12 and Figure 13)
(1)
(2)
(3)
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D (2)
710 mW
5.7 mW/°C
455 mW
369 mW
D (3)
1282 mW
10.3 mW/°C
821 mW
667 mW
P
1000 mW
8.0 mW/°C
640 mW
520 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3
Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1) (2)
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
Supply voltage range, VCC
-0.3 V to 6 V
Voltage range at A or B
-9 V to 14 V
Input voltage range at D, DE, R or RE
-0.5 V to VCC + 0.5 V
Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 11)
Receiver output current, IO
Electrostatic discharge
Human body model (3)
Charged-device model (4)
A, B, and GND
16 kV
All pins
4 kV
All pins
1 kV
Continuous total power dissipation
(1)
(2)
(3)
(4)
2
-50 V to 50 V
–11 mA to 11mA
See Dissipation Rating Table
Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under" recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
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SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
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SLLS533D – MAY 2002 – REVISED JULY 2006
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX
Supply voltage, VCC
Voltage at any bus terminal (separately or common mode) VI or VIC
High-level input voltage, VIH
D, DE, RE
Low-level input voltage, VIL
D, DE, RE
High-level output current, IOH
Low-level output current, IOL
4.5
5.5
V
-7 (1)
12
V
2
Differential input voltage, VID (see Figure 7)
V
-12
Driver
0.8
V
12
V
-100
Receiver
UNIT
mA
-8
Driver
100
Receiver
8
mA
SN65HVD05
SN65HVD06
Operating free-air temperature, TA
-40
85
°C
0
70
°C
SN65HVD07
SN75HVD05
SN75HVD06
SN75HVD07
(1)
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
DRIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
VIK
Input clamp voltage
|VOD|
Differential output voltage
TEST CONDITIONS
II = -18 mA
MIN TYP (1)
VCC
RL = 54 Ω, See Figure 4
2.5
Vtest = -7 V to 12 V, See Figure 2
2.2
∆|VOD|
Change in magnitude of differential output
voltage
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode
output voltage
VOC(PP)
Peak-to-peak common-mode
output voltage
IOZ
High-impedance output current
II
Input current
IOS
Short-circuit output current
-7 V ≤ VO ≤ 12 V
C(diff)
Differential output capacitance
VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
See Figure 4 and Figure 2
See Figure 3
0.2
V
2.2
3.3
V
-0.1
0.1
V
600
See Figure 3
500
HVD07
(1)
V
-0.2
HVD05
ICC
UNIT
V
No Load
HVD06
MAX
-1.5
mV
900
See receiver input currents
D
DE
Supply current
-100
0
0
100
-250
250
16
µA
mA
pF
RE at VCC,
D & DE at VCC,
No load
Receiver disabled
and driver enabled
9
15
mA
RE at VCC,
D at VCC DE at 0 V,
No load
Receiver disabled
and driver disabled
(standby)
1
5
µA
RE at 0 V,
D & DE at VCC,
No load
Receiver enabled
and driver enabled
9
15
mA
All typical values are at 25°C and with a 5-V supply.
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SN65HVD05,, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
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SLLS533D – MAY 2002 – REVISED JULY 2006
DRIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
MIN TYP (1)
MAX
HVD05
6.5
11
HVD06
27
40
HVD07
250
400
HVD05
6.5
11
HVD06
27
40
250
400
PARAMETER
tPLH
TEST CONDITIONS
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
HVD07
HVD05
tr
Differential output signal rise time
tf
tsk(pp) (2)
tPZH1
3.6
6
18
28
55
HVD07
150
300
450
HVD05
2.7
3.6
6
HVD06
18
28
55
HVD07
150
300
450
HVD06
Differential output signal fall time
tsk(p)
2.7
Pulse skew (|tPHL - tPLH|)
Part-to-part skew
Propagation delay time,
high-impedance-to-high-level output
HVD05
2
HVD06
2.5
HVD07
10
HVD05
3.5
HVD06
14
HVD07
100
HVD05
25
HVD06
HVD07
HVD05
Propagation delay time,
high-level-to-high-impedance output
tPHZ
tPZL1
Propagation delay time,
high-impedance-to-low-level output
RE at 0 V, RL = 110 Ω,
See Figure 5
60
250
HVD05
15
HVD06
Propagation delay time,
low-level-to-high-impedance output
45
RE at 0 V, RL = 110 Ω,
See Figure 6
ns
ns
ns
ns
ns
ns
25
HVD07
HVD05
ns
ns
200
14
HVD06
90
HVD07
550
ns
tPZH2
Propagation delay time, standby-to-high-level output
RL = 110Ω , RE at 3 V,
See Figure 5
6
µs
tPZL2
Propagation delay time, standby-to-low-level output
RL = 110 Ω, RE at 3 V,
See Figure 6
6
µs
(1)
(2)
4
45
ns
250
HVD06
HVD07
tPLZ
RL = 54 Ω, CL = 50 pF,
See Figure 4
UNIT
All typical values are at 25°C and with a 5-V supply.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
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SLLS533D – MAY 2002 – REVISED JULY 2006
RECEIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
VIT+
Positive-going input
threshold voltage
IO = -8 mA
VIT-
Negative-going input
threshold voltage
IO = 8 mA
Vhys
Hysteresis voltage
(VIT+ - VIT-)
VIK
Enable-input clamp
voltage
II = -18 mA
VOH
High-level output voltage
VID = 200 mV,
IOH = -8 mA,
See Figure 7
VOL
Low-level output voltage
VID = -200 mV,
IOL = 8 mA,
See Figure 7
IOZ
High-impedance-state
output current
VO = 0 or VCC
RE at VCC
MAX
V
-0.2
35
HVD05
Other inputat 0 V
VA or VB = 12 V,
V
4
V
VCC = 0 V
VCC = 0 V
Other inputat 0 V
VA or VB = -7 V
VA or VB = -7 V,
VCC = 0 V
V
1
µA
0.5
0.3
0.5
0.13
-0.4
0.15
VCC = 0 V
0.4
0.23
-0.4
VA or VB = 12 V
VA or VB = 12 V,
mV
-1.5
-1
VA or VB = -7 V
VA or VB = -7 V,
Bus input current
HVD06
HVD07
UNIT
0.01
VA or VB = 12 V
II
TYP (1)
0.06
0.1
0.08
0.13
-0.1
0.05
-0.05
0.03
mA
mA
IIH
High-level input current,
RE
VIH = 2 V
-60
26.4
µA
IIL
Low-level input current,
RE
VIL = 0.8 V
-60
27.4
µA
C(diff)
Differential input
capacitance
VI = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
16
pF
ICC
(1)
Supply current
RE at 0 V, D & DE at
0 V, No load
Receiver enabled and driver disabled
5
10
mA
RE at VCC, DE at 0 V,
D at VCC, No load
Receiver disabled and driver disabled
(standby)
1
5
µA
RE at 0 V,
D & DE at VCC,
No load
Receiver enabled and driver enabled
9
15
mA
All typical values are at 25°C and with a 5-V supply.
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SN65HVD05,, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
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SLLS533D – MAY 2002 – REVISED JULY 2006
RECEIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
Propagation delay time, low-to-high-level output 1/2 UL
HVD05
14.6
25
ns
tPHL
Propagation delay time, high-to-low-level output 1/2 UL
HVD05
14.6
25
ns
tPLH
Propagation delay time, low-to-high-level output 1/8 UL
HVD06
55
70
HVD07
55
70
55
70
55
70
tPHL
Propagation delay time, high-to-low-level output 1/8 UL
tsk(p)
Pulse skew (|tPHL - tPLH|)
tsk(pp) (2)
Part-to-part skew
tr
Output signal rise time
tf
Output signal fall time
tPZH1
Output enable time to high level
VID = -1.5 V to 1.5 V,
CL = 15 pF,
See Figure 8
HVD06
HVD07
HVD05
2
HVD06
4.5
HVD07
4.5
HVD05
6.5
HVD06
14
HVD07
14
CL = 15 pF,
See Figure 8
2
3
2
3
ns
ns
ns
ns
ns
10
CL = 15 pF,
DE at 3 V,
See Figure 9
tPZL1
Output enable time to low level
tPHZ
Output disable time from high level
tPLZ
Output disable time from low level
tPZH2
Propagation delay time, standby-to-high-level output
tPZL2
Propagation delay time, standby-to-low-level output
(1)
(2)
10
15
ns
15
CL = 15 pF, DE at 0,
See Figure 10
6
6
µs
All typical values are at 25°C and with a 5-V supply.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
PARAMETER MEASUREMENT INFORMATION
VCC
DE
II
A
IOA
VOD
0 or 3 V
B
54 Ω ±1%
IOB
VI
VOB
VOA
Figure 1. Driver VOD Test Circuit and Voltage and Current Definitions
375 Ω ±1%
VCC
DE
D
A
VOD
0 or 3 V
60 Ω ±1%
+ -7 V < V(test)
_ < 12 V
B
375 Ω ±1%
Figure 2. Driver VOD With Common-Mode Loading Test Circuit
6
UNIT
tPLH
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SN65HVD05,, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
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SLLS533D – MAY 2002 – REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
VCC
DE
Input
D
27 Ω ± 1%
A
A
VA
B
VB
VOC(PP)
27 Ω ± 1%
B
CL = 50 pF ±20%
VOC
∆VOC(SS)
VOC
CL Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50 Ω
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
3V
VCC
DE
D
Input
Generator
VI
VOD
1.5 V
0V
CL Includes Fixture
and Instrumentation
Capacitance
RL = 54 Ω
± 1%
B
50 Ω
1.5 V
VI
CL = 50 pF ±20%
A
tPLH
tPHL
90%
VOD
≈2V
90%
0V
10%
0V
10%
≈ –2 V
tr
tf
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 4. Driver Switching Test Circuit and Voltage Waveforms
A
3V
D
3V
S1
VO
VI
1.5 V
1.5 V
B
DE
Input
Generator
VI
RL = 110 Ω
± 1%
CL = 50 pF ±20%
50 Ω CL Includes Fixture
and Instrumentation
Capacitance
0V
0.5 V
tPZH(1 & 2)
VOH
VO
2.3 V
≈0V
tPHZ
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
VCC
A
3V
D
VI
≈3V
VI
S1
1.5 V
1.5 V
VO
DE
Input
Generator
RL = 110 Ω
± 1%
50 Ω
B
0V
tPZL(1 & 2)
tPLZ
CL = 50 pF ±20%
VCC
0.5 V
CL Includes Fixture
and Instrumentation
Capacitance
VO
2.3 V
VOL
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
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SN65HVD05,, SN65HVD06
SN75HVD05, SN65HVD07
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SLLS533D – MAY 2002 – REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
IA
VA
VIC
VA + VB
2
VB
A
IO
R
VID
B
VO
IB
Figure 7. Receiver Voltage and Current Definitions
A
Input
Generator
R
VI
50 Ω
1.5 V
0V
B
3V
VO
CL = 15 pF ±20%
RE
CL Includes Fixture
and Instrumentation
Capacitance
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
1.5 V
VI
1.5 V
0V
tPLH
VO
tPHL
90% 90%
1.5 V
10%
tr
Figure 8. Receiver Switching Test Circuit and Voltage Waveforms
8
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VOH
1.5 V
10% V
OL
tf
SN65HVD05,, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
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SLLS533D – MAY 2002 – REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
A
D
0 V or 3 V
Generator: PRR = 100 kHz,
50% Duty Cycle,
tr <6 ns, tf <6 ns, Zo = 50 Ω
3V
B
DE
RE
Input
Generator
VI
50 Ω
A
VCC
VO
S1
R
1 kΩ ± 1%
B
CL = 15 pF ±20%
CL Includes Fixture and
Instrumentation Capacitance
3V
VI
1.5 V
1.5 V
0V
tPZH(1)
tPHZ
VOH –0.5 V
VOH
D at 3 V
S1 to B
1.5 V
VO
≈0V
tPZL(1)
tPLZ
VCC
VO
1.5 V
D at 0 V
S1 to A
VOL +0.5 V
VOL
Figure 9. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
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SN65HVD05,, SN65HVD06
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SLLS533D – MAY 2002 – REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Generator: PRR = 100 kHz,
50% Duty Cycle,
tr <6 ns, tf <6 ns, Zo = 50 Ω
0V
DE
RE
Input
Generator
VI
50 Ω
A
A
VCC
VO
S1
R
B
1 kΩ ± 1%
B
0 V or 1.5 V
1.5 V or 0 V
CL = 15 pF ±20%
CL Includes Fixture and
Instrumentation Capacitance
3V
1.5 V
VI
0V
tPZH(2)
A at 1.5 V
B at 0 V
S1 to B
VOH
1.5 V
VO
GND
tPZL(2)
A at 0 V
B at 1.5 V
S1 to A
VCC
1.5 V
VO
VOL
Figure 10. Receiver Enable Time From Standby (Driver Disabled)
0 V or 3 V
A
RE
R
Pulse Generator,
15 µs Duration,
1% Duty Cycle
tr, tf ≤ 100 ns
100 Ω
± 1%
B
D
+
_
DE
3 V or 0 V
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 11. Test Circuit, Transient Over Voltage Test
10
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SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
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SLLS533D – MAY 2002 – REVISED JULY 2006
FUNCTION TABLES
DRIVER
INPUT
ENABLE
D
DE
OUTPUTS
A
B
H
L
X
Open
X
H
H
L
H
Open
H
L
Z
H
Z
L
H
Z
L
Z
RECEIVER (1)
(1)
DIFFERENTIAL INPUTS
ENABLE
OUTPUT
VID = VA - VB
RE
R
VID≤ -0.2 V
-0.2 V < VID < -0.01 V
-0.01 V≤ VID
X
Open Circuit
Short Circuit
X
L
L
L
H
L
L
Open
L
?
H
Z
H
H
Z
H = high level; L = low level; Z = high impedance; X = irrelevant;
? = indeterminate
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SN75HVD06, SN75HVD07
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SLLS533D – MAY 2002 – REVISED JULY 2006
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Inputs
DE Input
VCC
VCC
100 kΩ
1 kΩ
1 kΩ
Input
Input
100 kΩ
9V
9V
A Input
B Input
VCC
VCC
16 V
100 kΩ
16 V
R3
R1
R3
Input
Input
16 V
R2
R1
100 kΩ
16 V
A and B Outputs
R2
R Output
VCC
VCC
16 V
5Ω
Output
Output
9V
16 V
SN65HVD05
SN65HVD06
SN65HVD07
12
R1/R2
9 kΩ
36 kΩ
36 kΩ
R3
45 kΩ
180 kΩ
180 kΩ
Submit Documentation Feedback
SN65HVD05,, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com
SLLS533D – MAY 2002 – REVISED JULY 2006
HVD05
MAXIMUM RECOMMENDED STILL-AIR
OPERATING TEMPERATURE
vs
SIGNALING RATE
(D-PACKAGE)
HVD06
MAXIMUM RECOMMENDED STILL-AIR
OPERATING TEMPERATURE
vs
SIGNALING RATE
(D-PACKAGE)
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum Recommended Still-Air
Operating Temperature - T A ( °C)
Maximum Recommended Still-Air
Operating Temperature - T A ( °C)
TYPICAL CHARACTERISTICS
85
High K Board
25
Low K Board
1
10
85
High K Board
25
Low K Board
1
40
10
Signaling Rate - Mbps
120
Figure 13.
HVD05
RMS SUPPLY CURRENT
vs
SIGNALILNG RATE
HVD06
RMS SUPPLY CURRENT
vs
SIGNALING RATE
120
RL = 54 Ω
CL = 50 pF
VCC = 5 V
RL = 54 Ω
CL = 50 pF
VCC = 5 V
TA = 25°C
RE at VCC
DE at VCC
I CC - RMS Supply Current - mA
I CC - RMS Supply Current - mA
Figure 12.
TA = 25°C
RE at VCC
DE at VCC
110
Signaling Rate - Mbps
100
90
80
70
60
50
100
80
60
40
40
30
0
5
10
15
20
25
30
35
40
0
2.5
5
Signaling Rate - Mbps
Signaling Rate - Mbps
Figure 14.
Figure 15.
Submit Documentation Feedback
7.5
10
13
SN65HVD05,, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com
SLLS533D – MAY 2002 – REVISED JULY 2006
TYPICAL CHARACTERISTICS (continued)
HVD07
RMS SUPPLY CURRENT
vs
SIGNALING RATE
110
90
80
70
60
100
HVD05
50
0
HVD06
HVD07
-50
-150
40
100
400
700
Signaling Rate - kbps
-200
-7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12
VI - Bus Input Voltage - V
1000
Figure 16.
Figure 17.
DRIVER HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
DRIVER LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
160
0
TA = 25°C
DE at VCC
D at VCC
VCC = 5 V
-20
-40
I OL- Driver Low-Level Output Current - mA
I OH - Driver High-Level Output Current - mA
150
-100
50
-60
-80
-100
-120
-140
-160
0
14
TA = 25°C
DE at 0 V
VCC = 5 V
200
I I - Bus Input Current - µ A
I CC - RMS Supply Current - mA
250
RL = 54 Ω
CL = 50 pF
VCC = 5 V
TA = 25°C
RE at VCC
DE at VCC
100
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
TA = 25°C
DE at VCC
D at 0 V
VCC = 5 V
140
120
100
80
60
40
20
0
VO - High-Level Output Voltage - V
0
1 1.5 2
2.5 3 3.5 4
VO - Low-Level Output Voltage - V
Figure 18.
Figure 19.
Submit Documentation Feedback
0.5
4.5
5
SN65HVD05,, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com
SLLS533D – MAY 2002 – REVISED JULY 2006
TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
70
4
3.6
TA = 25°C
DE at VCC
D at VCC
RL = 54 Ω
60
I O - Driver Output Current - mA
VOD - Differential Output Voltage - V
3.8
DE at VCC
D at VCC
VCC = 5 V
RL = 54 Ω
3.4
3.2
3
2.8
2.6
2.4
50
40
30
20
10
2.2
2
-40
0
-15
10
35
60
TA - Free-Air Temperature - °C
85
0.6
1.2 1.8 2.4
3
3.6 4.2
VCC - Supply Voltage - V
4.8
Figure 20.
Figure 21.
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL OUTPUT CURRENT
ENABLE TIME
vs
COMMON-MODE VOLTAGE (SEE Figure 24)
5.4
600
5
4
60 Ω Load
Line
3.5
TA = 25°C
DE at VCC
D at VCC
VCC = 5 V
500
30 Ω Load
Line
3
HVD07
HVD5
Enable Time − ns
4.5
VO - Differential Output Voltage - V
0
2.5
2
1.5
1
400
300
HVD06
200
100
0.5
0
0
0
20
40
60
80
100
IOD - Differential Output Current - mA
120
-7
Figure 22.
-2
3
8
13
V(TEST) − Common-Mode Voltage − V
Figure 23.
Submit Documentation Feedback
15
SN65HVD05,, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com
SLLS533D – MAY 2002 – REVISED JULY 2006
TYPICAL CHARACTERISTICS (continued)
375 W ± 1%
Y
D
0 or 3 V
-7 V < V(TEST) < 12 V
VOD
60 W
± 1%
Z
DE
375 W ± 1%
Input
Generator
V
50 W
50%
tpZH(diff)
VOD (high)
1.5 V
0V
tpZL(diff)
-1.5 V
VOD (low)
Figure 24. Driver Enable Time From DE to VOD
The time tpZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
16
Submit Documentation Feedback
SN65HVD05,, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com
SLLS533D – MAY 2002 – REVISED JULY 2006
APPLICATION INFORMATION
RT
RT
Device
HVD05
HVD06
HVD07
Number of Devices on Bus
64
256
256
NOTE: The line should be terminated at both ends with its characteristic impedance (RT = ZO).
Stub lengths off the main line should be kept as short as possible.
Figure 25. Typical Application Circuit
Submit Documentation Feedback
17
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65HVD05D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD05DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD05DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD05DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD05P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN65HVD05PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN65HVD06D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD06DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD06DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD06DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD06P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN65HVD06PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN65HVD07D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD07DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD07DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD07DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD07P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN65HVD07PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN75HVD05D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD05DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD05DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD05DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD05P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN75HVD05PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN75HVD06D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN75HVD06DG4
ACTIVE
SOIC
D
8
SN75HVD06DR
ACTIVE
SOIC
D
SN75HVD06DRG4
ACTIVE
SOIC
SN75HVD06P
ACTIVE
SN75HVD06PE4
75
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN75HVD07D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD07DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD07DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD07DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD07P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN75HVD07PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65HVD05DR
D
8
SITE 27
330
0
6.4
5.2
2.1
8
12
Q1
SN65HVD06DR
D
8
SITE 27
330
0
6.4
5.2
2.1
8
12
Q1
SN65HVD07DR
D
8
SITE 27
330
0
6.4
5.2
2.1
8
12
Q1
SN75HVD05DR
D
8
SITE 27
330
0
6.4
5.2
2.1
8
12
Q1
SN75HVD06DR
D
8
SITE 27
330
0
6.4
5.2
2.1
8
12
Q1
SN75HVD07DR
D
8
SITE 27
330
0
6.4
5.2
2.1
8
12
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN65HVD05DR
D
8
SITE 27
342.9
336.6
0.0
SN65HVD06DR
D
8
SITE 27
342.9
336.6
0.0
SN65HVD07DR
D
8
SITE 27
342.9
336.6
0.0
SN75HVD05DR
D
8
SITE 27
342.9
336.6
0.0
SN75HVD06DR
D
8
SITE 27
342.9
336.6
0.0
SN75HVD07DR
D
8
SITE 27
342.9
336.6
0.0
Pack Materials-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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