TI UC2907

 SLUS165C – MARCH 1999 - REVISED JANUARY 2002
FEATURES
D Fully Differential High Impedance Voltage
Sensing
SOIC-16 DW PACKAGE
(TOP VIEW)
C/S OUT
C/S (+)
C/S (–)
(–) SENSE
POWER RETURN
ARTIFICIAL GND
VREF
ISET
D Accurate Current Amplifier for Precise
C/S (–)
2
1
CURRENT SHARE BUS
N/C
3
STATUS INDICATE
C/S OUT
PLCC-20, LCC-20,
Q OR L PACKAGE
(TOP VIEW)
C/S (+)
D
D
D
D
Current Sharing
Opto Coupler Driving Capability
1.25% Trimmed Reference
Master Status Indication
4.5-V to 35-V Operation
20 19
18
ADJ OUT
(–) SENSE
5
17
ADJ INPUT
N/C
6
16
POWER RETURN
7
15
8
14
VCC
N/C
OPTO DRIVE
DESCRIPTION
ISET
VREF
9 10 11 12 13
16
15
14
13
12
11
10
9
STATUS INDICATE
CURRENT SHARE BUS
ADJ OUT
ADJ INPUT
COMP
(+) SENSE
VCC
OPTO DRIVE
DIL-16 J or N PACKAGE
(TOP VIEW)
4
ARTIFICIAL GND
1
2
3
4
5
6
7
8
N/C
COMP
(+) SENSE
C/S OUT
C/S (+)
C/S (–)
(–) SENSE
POWER RETURN
ARTIFICIAL GND
VREF
ISET
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
STATUS INDICATE
CURRENT SHARE BUS
ADJ OUT
ADJ INPUT
COMP
(+) SENSE
VCC
OPTO DRIVE
The UCx907 family of load share controller ICs provides all the necessary features to allow
multiple-independent-power modules to be paralleled such that each module supplies only its proportionate share
to total-load current.
This sharing is accomplished by controlling each module’s power stage with a command generated from a
voltage-feedback amplifier whose reference can be independently adjusted in response to a common-share-bus
voltage. By monitoring the current from each module, the current share bus circuitry determines which paralleled
module would normally have the highest output current and, with the designation of this unit as the master, adjusts
all the other modules to increase their output current to within 2.5% of that of the master.
The current share bus signal interconnecting all the paralleled modules is a low-impedance, noise-insensitive line
which will not interfere with allowing each module to act independently should the bus become open or shorted to
ground. The UC3907 controller will reside on the output side of each power module and its overall function is to supply
a voltage feedback loop. The specific architecture of the power stage is unimportant. Either switching or linear designs
may be utilized and the control signal may be either directly coupled or isolated though the use of an optocoupler or
other isolated medium.
Other features of the UC3907 include 1.25% accurate reference: a low-loss, fixed-gain current-sense amplifier, a fully
differential, high-impedance voltage sensing capability, and a status indicator to designate which module is
performing as master.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
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1
SLUS165C – MARCH 1999 - REVISED JANUARY 2002
block diagram
VOLTAGE ERROR AMPLIFIER
(+) SENSE
11
+
12
V CC
1.75 V
0.25 V
GROUND
AMPLIFIER
(–) SENSE
4
POWER RTN
5
9
OPTO DRIVE
V REF
1.75 V
–
GND
+
8
ISET
+
DRV
–
1 kΩ
20 k Ω
50 kΩ
ADJUST
AMPLIFIER
6
14
ADJ OUT
13
ADJ INPUT
15
CURRENT SHARE BUS
16
STATUS INDICATE
50 mV
+
ARTIFICIAL GND
DRIVE
1.0 V AMPLIFIER
COMP
+
+
VCC (4.5 V TO 35 V) 10
–
VREF
7
C/S OUT
1
17.5 kΩ
–
ADJ
+
40 kΩ
2 kΩ
C/S (–)
3
–
2 kΩ
C/S (+)
BUFFER
AMPLIFIER
CURRENT SENSE
AMPLIFIER
100
–
+
+
2
10 k Ω
40 k Ω
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V
Opto out voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V
Opto out current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Status indicate sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
C/S input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V
Share bus voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 35 V
Other analog inputs and outputs (zener clamped) maximum forced voltage . . . . . . . . . . . . . . . . –0.3 V to10 V
Other analog inputs and outputs (zener clamped) maximum forced current . . . . . . . . . . . . . . . . . . . . . ±10 mA
Ground amp sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Pins 1, 9, 12, 15 sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Lead temperature (solder 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Pin Nos. refer to 16 Pin DIL Package.
‡ Currents are positive into, negative out of the specified terminal. Consult packaging section of databook for thermal limitations and considerations
of package.
2
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SLUS165C – MARCH 1999 - REVISED JANUARY 2002
electrical characteristics, these specifications apply for TA = –55°C to 125°C for UC1907, –40°C to
85°C for UC2907, and 0°C to 70°C for UC3907, VIN = 15 V, TA = TJ (unless otherwise stated )
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
1.975
2.000
2.025
V
1.960
2.000
2.040
Voltage Amp Section
COMP = 1 V,
Inp t voltage
Input
oltage
Line regulation
Load regulation
Long term stability
TA = 25°C
over temp
COMP = 1 V,
VIN = 4.5 V to 35 V
IL reference = 0.0 mA to –10 mA
Total output variation
TA = 125°C,
Line, load, temp
1000hrs See Note 2
Input adjust range
ADJ OUT from max high to max low
5
1.960
Input bias current
85
V
15
mV
10
mV
25
mV
2.040
100
115
mV
µA
–1
Open loop gain
COMP = 0.75 V to 1.5 V
Unity gain bandwidth
See Note 2
Output sink current
TA = 25°C
(+) SENSE = 2.2 V,
COMP = 1 V
6
15
mA
Output source current
(+) SENSE = 1.8 V,
COMP = 1 V
400
600
µA
VOUT high
VOUT low
(+) SENSE = 1.8 V,
IL = –400 µΑ
IL = 1 mA
1.85
2
V
(+) SENSE = 2.2 V,
65
dB
700
kHz
0.15
0.40
V
1.970
2.000
2.030
V
1.955
2.000
2.045
–15
–30
–60
mA
200
250
300
mV
5
mV
10
mV
15
mV
60
mV
Reference Section
O tp t voltage
Output
oltage
TA = 25°C
Over operating temp
Short circuit current
VREF = 0.0 V
V
Ground Amp Section
Output voltage
Common mode variation
(–) SENSE from 0.0 V to 2 V
Load regulation
reg lation
IL = 0.0 mA to 20 mA,
IL = 0.0 mA to 20 mA,
TA = 25°C
over temp
Adjust Amp Section
Input offset voltage
ADJ OUT = 1.5 V, VCM = 0.0 V
Input bias current
40
50
µA
–2
Open loop gain
1.5 V ≤ ADJ OUT ≤ 2.25 V
Unity gain bandwidth
TA = 25°C,
COUT =1 µF
See Note 2
IOUT = –10 µA to 10 µA,
VOUT = 1.5 V
1.7
3
4.5
ms
VID = 0.0 V,
VID = 250 mV,
ADJ OUT = 1.5 V
55
135
225
µA
Output source current
ADJ OUT = 1.5 V
110
200
350
µA
VOUT high
VOUT low
VID = 250 mV,
VID = 0.0 V,
IOUT = – 50 mA
IOUT = 50 mA
2.20
2.70
2.90
V
0.75
1.15
Common mode rejection ratio
VCM = 0.0 to 10 V
VOUT ADJ OUT = 1.5 V to 2 V,
∆(+) SENSE/ ∆ADJ OUT
Transconductance
Output sink current
Output gain to V/A
65
dB
500
Hz
70
50
V
dB
57
64
mV/V
NOTE 1: Unless otherwise specified all voltages are with respect to (–) SENSE. Currents are positive into, negative out of the specified terminal.
NOTE 2: Ensured by design. Not production tested.
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3
SLUS165C – MARCH 1999 - REVISED JANUARY 2002
electrical characteristics, these specifications apply for TA = –55°C to 125°C for UC1907, –40°C to
85°C for UC2907, and 0°C to 70°C for UC3907, VIN = 15 V, TA = TJ (unless otherwise stated )
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
19.2
19.6
20.1
V/V
210
250
290
mV
180
250
330
mV
600
µV/V
450
mV
Current Amp Section
Gain
O tp t voltage
Output
oltage
Input offset change with common mode
input
VCM = 0.0 V,
VC/S (+) = VC/S (–) = 0.0 V,
VC/S (+) = VC/S (–) = 0.0 V,
VCM = 0 V to 13 V
VOUT high
VOUT low
VID = 1 V
VID = – 1 V,
Power supply rejection ratio
VIN = 4.5 V to 35 V,
VID = 50 mV to 100 mV
TA = 25°C
over temp
10
IL = 1 mA
VCM = 0.0 V
14.5
350
V
60
Slew rate
dB
0.4
V/µs
Drive Amp Section RSET = 500 Ω to Artificial GND, Opto Drive = 15 V
Voltage gain
COMP = 0.5 V to 1 V
2.3
2.5
2.6
ISET VOUT high
ISET VOUT low
(+) SENSE = 2.2 V
3.8
4.1
4.4
V
270
300
mV
35
V
1.55
1.65
1.75
V
5
mV
5
10
20
kΩ
6
15
(+) SENSE = 1.8 V
Opto out voltage range
4
Zero current input threshold
V/V
Buffer Amp Section
Input offset voltage
Input = 1 V
Output off impedance
Input = 1 V,
output = 1.5 V to 2 V
Output source current
Input = 1 V,
output = 0.5 V
Common mode rejection ratio
VCM = 0.3 V to 10 V
VIN = 4.5 V to 35 V
Power supply rejection ratio
mA
70
dB
70
dB
Under Voltage Lockout Section
Startup threshold
3.7
Threshold hysteresis
200
4.4
V
mV
Status Indicate Section
VOUT low
Output leakage
ADJ OUT = current share bus
ADJ OUT = 1 V,
VOUT = 35 V
0.2
0.5
V
0.1
5
µA
3
5
mA
6
10
mA
Total Stand by Current Section
Startup current
Operating current
VIN = UVLO – 0.2 V
VIN = 35 V
NOTE 1: Unless otherwise specified all voltages are with respect to (–) SENSE. Currents are positive into, negative out of the specified terminal.
NOTE 2: Ensured by design. Not production tested.
4
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SLUS165C – MARCH 1999 - REVISED JANUARY 2002
pin assignments
(–) SENSE: (Pin 4) This is a high-impedance pin allowing remote sensing of the system ground, bypassing any
voltage drops which might appear in the power return line. This point should be considered as the true ground. Unless
otherwise stated, all voltages are with respect to this point.
Artificial Ground: (Pin 6) This is a low-impedance-circuit ground which is exactly 250 mV above the (–) SENSE
terminal. This offset allows the ground buffer amplifier negative headroom to return all the control bias and operating
currents while maintaining a high impedance at the (–) SENSE input.
Power RTN: (Pin 5) This should be the most negative voltage available and can range from zero to 5 V below the
(–) SENSE terminal. It should be connected as close to the power source as possible so that voltage drops across
the return line and current-sensing impedances lie between this terminal and the (–) SENSE point.
VREF: (Pin 7) The internal voltage reference is a band-gap circuit set at 2.0 V with respect to the (–) SENSE input
(1.75 V above the artificial ground), and an accuracy of ±1.5%. This circuit, as well as all the other chip functions, will
work over a supply voltage range of 4.5 V to 35 V allowing operation from unregulated dc, an auxiliary voltage, or
the same output voltage that it is controlling. Under-voltage lockout has been included to insure proper startup by
disabling internal bias currents until the reference rises into regulation.
Voltage Amplifier: (Pins 11, 12) This circuit is the feedback-control-gain stage for the power module’s output-voltage
regulation, and overall-loop compensation will normally be applied around this amplifier. Its output will swing from
slightly above the ground return to an internal clamp of 2.0 V. The reference trimming is performed closed loop, and
measured at pin 11, (+) SENSE. The value is trimmed to 2 V ±1.25%.
Drive Amplifier: (Pins 8, 9, 12) This amplifier is used as an inverting buffer between the voltage amplifier’s output
and the medium used to couple the feedback signal to the power controller. It has a fixed-voltage gain of 2.5 and is
usually configured with a current-setting resistor to ground. This establishes a current-sinking output optimized to
drive optical couplers biased at any voltage from 4.5 V to 35 V, with current levels up to 20 mA. The polarity of this
stage is such that an increasing voltage at the voltage amplifier’s sense input (as, for example, at turnon) will increase
the opto’s current. In a nonisolated application, a voltage signal ranging from 0.25 V to 4.1 V may be taken from the
current-setting output but it should be noted that this voltage will also increase with increasing sense voltage and an
external inverter may be required to obtain the correct feedback polarity.
Current Amplifier: (Pins 1, 2, 3) This amplifier has differential-sensing capability for use with an external shunt in
the power-return line. The common mode range of its input will accommodate the full range between the power return
point and VCC-2 V which will allow undefined-line impedances on either side of the current shunt. The gain is
internally set at 20, giving the user the ability to establish the maximum-voltage drop across the current-sense resistor
at any value between 50 mV and 500 mV. While the bandwidth of this amplifier may be reduced with the addition of
an external-output capacitor to ground, in most cases this is not required as the compensation of the adjust amplifier
will typically form the dominant pole in the adjust loop.
Buffer Amplifier: (Pins 1, 15) This amplifier is a unidirectional buffer which drives the current-share bus. The line
which will interconnect all power modules paralleled for current sharing. Since the buffer amplifier will only source
current, it insures that the module with the highest-output current will be the master and drive the bus with a
low-impedance drive capability. All other buffer amplifiers will be inactive with each exhibiting a 10-kΩ load impedance
to ground. The share bus terminal is protected against both shorts to ground and accidental voltages in excess of
50 V.
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SLUS165C – MARCH 1999 - REVISED JANUARY 2002
pin assignments
Adjust Amplifier: (Pins 13, 14, 15) This amplifier adjusts the individual module’s reference voltage to maintain
equal-current sharing. It is a transconductance type in order that its bandwidth may be limited and noise kept out of
the reference-adjust circuitry, with a simple capacitor to ground. The function of this amplifier is to compare its own
module-output current to the share-bus signal, which represents the highest output current. This will force an adjust
command which is capable of increasing the reference voltage as seen by the voltage amplifier by as much as 100
mV. This number stems from the 17.5:1 internal resistor ratio between the adjust amplifier’s clamped output and the
reference, and represents a 5% total range of adjustment. This value should be adequate to compensate for
unit-to-unit reference and external-resistor tolerances. The adjust amplifier has a built-in 50-mV offset on its inverting
input which will force the unit acting as the master to have a low output, resulting in no change to the reference. While
this 50-mV offset represents an error in current sharing, the gain of the current amplifier reduces it to only 2.5 mV
across the current-sense resistor. It should also be noted that when the module is acting independently with no
connection to the share bus node, or when the share bus node is shorted to ground, its reference voltage will be
unchanged. Since only the circuit acting as a master will have a low output from the adjust amplifier, this signal is used
to activate a flag output to identify the master, should some corrective action be needed.
Status Indicate: (Pin 16) This pin is an open-collector output intended to indicate the unit which is acting as the
master. It achieves this by sensing when the adjust amp is in its low state and pulling the status-indicate pin low.
additional information
Please refer to additional application information.
1. By Mark Jordan, UC3907 Load Share IC Simplifies Parallel Power Supply Design, TI Literature Number
SLUA147.
2. By Laszlo Balogh, UC3902 Load Share Controller and its Performance in Distributed Power Systems, TI
Literature Number SLUA128.
UDG-94103
Figure 1. Load System Diagram
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SLUS165C – MARCH 1999 - REVISED JANUARY 2002
additional information (continued)
V CC
0–20 mA
ISOLATED
CONTROL
UC3907
12
+
1.0 V
VOLTAGE ERROR
AMPLIFIER
(+) SENSE
11
V REFRANGE 2.0 V–2.1 V
–
20 k Ω
–
DRIVE
AMPLIFIER
+
9
ISET
50 k Ω
0–4 V
DIRECT
CONTROL
8
+
REF
MASTER
INDICATE
1.75 V
7
V CC
16
V CC
1.750 V
REF
10
+
0.250 V
ADJUST AMPLIFIER
+
GND
AMPLIFIER
–
50 mV
+
–
( ) SENSE
4
+
20X
–
+
BUFFER
AMPLIFIER
–
+
CURRENT
SHARE
BUS
15
10 k Ω
ARTIFICIAL GND
6
2
FROM LOAD
3
14
CURRENT
SENSE
+
1
ADJ
COMP
13
C/S OUT
5
ADJ IN
PWR RET
TO PWR
RETURN
MODULE LOAD CURRENT
UDG-99053
Figure 2. Load System Connection Diagram
UDG-94105
Figure 3. UC3907 In a Load-Sharing Feedback Loop for an Off-Line Isolated Supply
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7
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