TI UC2826

UC1826
UC2826
UC3826
Secondary Side Average Current Mode Controller
FEATURES
DESCRIPTION
•
Practical Secondary Side Control of
Isolated Power Supplies
•
1MHz Operation
•
Tailored Loop Bandwidth Provides
Excellent Noise Immunity
•
Voltage Feedforward Provides
Superior Transient Response
•
Accurate Programmable Maximum
Duty Cycle
The UC1826 family of average current mode controllers accurately
accomplishes secondary side average current mode control. The secondary side output voltage is regulated by sensing the output voltage
and differentially sensing the AC switching current. The sensed output
voltage drives a voltage error amplifier. The AC switching current, monitored by a current sense resistor, drives a high bandwidth, low offset
current error amplifier. The output of the voltage error amplifier can be
used to drive the current amplifier which filters the measured inductor
current. Fast transient response is accomplished by utilizing voltage
feedforward in generating the PWM ramp.
•
Multiple Chips Can be Synchronized
to Fastest Oscillator
•
Wide Gain Bandwidth Product
(70MHz, Acl>10) Current Error
Amplifier
•
Up to Ten Devices Can Easily Share
a Common Load
The UC1826 features load share, oscillator synchronization, undervoltage lockout, and programmable output control. Multiple chip operation
can be achieved by connecting up to ten UC1826 chips in parallel. The
SHARE bus and CLKSYN bus provide load sharing and synchronization to the fastest oscillator respectively. With its tailored bandwidth, the
UC1826 provides excellent noise immunity and is an ideal controller to
achieve high power, secondary side average current mode control.
BLOCK DIAGRAM
Pin Numbers refer to 24-pin packages.
7/95
UDG-95013
UC1826
UC2826
UC3826
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . . . . . . . .−65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . .−65°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . .+300°C
All voltages with respect to VEE except where noted; all currents
are positive into, negative out of the specified terminal.
Consult Packaging Section of Databook for thermal limitations
and considerations of packages.
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20V
Output Current Source or Sink . . . . . . . . . . . . . . . . . . . . . .0.3A
Analog Input Voltages . . . . . . . . . . . . . . . . . . . . . . .−0.3V to 7V
ILIM, KILL, SEQ, ENBL, RUN, PWRSEN, PWROK . . . .−0.3V to 7V
CLKSYN Current Source . . . . . . . . . . . . . . . . . . . . . . . . .20mA
RUN Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA
SEQ Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA
RDEAD Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA
RAMP Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA
Share Bus Voltage (voltage with respect to GND) . . .0V to 6.2V
ADJ Voltage (voltage with respect to GND) . . . . . .0.9V to 6.3V
VEE (voltage with respect to GND) . . . . . . . . . . . . . . . . . .−1.5V
RECOMMENDED OPERATING CONDITIONS
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V to 20V
Sink/Source Output Current . . . . . . . . . . . . . . . . . . . . . .250mA
Timing Resistor RT . . . . . . . . . . . . . . . . . . . . . . . . . .1k to 200k
Timing Capacitor CT . . . . . . . . . . . . . . . . . . . . . . . .75pF to 2nF
CONNECTION DIAGRAMS
DIL-24, SOIC-24,TSSOP-24 (Top View)
J or N, DW, PW Packages
PLCC-28 (Top View)
Q Package
ELECTRICAL CHARACTERISTICS Unless otherwise stated these specifications apply for TA = −55°C to +125°C for
UC1826; −40°C to +85°C for UC2826; and 0°C to +70°C for UC3826; VCC = 12V, VEE = GND, Output no load, CT = 345pF,
RT = 4kΩ, RDEAD = 1000Ω, CRAMP = 345pF, RRAMP = 35.2kΩ, RCLKSYN = 1k, TA = TJ.
PARAMETER
Current Error Amplifier
Ib
Vio
Avo
GBW (Note 2)
Vol
Voh
TEST CONDITIONS
MIN
TYP
0.5
0.75
TA = +25°C
Over Temperature
Acl = 10, RIN = 1k, CC = 15pF, f = 200kHz (Note 1)
IO = 1mA, Voltage above VEE
IO = 0mA
IO = −1mA
Voltage Error Amplifier
Ib
Vio
Avo
60
45
2
3
3
5
µA
mV
mV
dB
MHz
V
V
V
3
5
µA
mV
dB
90
70
0.5
3.8
3.5
0.5
60
MAX UNITS
90
UC1826
UC2826
UC3826
ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated these specifications apply for TA = −55°C to
+125°C for UC1826; −40°C to +85°C for UC2826; and 0°C to +70°C for UC3826; VCC = 12V, VEE = GND, Output no load, CT =
345pF, RT = 4kΩ, RDEAD = 1000Ω, CRAMP = 345pF, RRAMP = 35.2kΩ, RCLKSYN = 1k, TA = TJ.
PARAMETER
Voltage Error Amplifier (cont.)
GBW (Note 2)
Vol
Voh
Voh-ILIM
2X Amplifier and Share Amplifier
V offset (b; y = mx + b)
GAIN (m; y = mx + b)
GBW (Note 2)
RSHARE
Total Offset
Vol
Voh
Adjust Amplifier
Vio
gm
Vol
Voh
Oscillator
Frequency
Max Duty Cycle
OSC Ramp Amplitude
Ramp Saturation
Clock Driver/SYNC (CLKSYN)
Vol
Voh
TEST CONDITION
MIN
f = 200kHz
IO = 175mA, Volts above VEE
ILIM = 3V
Tested ILIM = 0.5V, 1.0V, 2.0V
2.85
−100
Slope with AVOUT = 1V and 2V
1.98
VCC = 0, VSHARE/ISHARE
Negative supply is VEE, GND Open,VAO = GND
VAO = Voltage Amp Vol, Volts above VEE
IO = 0mA, ILIM = 3V, VAO = Voltage Amp Voh
IO = −1mA, ILIM = 3V, VAO = Voltage Amp Voh
−75
0.2
5.7
5.7
0.9
0.85
5.7
5.7
450
72
2
IO = 10mA, OSC = 0V
RCLKSYN = 200Ω
ISOURCE
RCLKSYN
VTH
VREF Comparator
Turn-on Threshold
Hysteresis
VCC Comparator
Turn-on Threshold
Hysteresis
PWR Sense Comparator
Voltage Threshold
Vol
Voh
KILL Comparator
Voltage Threshold
MAX UNITS
7
40
IO = −2µA to 2µA, CADJ = 0.1µF
IOUT = 0
IOUT = 2µA
IOUT = 0, VSHARE = 6.5V
IOUT = −2µA, VSHARE = 6.5V
TYP
VCC = 0, VCLKSYN/ICLKSYN
3
0.6
3.15
100
20
2.02
100
200
0
0.45
6
6
75
0.6
6.3
6.3
mV
V
kHZ
kΩ
mV
V
V
V
60
−0.1
1
1
6
6
80
−0.3
1.1
1.15
6.3
6.3
mV
mS
V
V
V
V
500
76
2.2
0.44
550
80
2.4
0.8
kHz
%
V
V
0.02
3.6
3.5
25
10
1.5
0.2
V
V
V
mA
k
V
4.65
0.4
7.9
8.4
0.4
1.25
0.3
4
IO = 1mA
IO = −100µA
3
3
MHz
V
V
mV
V
V
8.9
0.4
V
V
V
V
V
V
UC1826
UC2826
UC3826
ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated these specifications apply for TA = −55°C to
+125°C for UC1826; −40°C to +85°C for UC2826; and 0°C to +70°C for UC3826; VCC = 12V, VEE = GND, Output no load, CT =
345pF, RT = 4kΩ, RDEAD = 1000Ω, CRAMP = 345pF, RRAMP = 35.2kΩ, RCLKSYN = 1k, TA = TJ.
PARAMETER
Sequence Comparator
Voltage Threshold
SEQ SAT
Enable Comparator
Voltage Threshold
RUN SAT
Reference
VREF
Line Regulation
Load Regulation
Short Circuit I
Output Stage
Rise Time
Fall Time
Voh
Vol
Virtual Ground
VGND − VEE
TEST CONDITION
MIN
TYP
MAX UNITS
IO = 10mA
2.5
0.25
V
V
IO = 10mA
2.5
0.2
V
V
TA = 25°C
VCC = 15V
10 < VCC < 20
0 < IO < 10mA
VREF = 0V
4.95
4.9
30
CL = 100pF
CL = 100pF
VCC > 11V, IO = −10mA
IO = −200mA
IO = 200mA
IO = 10mA
VEE is externally supplied, GND is floating
and used as Signal GND.
8.0
7.8
5
3
3
60
5.05
5.1
15
15
90
V
V
mV
mV
mA
10
10
8.4
20
20
8.8
ns
ns
V
V
V
V
3.0
0.5
0.2
0.75
Icc
Icc (run)
21
30
Note 1: Guaranteed by design. Not 100% tested in production.
Note 2: Unless otherwise specified all voltages are with respect to GND. Currents are positive into, negative out of the
specified terminal.
V
mA
PIN DESCRIPTIONS
ADJ: The output of the transconductance (gm = −0.1mS)
amplifier adjusts the control voltage to maintain equal current sharing. The chip sensing the highest output current
will have its output clamped to 1V. A resistor divider
between VREF and ADJ drives the control voltage (VA+)
for the voltage amplifier. Each slave unit’s ADJ voltage
increases (to a maximum of 6V) its control voltage (VA+)
until its load current is equal to the master. The 60mV
input offset on the gm amplifier guarantees that the unit
sensing the highest load current is chosen as the master.
The 60mV offset is guaranteed by design to be greater
than the inherent offset of the gm amplifier and the buffer
amplifier. While the 60mV offset represents an error in
current sharing, the gain of the current and 2X amplifiers
reduces it to only 30mV. The total current sense gain is
the current amplifier gain. This pin needs a 0.1µF capacitor to compensate the amplifier.
CA-, CA+: The inverting and non-inverting inputs to the
current error amplifier. This amplifier needs a capacitor
between CA- and CAO to set its dominant pole.
CAO: The output of the current error amplifier which is
internally clamped to 4V. It is internally connected to the
inverting input of the PWM comparator.
CLKSYN: The clock and synchronization pin for the
oscillator. This is a bidirectional pin that can be used to
synchronize several chips to the fastest oscillator. Its
input synchronization threshold is 1.4V. The CLKSYN
voltage is 3.6V when the oscillator capacitor CT is being
discharged, otherwise it is 0V.
4
UC1826
UC2826
UC3826
PIN DESCRIPTIONS (cont.)
ENBL: The active low input with a 2.5V threshold
enables the output to switch. SEQ and RUN are driven
low when ENBL is above its 2.5V threshold.
VCC and GND to accomplish feedforward. The PWM
output drives this pin. When the output is high, the transistor is off enabling the charging of the RAMP capacitor.
When the output transitions low, the transistor is turned
on discharging the RAMP capacitor. The voltage at
RAMP rises from 0.2V to near 4V at maximum duty
cycle. Although this is an exponential ramp at high VCC
voltage the ramp appears linear.
GND: The signal ground used for the voltage sense
amplifier, current error amplifier, current error amplifier,
voltage reference, 2X amplifier, and share amplifier. The
output sink transistor is wired directly to this pin.
KILL: The active low input with a 3.0V threshold stops
the output from switching. Once this function is activated
RUN must be cycled low by driving KILL above 3.0V and
either resetting the power to the chip (VCC) or resetting
the ENBL signal.
RDEAD: The pin that programs the maximum duty cycle
by connecting a resistor between it and OSC. The maximum duty cycle is decreased by increasing this resistor
value which increases the discharge time. The dead
time, the time when the output is low, is 2 RDEAD CT.
The CT capacitance should be increased by approximately 40pF to account for parasitic capacitance.
·
ILIM: A voltage on this pin programs the voltage error
amplifier’s Voh clamp. The voltage error amplifier output
represents the average output current. The Voh clamp consequently limits the output current. If ILIM is tied to VREF, it
defaults to 3.0V. A voltage less than 3.0V connected to
ILIM clamps the voltage error amplifier at this voltage and
consequently limits the maximum output current.
RUN: This is an open collector logic output that signifies
when the chip is operational. RUN is pulled high to VREF
through an external resistor when VCC is greater than
8.4V, VREF is greater than 4.65V, SEQ is greater than
2.5V, and KILL lower than 3.0V. RUN connected to the
VA+ pin and to a capacitor to ground adds an RC rise
time on the VA+ pin initiating a soft start.
OSC:The oscillator ramp (not to be confused with PWM
ramp) pin has a capacitor CT to ground and two resistors
in series RT and RDEAD to VREF. The total resistance of
RT and RDEAD divided by VREF − VOSC sets exponential
charge current. The oscillator charges from 1.2V to 3.4V
until the output transitions low. At this time an open collector transistor is turned on and discharges the C T
capacitor through RDEAD.
SEQ: The sequence pin allows the sequencing of startup
for multiple units. A resistor between VREF and SEQ and
a capacitor between SEQ and GND create a unique RC
rise time for each unit which sequences the output startup.
SHARE:The nearly DC voltage representing the average
output current. This pin is wired directly to all SHARE
pins and is the load share bus.
The charge time is approximately TCHARGE = 2(R T +
RDEAD) CT when the RDEAD resistor is used.
·
The dead time is approximately TDISCHARGE = 2
CT.
1
(1) Frequency ≈
TCHARGE + TDISCHARGE
(2) Maximum Duty Cycle ≈
·
· RDEAD ·
VA-, VA+: The inverting and non-inverting inputs to the
voltage error amplifier.
VAO: The output of the voltage error amplifier. Its Voh is
clamped with the ILIM pin.
TCHARGE
VCC: The input voltage to the chip. The chip is operational between 8.4V and 20V.
TCHARGE + TDISCHARGE
VEE: The negative supply voltage to the chip which powers the lower voltage rail for all amplifiers. The chip is
operational if VEE is connected to GND or if GND is
floating. When voltage is applied externally to VEE, GND
becomes a virtual ground because of an internal diode
between VEE and GND. The GND current flows through
the forward biased diode and out VEE. GND is always
the signal ground from which the voltage reference and
all amplifier inputs are referenced.
The CT capacitance should be increased by approximately 40pF to account for parasitic capacitance.
OUT: The output of the PWM driver. It has an upper
clamp of 8.5V. The peak current sink and source are
250mA. All UVLO, SEQ, ENBL, and KILL logic either
enable or disable the output driver.
PWRSEN: This pin is the input to the PWROK comparator.
PWROK: The output pin from the PWROK comparator. It
has a 300µA current source output when driven high.
VREF: The reference voltage equal to 5.0V.
RAMP: An open collector that can sink 20mA to discharge the oscillator capacitor. An RC is tied between
5
UC1826
UC2826
UC3826
UDG-95014-1
Figure 1. Oscillator Block with External Connections
CIRCUIT DESCRIPTION:
·
·
The oscillator block diagram with external wiring is
shown in Figure 1. OSC has a capacitor (CT) to ground
and two resistors in series (RT and RDEAD) to VREF. The
total resistance of RT and RDEAD divided by VREF −
VOSC sets the exponential charge current. The oscillator
charges from 1.2V to a 3.4V threshold with an RC time
·
As shown in Figure 3, several oscillators are synchronized to the highest free running frequency by connecting 100pF capacitors in series with each CLKSYN pin
and connecting the other side of the capacitors together
forming the CLKSYN bus. The CLKSYN bus is then
pulled down to ground with a resistance of approximately
10k. Referring to Figure 1, the synchronization threshold
is 1.4V. The oscillator blanks any synchronization pulse
that occurs when OSC is below 2.5V. This allows units,
once they discharge below 2.5V, to continue through the
current discharge and subsequent charge cycles
whether or not other units on the CLKSYN bus are still
synchronizing. This requires the frequency of all free running oscillators to be within 40% of each other to guarantee synchronization.
3.0-
OSC
·
delay of 2
CT (RDEAD + RT). After exceeding this
threshold, the RS flip-flop is set driving CLKSYN high
and RDEAD low which discharges CT. At this time and
open collector transistor is turned on and discharges CT
capacitor through RDEAD with a RC time delay of 2
CT
RDEAD. The oscillator and ramp waveforms are
shown in Figure 2. Equations to attain frequency and
maximum duty cycle are listed under the OSC pin
description.
PWM Oscillator: The chip has two pins that set RC time
constants. The resistor and capacitor tied to RAMP create the ramp used as the input to the PWM comparator.
When the output pin OUT is high, RAMP charges until it
passes the PWM comparator threshold. The output is
then driven low and RAMP is discharged. The resistors
and capacitor on the OSC pin are used to set the PWM
operating frequency and its maximum duty cycle.
1.0
CLKSYN
OUT
CAO
Grounds, Voltage Sensing and Current Sensing: The
voltage is sensed directly at the load. Proper load sharing requires the same sensed voltage for each power
supply connected in parallel. Referring to Figure 4, the
RAMP
Figure 2. Oscillator and PWM Output Waveform
6
UC1826
UC2826
UC3826
CIRCUIT BLOCK DESCRIPTION (cont.)
Figure 4 shows one recommended voltage and current
sensing scheme when VEE is connected to GND. The
signal ground is the negative sense point for the output
voltage and the positive sense point for the output current. VEE is the negative supply for the current sense
amplifier. When it is separated from GND, it extends the
current sense amplifier’s common mode input voltage
range to include VEE which is approximately −0.7V
below ground. The resistor RADJ is used for load sharing.
The unit which is the master will force VADJ to 1.0V.
Therefore, the regulated voltage being sensed is actually
VSP − VSM = (VREF − VADJ)
RADJ
· ( R1 + R ) + VADJ
ADJ
VSM = 0V, VADJ = 1V (master), VREF = 5V
VSP = 4
RADJ
· (R1 + R )
+ 1V
ADJ
The voltage at ADJ on the slave chips will increase forcing their load currents to increase to match the master.
UDG-95015
The AC frequency response of the voltage error amplifier
is shown in Figure 5.
Figure 3. Oscillator Synchronization
Connection Diagram
positive sense voltage (VSP) connects to the voltage
error amplifier inverting terminal (VA-), the return lead for
the on-chip reference is used as the negative sense
(VSM). The current is sensed across the shunt resistor,
RS. The voltage across the shunt resistor is level shifted
up so that the maximum voltage across Rs corresponds
to the voltage error amplifier Voh.
∅m ≈
Figure 5. AC Frequency Response of the Voltage
Error Amplifier
Startup and Shutdown: Isolated power up can be
accomplished using the UCC1889. Application Note
U-149 is available for additional information.
The UC1826 offers several features that enhance startup
and shutdown. Soft start is accomplished by connecting
RUN to VA+ and a capacitor to ground. The resulting RC
rise time on the VA+ pin initiates a soft start. It can also
be accomplished by connecting RUN to ILIM. When RUN
is low it will command zero load current, guaranteeing a
soft start. The undervoltage lockout (UVLO) is a logical
AND of ENBL < 2.5V, SEQ > 2.5V, VCC > 8.4V and
UDG-95016
Figure 4.Voltage and Current Sense VEE Tied to GND
7
UC1826
UC2826
UC3826
CIRCUIT BLOCK DESCRIPTION (cont.)
VREF > 4.65V. The block diagram shows that the thresholds are set by comparators. By placing an RC divider on
the SEQ pin, the enabling of multiple chips can be
sequenced with different RC time constants. Similarly,
different RC time constants on the ENBL pins can
sequence shutdown. The UVLO keeps the output from
switching; however the internal reference starts up with
VCC less than 8.4V. The KILL input shuts down the
switching of the chip. This can be used in conjunction
with an overvoltage comparator for overvoltage protection. In order to restart the chip after KILL has been initiated, the chip must be powered down and then back up.
A pulse on the ENBL pin also accomplishes this without
actually removing voltage to the VCC pin.
Current Control Loop: The current error amplifier (CEA)
needs its loop compensated externally. The zero crossing
can be calculated with Equation 3.
(3)
1
Frequency (0dB) =
·
2π RINV CCOMP
RINV is the input resistance at the inverting terminal CACCOMP is the capacitance between CA- and CAO.
Although it is only unity gain stable for a BW of 7MHz,
the amplifier is typically configured with a differential gain
of at least 10, allowing the amplifier to operate with sufficient phase margin at a GBW of 70MHz. A closed loop
gain of 10 attenuates the output by 20.8dB
20.8 = 20log
Load Sharing: Load sharing is accomplished similarly to
the UC1907 except it has the added constraint of using
the sensed current for average current mode control. The
sensed current for the UC1826 has an AC component
that is amplified and then averaged. The voltage error
amplifier represents this average current. The voltage
error amplifier output is the current command signal and
its voltage represents the average output load current.
The ILIM pin programs the upper clamp voltage of this
amplifier and consequently the maximum load current. A
gain of 2 amplifier connected between the voltage error
amplifier output and the share amplifier input increases
the current share resolution and noise margin. The average current is used as an input to a source only load
share buffer amplifier. The output of this amplifier is the
current share bus. The IC with the highest sensed current will have the highest voltage on the current share
bus and consequently act as the master. The 60mV input
offset guarantees that the unit sensing the highest load
current is chosen as the master.
·
1
11
to the inverting terminal assuring stability. The amplifier’s
gain fed back into the inverting terminal is less than unity
at 7MHz, where the phase margin begins to roll off. See
Figure 6 for a typical Bode plot.
−
The adjust amplifier is used by the remaining (slave) ICs
to adjust their respective references high in order to balance each IC’s load current. The master’s ADJ pin will be
at its 1.0V clamp and connected back to the non-inverting voltage error amplifier input through a high value
resistor. This requires the user to initially calculate the
control voltage with the ADJ pin at 1.0V.
β
∅m
Figure 6. Current Error Amplifier Bode Plot
The current error amplifier bandwidth is rolled off and
controlled by the voltage error amplifier output. The maximum load current is limited to approximately the maximum voltage across the shunt resistor (maximum of
200mV) divided by RS:
VREF can be adjusted 150mV to 300mV which compensates for 5% unit to unit reference mismatch and external
resistor mismatch. RADJ will typically be 10 to 30 times
larger than R1. This also attenuates the overall variation of
the ADJ clamp of 1V ±100mV by a factor of 10 to 30, contributing only a 3mV to 10mV additional delta to VREF.
Refer to the UC3907 Application Note U-130 for further
information on parallel power supply load sharing.
(4) IMAXload = VRs
RS
ILIM sets the maximum current limit by setting the Voh
clamp on the voltage error amplifier. If ILIM is not set to
limit the Voh to be equal to the maximum voltage across
RS, VAO must be attenuated to match the maximum volt-
8
UC1826
UC2826
UC3826
CIRCUIT BLOCK DESCRIPTION (cont.)
age VRS across the shunt resistor. By attenuating the
maximum voltage at VAO to be equal to VRS, the current
control loop keeps the load from exceeding its current
limit. If the ILIM pin is connected to VREF, the Voh is set
at 3.0V. The maximum current limit clamp can be
reduced by reducing the voltage on ILIM to less than
3.0V as described in the ILIM pin description.
Design Example: Figure 7 is an open loop test that lets
the user test the circuit blocks discussed without having
to build an entire control loop. The pulse width can be
varied by either the VADJ or the VISENSE inputs. Figure 8
shows an isolated power supply using the UC1826 secondary side average current mode controller.
UDG-95017-1
Figure 7. Open Loop Circuit
9
Figure 8. UC1826 Application Diagram
UC1826
UC2826
UC3826
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. 603-424-2410 • FAX 603-424-3460
10
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1999, Texas Instruments Incorporated