UC1849 UC2849 UC3849 Secondary Side Average Current Mode Controller FEATURES DESCRIPTION • Practical Secondary Side Control of Isolated Power Supplies • 1MHz Operation • Differential AC Switching Current Sensing • Accurate Programmable Maximum Duty Cycle • Multiple Chips Can be Synchronized to Fastest Oscillator The UC1849 family of average current mode controllers accurately accomplishes secondary side average current mode control. The secondary side output voltage is regulated by sensing the output voltage and differentially sensing the AC switching current. The sensed output voltage drives a voltage error amplifier. The AC switching current, monitored by a current sense resistor, drives a high bandwidth, low offset current sense amplifier. The outputs of the voltage error amplifier and current sense amplifier differentially drive a high bandwidth, integrating current error amplifier. The sawtooth waveform at the current error amplifier output is the amplified and inverted inductor current sensed through the resistor. This inductor current downslope compared to the PWM ramp achieves slope compensation, which gives an accurate and inherent fast transient response to changes in load. • Wide Gain Bandwidth Product (70MHz, Acl>10) Current Error and Current Sense Amplifiers • Up to Ten Devices Can Easily Share a Common Load The UC1849 features load share, oscillator synchronization, undervoltage lockout, and programmable output control. Multiple chip operation can be achieved by connecting up to ten UC1849 chips in parallel. The SHARE bus and CLKSYN bus provide load sharing and synchronization to the fastest oscillator respectively. The UC1849 is an ideal controller to achieve high power, secondary side average current mode control. BLOCK DIAGRAM Pin numbers refer to 24-pin packages. UDG-94110 7/95 UC1849 UC2849 UC3849 Junction Temperature . . . . . . . . . . . . . . . . . . .−65°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . .+300°C All voltages with respect to VEE except where noted; all currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20V Output Current Source or Sink . . . . . . . . . . . . . . . . . . . . . .0.3A Analog Input Voltages . . . . . . . . . . . . . . . . . . . . . . .−0.3V to 7V ILIM, KILL, SEQ, ENBL, RUN . . . . . . . . . . . . . . . .−0.3V to 7 V CLKSYN Current Source . . . . . . . . . . . . . . . . . . . . . . . . .12mA RUN Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA SEQ Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA RDEAD Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA Share Bus Voltage (voltage with respect to GND) . . .0V to 6.2V ADJ Voltage (voltage with respect to GND) . . . . . .0.9V to 6.3V VEE (voltage with respect to GND) . . . . . . . . . . . . . . . . .−1.5V Storage Temperature . . . . . . . . . . . . . . . . . . .−65°C to +150°C RECOMMENDED OPERATING CONDITIONS Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V to20V Sink/Source Output Current . . . . . . . . . . . . . . . . . . . . . .250mA Timing Resistor (RT) . . . . . . . . . . . . . . . . . . . . . . . . .1k to 200k Timing Capacitor (CT) . . . . . . . . . . . . . . . . . . . . . .75pF to 2nF CONNECTION DIAGRAMS DIL-24, SOIC-24,TSSOP-24 (Top View) J or N, DW, PW Packages PLCC-28 (Top View) Q Package ELECTRICAL CHARACTERISTICS Unless otherwise stated these specifications apply for TA = −55°C to +125°C for UC1849; −40°C to +85°C for UC2849; and 0°C to +70°C for UC3849; VCC = 12V, VEE = GND, Output no load, CT = 345pF, RT = 4530Ω, RDEAD = 511Ω, RCLKSYN = 1k, TA = TJ. PARAMETER Current Sense Amplifier Ib Vio Avo GBW (Note 2) Vol Voh CMRR PSRR Current Error Amplifier Ib Vio TEST CONDITIONS MIN TYP 0.5 TA = +25°C Over Temperature Acl = 1, RIN = 1k, CC = 15pF, f = 200kHz (Note 1) Io = 1mA, Voltage above VEE Io = 0mA Io = −1mA −0.2 < Vcm < 8V 10V < VCC < 20V 60 4.5 3 3 5 µA mV mV dB MHz V V V dB dB 3 20 µA mV 90 7 0.5 3.8 3.5 80 80 0.5 3 2 MAX UNITS UC1849 UC2849 UC3849 ELECTRICAL CHARACTERISTICS Unless otherwise stated these specifications apply for TA = −55°C to +125°C for UC1849; −40°C to +85°C for UC2849; and 0°C to +70°C for UC3849; VCC = 12V, VEE = GND, Output no load, CT = 345pF, RT = 4530Ω, RDEAD = 511Ω, RCLKSYN = 1k, TA = TJ. PARAMETER Current Error Amplifier (cont.) Avo GBW (Note 2) Vol Voh CMRR PSRR Voltage Error Amplifier Ib Vio Avo GBW (Note 2) Vol Voh Voh - ILIM CMRR PSRR 2X Amplifier and Share Amplifier V offset (b; y = mx + b) GAIN (m; y = mx + b) GBW (Note 2) RSHARE Total Offset Vol Voh Adjust Amplifier Vio gm Vol Voh TEST CONDITION Acl = 1, RIN = 1k, CC=15pF, f=200kHz (Note 1) IO = 1mA, Voltage above VEE IO = 0mA IO = −1mA −0.2 < Vcm < 8V 10V < VCC < 20V TYP 60 4.5 90 7 0.5 3.8 3.5 80 80 60 4.5 f = 200kHz IO = 175µA, Volts above VEE ILIM > 3V Tested ILIM = 0.5V, 1.0V, 2.0V −0.2 < Vcm < 8V 10V < VCC < 20V 2.85 −100 Slope with AVOUT = 1V and 2V 1.98 VCC = 0, VSHARE/ISHARE Negative supply is VEE, GND Open, VAO = GND VAO = Voltage Amplifier Vol, Volts above VEE IO = 0mA, ILIM = 3V, VAO = Voltage Amp Voh IO = −1mA, ILIM = 3V, VAO = Voltage Amp Voh RCLKSYN = 200Ω VCC = 0, VCLKSYN/ICLKSYN 3 0.5 2 90 7 0.3 3 MAX UNITS dB MHz V V V dB dB 3 5 0.6 3.15 100 80 80 −75 0.2 5.7 5.7 40 IOUT= −10µA to 10µA, VOUT = 3.5V, CADJ = 1µF IOUT = 0 IOUT = 50µA IOUT = 0, VSHARE = 6.5V IOUT = −50µA, VSHARE = 6.5V Oscillator Frequency Max Duty Cycle OSC Ramp Amplitude Clock Driver/SYNC (CLKSYN) Vol Voh ISOURCE RCLKSYN VTH MIN 20 2.02 100 200 0 0.45 6 6 75 0.6 6.3 6.3 60 80 µA mV dB MHz V V mV dB dB mV V kHZ k mV V V V 0.9 0.85 5.7 5.7 1 1 6 6 1.1 1.15 6.3 6.3 mV mS V V V V 450 80 2 500 85 2.5 550 90 2.8 kHz % V 0.02 3.6 3.2 25 10 1.5 0.2 V V V mA k V −1 UC1849 UC2849 UC3849 ELECTRICAL CHARACTERISTICS (cont)Unless otherwise stated these specifications apply for TA = −55°C to +125°C for UC1849; −40°C to +85°C for UC2849; and 0°C to +70°C for UC3849; VCC = 12V, VEE = GND, Output no load, CT = 345pF, RT = 4530Ω, RDEAD = 511Ω, RCLKSYN = 1k, TA = TJ. PARAMETER VREF Comparator Turn-on threshold Hysteresis VCC Comparator Turn-on Threshold Hysteresis KILL Comparator Voltage Threshold Sequence Comparator Voltage Threshold SEQ SAT Enable Comparator Voltage Threshold RUN SAT Reference VREF VREF Line Regulation Load Regulation Short Circuit I Output Stage Rise Time Fall Time Voh Vol Virtual Ground VGND-VEE TEST CONDITION MIN TYP MAX UNITS 4.65 0.4 7.9 8.3 0.4 V V 8.7 V V 3 V IO = 10mA 2.5 0.25 V V IO = 10mA 2.5 0.25 V V TA = 25°C VCC = 15V 10 < VCC < 20 0 < Io < 10mA VREF = 0V 4.95 4.9 30 CL = 100pF CL = 100pF VCC > 11V, IO = −10mA IO = −200mA IO = 200mA IO = 10mA VEE is externally supplied, GND is floating and used as Signal GND. Icc Icc (run) 8.0 7.8 5 3 3 60 5.05 5.1 15 15 90 V V mV mV mA 10 10 8.4 20 20 8.8 ns ns V V V V 3.0 0.5 0.2 0.75 21 V 30 mA Note 1: If a closed loop gain greater than 1 is used, the possible GBW will increase by a factor of ACL + 10; where ACL is the closed loop gain. Note 2: Guaranteed by design. Not 100% tested in production. Note 3: Unless otherwise specified all voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. PIN DESCRIPTIONS ADJ: The output of the transconductance (gm = −1mS) amplifier adjusts the control voltage to maintain equal current sharing. The chip sensing the highest output current will have its output clamped to 1V. A resistor divider between VREF and ADJ drives the control voltage (VA+) for the voltage amplifier. Each slave unit’s ADJ voltage increases (to a maximum of 6V) its control voltage (VA+) until its load current is equal to the master. The 60mV input offset on the gm amplifier guarantees that the unit sensing the highest load current is chosen as the mas- ter. The 60mV offset guarantees by design to be greater than the inherent offset of the gm amplifier and the buffer amplifier. While the 60mV offset represents an error in current sharing, the gain of the current and 2X amplifiers reduces it to only 30mV. This pin needs a 1µF capacitor to compensate the amplifier. CA-: The inverting input to the current error amplifier. This amplifier needs a capacitor between CA- and CAO to set its dominant pole. 4 UC1849 UC2849 UC3849 PIN DESCRIPTIONS (cont.) CAO: The output of the current error amplifier which is internally clamped to 4V. It is internally connected to the inverting input of the PWM comparator. The dead time is approximately TDISCHARGE = 2 CT. (1) Frequency ≈ CS-, CS+: The inverting and non-inverting inputs to the current sense amplifier. This amplifier is not internally compensated so the user must compensate externally to attain the highest GBW for the application. 1 TCHARGE + TDISCHARGE (2) Maximum Duty Cycle ≈ TCHARGE TCHARGE + TDISCHARGE The CT capacitance should be increased by approximately 40pF to account for parasitic capacitance. CLKSYN: The clock and synchronization pin for the oscillator. This is a bidirectional pin that can be used to synchronize several chips to the fastest oscillator. Its input synchronization threshold is 1.4V. The CLKSYN voltage is 3.6V when the oscillator capacitor (CT) is being discharged, otherwise it is 0V. If the recommended synchronization circuit is not used, a 1k or lower value resistor from CLKSYN to GND may be needed to increase fall time on CLKSYN pin. OUT: The output of the PWM driver. It has an upper clamp of 8.5V. The peak current sink and source are 250mA. All UVLO, SEQ, ENBL, and KILL logic either enable or disable the output driver. RDEAD: The pin that programs the maximum duty cycle by connecting a resistor between it and OSC. The maximum duty cycle is decreased by increasing this resistor value which increases the discharge time. The dead time, the time when the output is low, is 2 RDEAD CT. The CT capacitance should be increased by approximately 40pF to account for parasitic capacitance. CSO: The output of the current sense amplifier which is internally clamped to 4V. · ENBL: The active low input with a 2.5V threshold enables the output to switch. SEQ and RUN are driven low when ENBL is above its 2.5V threshold. · RT: This pin programs the charge time of the oscillator ramp. The charge current is GND: The signal ground used for the voltage sense amplifier, current sense amplifier, current error amplifier, voltage reference, 2X amplifier, and share amplifier. The output sink transistor is wired directly to this pin. VREF 2 · RT The charge time is approximately TCHARGE ≈ RT when the RDEAD resistor is used. KILL: The active low input with a 3.0V threshold stops the output from switching. Once this function is activated RUN must be cycled low by driving KILL above 3.0V and either resetting the power to the chip (VCC) or resetting the ENBL signal. · CT The dead time is approximately T DISCHARGE ≈ 2 RDEAD CT. · · RUN: This is an open collector logic output that signifies when the chip is operational. RUN is pulled high to VREF through an external resistor when VCC is greater than 8.4V, VREF is greater than 4.65V, SEQ is greater than 2.5V, and KILL lower than 3.0V. RUN connected to the VA+ pin and to a capacitor to ground adds an RC rise time on the VA+ pin initiating a soft start. ILIM: A voltage on this pin programs the voltage error amplifier’s Voh clamp. The voltage error amplifier output represents the average output current. The Voh clamp consequently limits the output current. If ILIM is tied to VREF, it defaults to 3.0V. A voltage less than 3.0V connected to ILIM clamps the voltage error amplifier at this voltage and consequently limits the maximum output current. SEQ: The sequence pin allows the sequencing of startup for multiple units. A resistor between VREF and SEQ and a capacitor between SEQ and GND creates a unique RC rise time for each unit which sequences the output startup. OSC: The oscillator ramp pin which has a capacitor (CT) to ground and a resistor (RDEAD) to the RDEAD pin programs its maximum duty cycle by programming a minimum dead time. The ramp oscillates between 1.2V to 3.4V when an RDEAD resistor is used. The maximum duty cycle can be increased by connecting RDEAD to OSC which changes the oscillator ramp to vary between 0.2V and 3.5V. In order to guarantee zero duty cycle in this configuration VEE should not be connected to GND. The charge time is approximately TCHARGE = RT when the RDEAD resistor is used. · RDEAD · SHARE:The nearly DC voltage representing the average output current. This pin is wired directly to all SHARE pins and is the load share bus. VA+, VA-: The inverting and non-inverting inputs to the voltage error amplifier. · CT VAO: The output of the voltage error amplifier. Its Voh is clamped with the ILIM pin. 5 UC1849 UC2849 UC3849 PIN DESCRIPTIONS (cont.) VCC: The input voltage of the chip. The chip is operational between 8.4V and 20V. tual ground because of an internal diode between VEE and GND. The GND current flows through the forward biased diode and out VEE. GND is always the signal ground from which the voltage reference and all amplifier inputs are referenced. VEE: The negative supply to the chip which powers the lower voltage rail for all amplifiers. The chip is operational if VEE is connected to GND or if GND is floating. When voltage is applied externally to VEE, GND becomes a vir- VREF: The reference voltage equal to 5.0V. UDG-94111-1 Figure 1. Oscillator Block with External Connections CIRCUIT BLOCK DESCRIPTION: nized to the highest free running frequency by connecting 100pF capacitors in series with each CLKSYN pin and connecting the other side of the capacitors together forming the CLKSYN bus. The CLKSYN bus is then pulled down to ground with a resistance of approximately 10k. Referring to Figure1, the synchronization threshold is 1.4V. The oscillator blanks any synchronization pulse that occurs when OSC is below 2.5V. This allows units, once they discharge below 2.5V, to continue through the PWM Oscillator:The oscillator block diagram with external connections is shown in Figure 1. A resistor (RT) connected to pin RT sets the linear charge current; 2.5V RT . The timing capacitor (CT) is linearly charged with the charge current forcing the OSC pin to charge to a 3.4V threshold. After exceeding this threshold, the RS flip-flop is set driving CLKSYN high and RDEAD low which discharges CT. This discharge time with the RC time delay of 2 CT RDEAD is the minimum output low time. OSC continues to discharge until it reaches a 1.2V threshold and resets the RS flip-flop which repeats the charging sequence as shown in Figure 2. Equations to approximate frequency and maximum duty cycle are listed under the OSC pin description. Figure 3 and 4 graphs show measured variation of frequency and maximum duty cycle with varying RT, CT, and RDEAD component values. IRT ≈ · · UDG-94112 As shown in Figure 5, several oscillators are synchro- Figure 2. Oscillator and PWM Output Waveform 6 UC1849 UC2849 UC3849 CIRCUIT BLOCK DESCRIPTION (cont.) Ω Figure 3. Output Frequency UDG-94113 Figure 5. Oscillator Synchronization Connection Diagram Figure 4. Maximum Duty Cycle current discharge and subsequent charge cycles whether or not other units on the CLKSYN bus are still synchronizing. This requires the frequency of all free running oscillators to be within 40% of each other to guarantee synchronization. Grounds, Voltage Sensing and Current Sensing: The voltage is sensed directly at the load. Proper load sharing requires the same sensed voltage for each power supply connected in parallel. Referring to Figure 6, the positive sense voltage (VSP) connects to the voltage error amplifier inverting terminal (VA-), the return lead for the onchip reference is used as the negative sense (VSM). The current is sensed across the shunt resistor, RS. Figure 6 shows one recommended voltage and current sensing scheme when VEE is connected to GND. The signal ground is the negative sense point for the output voltage and the positive sense point for the output current. The voltage offset on the current sense amplifier is not needed if VEE is separated from GND. VEE is the negative supply for the current sense amplifier. When it is separated from GND, it extends the current sense amplifier’s common mode input voltage range to include VEE which is approximately −0.7V below ground. The resistor RADJ is used for load sharing. The unit which is the master will force VADJ to 1.0V. Therefore, the regulated voltage being sensed is actually UDG-94114 Figure 6.Voltage and Current Sense VEE Tied to GND VSP − VSM = (VREF − VADJ) RADJ · ( R1 + R ) + VADJ ADJ VSM = 0V, VADJ = 1V (master), VREF = 5V VSP = 4 7 RADJ · ( R1 + R ) ADJ + 1V UC1849 UC2849 UC3849 CIRCUIT BLOCK DESCRIPTION (cont.) The ADJ pin voltage on the slave chips will increase forcing their load currents to increase to match the master. voltage error amplifier output is the current command signal representing the average output load current. The ILIM pin programs the upper clamp voltage of this amplifier and consequently the maximum load current. A gain of 2 amplifier connected between the voltage error amplifier output and the share amplifier input increases the current share resolution and noise margin. The average current is used as an input to a source only load share buffer amplifier. The output of this amplifier is the current share bus. The IC with the highest sensed current will have the highest voltage on the current share bus and consequently act as the master. The 60mV input offset guarantees that the unit sensing the highest load current is chosen as the master. The AC frequency response of the voltage error amplifier is shown in Figure 7. The adjust amplifier is used by the remaining (slave) ICs to adjust their respective references high in order to balance each IC’s load current. The master’s ADJ pin will be at its 1.0V clamp and connected back to the non-inverting voltage error amplifier input through a high value resistor. This requires the user to initially calculate the control voltage with the ADJ pin at 1.0V. ∅m ≈ Figure 7. AC Frequency Response of the Voltage Error Amplifier VREF can be adjusted 150mV to 300mV which compensates for 5% unit to unit reference mismatch and external resistor mismatch. RADJ will typically be 10 to 30 times larger than R1. This also attenuates the overall variation of the ADJ clamp of 1V ±100mV by a factor of 10 to 30, contributing only a 3mV to 10mV additional delta to VREF. Refer to the UC3907 Application Note U-130 for further information on parallel power supply load sharing. Startup and Shutdown: Isolated power up can be accomplished using the UCC1889. Application Note U149 is available for additional information. The UC1849 offers several features that enhance startup and shutdown. Soft start is accomplished by connecting RUN to VA+ and a capacitor to ground. The resulting RC rise time on the VA+ pin initiates a soft start. It can also be accomplished by connecting RUN to ILIM. When RUN is low it will command zero load current, guaranteeing a soft start. The undervoltage lockout (UVLO) is a logical AND of ENBL < 2.5V, SEQ > 2.5V, VCC > 8.4V and VREF > 4.65V. The block diagram shows that the thresholds are set by comparators. By placing an RC divider on the SEQ pin, the enabling of multiple chips can be sequenced with different RC time constants. Similarly, different RC time constants on the ENBL pins can sequence shutdown. The UVLO keeps the output from switching; however the internal reference starts up with VCC less than 8.4V. The KILL input shuts down the switching of the chip. This can be used in conjunction with an overvoltage comparator for overvoltage protection. In order to restart the chip after KILL has been initiated, the chip must be powered down and then back up. A pulse on the ENBL pin also accomplishes this without actually removing voltage to the VCC pin. Current Control Loop: The current sense amplifier (CSA) is designed specifically for the task of sensing and amplifying the inductor ripple current at frequencies up to 1MHz. The CSA’s input offset voltage (VIO) is trimmed to less than 1mV to minimize error of the average current signal. This amplifier is not internally compensated allowing the user to optimally choose the zero crossing bandwidth. (3) Frequency (0dB) = 1 · 2π RINV CCOMP RINV is the input resistance at the inverting terminal CSCCOMP is the capacitance between CS- and CSO. Although it is only unity gain stable for a GBW of 7MHz, the amplifier is typically configured with a differential gain of at least 10, allowing the amplifier to operate at 70MHz with sufficient phase margin. A closed loop gain of 10 attenuates the output by 20.8dB. 20.8 = 20log Load Sharing: Load sharing is accomplished similar to the UC1907. The sensed current for the UC1849 has an AC component that is amplified and then averaged. The · 111 to the inverting terminal assuring stability. The amplifier’s gain fed back into the inverting terminal is less than unity 8 UC1849 UC2849 UC3849 CIRCUIT BLOCK DESCRIPTION (cont.) at 7MHz, where the phase margin begins to roll off. See Figure 8 for typical Bode plot. CSGAIN = VILIM VRS. The current error amplifier (CEA) also needs its loop compensated by the user with the same criteria as the current sense amplifier. This amplifier is essentially the same wide bandwidth amplifier without the input offset voltage trim. The zero crossing can also be approximately calculated with Equation 3. The gain bandwidth of the current loop is optimized by matching the inductor downslope (Vo/L) to the oscillator ramp slope (Vs fs). Subharmonic oscillation problems are avoided by keeping the amplified inductor downslope less than the oscillator ramp slope. (5) · − β ∅m The following equation determines the current error amplifier gain (GCA): (6) GCA = Figure 8. Current Sense Amplifier and Current Error Amplifier Bode Plot where CSGAIN and RS are defined by equations 4 and 5, Vs is the oscillator peak to peak voltage, fs is the oscillator frequency, Vo is the output voltage, and L is the inductance. The gain of the differential current sense amplifier (CSGAIN) is calculated by knowing the maximum load current. The maximum voltage across the shunt resistor (R S ) divided by R S is the maximum load current. By amplifying the voltage across RS, VRS, to be equal to the voltage error amplifier Voh, the current control loop keeps the load from exceeding its current limit. Voh is set at 3.0V if ILIM is connected to VREF. The maximum current limit clamp can be reduced by reducing the voltage at ILIM to less than 3.0V as described in the ILIM pin description. (4) RS = · fs ; (Vo/L) · RS · CSGAIN Vs Additional Information about average current mode control can be found in Unitrode Application Note U-140. Design Example: Figure 9 is an open loop test that lets the user test the circuit blocks discussed without having to build an entire control loop. The pulse width can be varied by either the VADJ or the VISENSE inputs. Figure 10 shows an isolated power supply using the UC1849 secondary side average current mode controller. VRS Max ILOAD UDG-94115-1 Figure 9. Open Loop Circuit 9 UC1849 UC2849 UC3849 UDG-94116-1 Figure 10. UC1849 Application Diagram UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. 603-424-2410 • FAX 603-424-3460 10 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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