SLUS329B − JUNE 1998 − REVISED FEBRUARY 2005
FEATURES
D Controls Boost PWM to Near-Unity Power
D
D
D
D
D
D
D
D
D
D
D
DESCRIPTION
The UC3854A/B products are pin compatible
enhanced versions of the UC3854. Like the
UC3854, these products provide all of the
functions necessary for active power factor
corrected preregulators. The controller achieves
near unity power factor by shaping the AC input
line current waveform to correspond to the AC
input line voltage. To do this the UC3854A/B uses
average current mode control. Average current
mode control maintains stable, low distortion
sinusoidal line current without the need for slope
compensation, unlike peak current mode control.
Factor
Limits Line Current Distortion To < 3%
World-Wide Operation Without Switches
Accurate Power Limiting
Fixed-Frequency Average Current-Mode
Control
High Bandwidth (5 MHz), Low-Offset Current
Amplifier
Integrated Current- and Voltage Amplifier
Output Clamps
Multiplier Improvements: Linearity, 500 mV
VAC Offset (Eliminates External Resistor), 0 V
to 5 V Multout Common-Mode Range
VREF GOOD Comparator
Faster and Improved Accuracy ENABLE
Comparator
UVLO Options (16 V/10 V or 10.5 V/10 V)
300-µA Start-Up Supply Current
A 1% 7.5 V reference, fixed frequency oscillator,
PWM, voltage amplifier with soft-start, line voltage
feedforward (VRMS squarer), input supply voltage
clamp, and over current comparator round out the
list of features.
Available in the 16-pin N (PDIP), DW (SOICWide), and J (CDIP) and 20-pin Q (PLCC)
package. See ordering information on page 3 for
availability by temperature range.
BLOCK DIAGRAM
VAO
MOUT
7
5
CAO PKLMT
3
REF
2
9
VCC
7.5 V REF
(A) 16 V / 10 V
(B) 10.5 V / 10 V
RUN
ENA 10
3V
IAC 6
VRMS
15 VCC
A
VSENSE 11
R
R
S Q
B
X2
8
7.1 V
IC
POWER
2.65 V / 2.15 V
14 µA
SS 13
16 GTDRV
C
RUN
I MOUT
+A
B
OSC
C
4
ISENSE
14
12
CT
RSET
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
20 V
1 GND
UDG−03110
Copyright 2003, Texas Instruments Incorporated
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1
SLUS329B − JUNE 1998 − REVISED FEBRUARY 2005
DESCRIPTION (continued)
The UC3854A/B products improve upon the UC3854 by offering a wide bandwidth, low offset current amplifier,
a faster responding and improved accuracy enable comparator, a VREF GOOD comparator, UVLO threshold
options (16 V/10 V for offline, 10.5 V/10 V for startup from an auxiliary 12 V regulator), lower startup supply
current, and an enhanced multiply/divide circuit. New features like the amplifier output clamps, improved
amplifier current sinking capability, and low offset VAC pin reduce the external component count while improving
performance. Improved common mode input range of the multiplier output/current amplifier input allow the
designer greater flexibility in choosing a method for current sensing. Unlike its predecessor, RSET controls only
oscillator charging current and has no effect on clamping the maximum multiplier output current. This current
is now clamped to a maximum of 2 × IAC at all times which simplifies the design process and provides foldback
power limiting during brownout and extreme low line conditions.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
Supply voltage, VCC
UCX854A, UCX854B
UNIT
22
V
GTDRV current, IGTDRV
Continuous
0.5
A
GTDRV Current, IGTDRV
50% duty cycle
1.5
A
VSENSE, VRMS, ISENSE MOUT
11
V
PKLMT
5
V
RSET, IAC, PKLMT, ENA
10
mA
1
W
Input voltage
Input current
Power dissipation
Junction temperature, TJ
−55 to 150
Storage temperature, Tstg
−65 to 150
°C
C
Lead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds
300
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to
GND. Currents are positive into and negative out of, the specified terminal. ENA input is internally clamped to approximately 10 V.
RECOMMENDED OPERATING CONDITIONS
MAX
UNIT
10
MIN
20
V
UC1854X
−55
125
UC2854X
−40
85
UC3854X
0
70
Supply voltage, VCC
Operating junction temperature, TJ
2
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°C
C
SLUS329B − JUNE 1998 − REVISED FEBRUARY 2005
PACKAGE DESCRIPTION
Q PACKAGE
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
GTDRV
VCC
CT
SS
RSET
VSENSE
ENA
VREF
3
ISENSE
CAOUT
N/C
MOUT
IAC
5
2 1 20 19
18
4
17
6
16
7
15
8
14
9 10 11 12 13
CT
SS
N/C
RSET
VSENSE
VAO
VRMS
NC
VREF
ENA
GND
PKLMT
CAO
ISENSE
MOUT
IAC
VAO
VRMS
PKLMT
GND
N/C
GTDRV
VCC
J, N and DW PACKAGES
(TOP VIEW)
N/C − No connection
ORDERING INFORMATION
TA
UVLO
TURN-ON
(V)
UVLO
TURN-OFF
(V)
−55°C to 125°C
−40°C to 85°C
0°C to 70°C
PART NUMBERS
CDIP−16
(J)
PDIP−16
(N)
SOIC−16
(DW)
PLCC−20
(Q)
−
16
10
−
−
−
10.5
10
UC1854BJ
−
−
−
16
10
UC2854AJ
UC2854AN
UC2854ADW
UC2854AQ
10.5
10
UC2854BJ
UC2854BN
UC2854BDW
UC2854BQ
16
10
−
UC3854AN
UC3854ADW
−
10.5
10
−
UC3854BN
UC3854BDW
−
(1) The DW and Q packages are available taped and reeled. Add TR suffix to device type (e.g. UC2854ADWTR) to order quantities of 2,000
devices per reel for the DW package and 1,000 devices per reel for the Q package.
THERMAL RESISTANCE
PACKAGED DEVICES
RESISTANCES
θJC (°C/W)
θJA (°C/W)
CDIP−16
(J)
28(2)
80−120
PDIP−16
(N)
SOP−16
(DW)
PLCC−20
(Q)
45
90(3)
27
50−130(3)
34
43−75(3)
(2) θJC data values stated are derived from MIL-STD-1835B which states “the baseline values shown are worst case (mean +2s) for a 60 × 60
mil microcircuit device silicon die and applicable for devices with die sizes up to 14,400 square mils. For device die sizes greater than
14,400 square mils use the following values, dual-in-line, 11°C/W; flat pack and pin grid array, 10°C/W.
(3) θJA (junction-to-ambient) applies to devices mounted to five square inch FR4 PC board with one ounce copper where noted. When
resitance range is given, lower values are for five square inch aluminum PC board. Test PWB is 0.062 inches thick and typically uses
0.635 mm trace widths for power packages and 1.3 mm trace widths for non-power packages with a 100 × 100 mil probe land are at the
end of each trace.
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3
SLUS329B − JUNE 1998 − REVISED FEBRUARY 2005
ELECTRICAL CHARACTERISTICS
VCC = 18 V, RT = 8.2 kΩ, CT = 1.5 nF, VPKLMT = 1 V, VVRMS = 1.5 V, IIAC = 100 µA, IISENSE = 0 V, VCAO = 3.5 V, VVAO = 5 V, VVSENSE = 3 V,
−40°C < TA < 85°C for the UC2854A and UC2854B, and 0°C < TA <70°C for the UC3854A and UC3854B, and TA = TJ (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
250
400
µA
mA
OVERALL
CAO = 0 V,
VAO = 0 V,
VCC = VUVLO−0.3 V
Supply current, off
Supply current, on
VCC turn-on threshold voltage
VCC turn-off threshold voltage
VCC clamp
12
18
UCx854A
15.0
16.0
17.5
UCx854B
8.0
10.5
11.2
9
10
12
18
20
22
IVCC = IVCC(on) + 5 mA
V
VOLTAGE AMPLIFIER
Input voltage
VSENSE bias current
Open loop gain
2 V ≤ VOUT ≤ 5 V
VOH
VOL
High-level output voltage
Low-level output voltage
ILOAD = −500 µA
ILOAD = 500 µA
ISC
Output short-circuit current
Gain bandwidth product(1)
VOUT = 0 V
fIN = 100 kHz,
2.9
3.0
3.1
V
−500
−25
500
nA
70
100
dB
6
V
10 mVP−P
0.3
0.5
V
1.5
3.5
mA
1
MHz
CURRENT AMPLIFIER
Input bias current, ISENSE
VCM = 0 V,
VCM = 0 V,
VCM = 0 V
Open loop gain
2 V ≤ VOUT ≤ 6 V
VOH
VOL
High-level output voltage
Low-level output voltage
ILOAD = −500 µA
ILOAD = 500 µA
0.3
0.5
ISC
CMRR
Output short-circuit current
VOUT = 0 V
1.5
3.5
Common mode rejection range
Gain bandwidth product(1)
fIN = 100 kHz,
Input offset voltage
TA = 25°C
overtemperature
−4
0
−5.5
0
−500
80
500
110
mV
nA
dB
8
−0.3
5.0
10 mVP−P
3
5
7.4
7.5
7.6
7.35
7.50
7.65
Load regulation
IREF = 0 mA,
TA = 25°C
IREF = 0 mA
1 mA ≤ IREF ≤ 10 mA
0
8
20
Line regulation
12 V ≤ VCC ≤ 18 V
0
14
25
25
35
60
V
mA
V
MHz
REFERENCE
Output voltage
ISC
Short circuit current
(1) Ensured by design. Not production tested.
(2) Gain constant. (K) +
4
I IAC
ƪ ǒV
VREF = 0 V
ǒVVAO * 1.5 VNj
VRMS
Ǔ
2
I MOUT
ƫ
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V
mV
mA
SLUS329B − JUNE 1998 − REVISED FEBRUARY 2005
ELECTRICAL CHARACTERISTICS
VCC = 18 V, RT = 8.2 kΩ, CT = 1.5 nF, VPKLMT = 1 V, VVRMS = 1.5 V, IIAC = 100 µA, IISENSE = 0 V, VCAO = 3.5 V, VVAO = 5 V, VVSENSE = 3 V,
−40°C < TA < 85°C for the UC2854A and UC2854B, and 0°C < TA <70°C for the UC3854A and UC3854B, and TA = TJ (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
85
100
115
kHz
kHz
OSCILLATOR
Initial accuracy
Voltage stability
TA = 25°C
12 V ≤ VCC ≤ 18 V
Total variation
Line, temperature
1%
80
120
Ramp amplitude (peak-to-peak)
4.9
5.9
Ramp valley voltage
0.8
1.3
V
ENABLE/SOFT-START/CURRENT LIMIT
Enable threshold voltage
2.55
2.80
V
500
600
mV
Enable input bias current
VFAULT = 2.5 V
VENA = 0 V
2.35
−2
−5
µA
Propagation delay to disable time(1)
Enable overdrive = 100 mV
300
Soft-start charge current
VSS = 2.5 V
Enable hysteresis
10
Peak limit offset voltage
14
−15
Peak limit input current
VPKLMT = −0.1 V
−200
Peak limit propagation delay time(1)
ns
24
15
mV
−100
µA
150
ns
MULTIPLIER
Output current, IAC limited
Output current, zero
Output current, power limited
Output current
Gain constant(2)
IAC = 100 µA,
RSET = 10 kΩ
VRMS = 1 V,
−220
−200
−170
IAC = 0 µA,
VRMS = 1.5 V,
RSET = 10 kΩ
−2.0
−0.2
2.0
Va = 6 V
−230
−200
−170
VRMS = 1.5 V,
VRMS = 1.5 V,
Va = 2 V
−22
Va = 5 V
−156
VRMS = 5 V,
VRMS = 5 V,
Va = 2 V
−2
Va = 5 V
−14
VRMS = 1.5 V,
Va = 6V,
TA = 25°C
−1.1
−1.0
12.0
12.8
A
µA
µA
µA
−0.9
A/A
GATE DRIVER
VOH
VOL
High-level output voltage
IOUT = −200 mA,
IOUT = 200 mA
Low-level output voltage
IOUT = 10 mA
IOUT = 50 mA,
Low-level UVLO voltage
Output rise time(1)
VCC = 15 V
VCC = 0 V
V
1.0
2.2
300
500
mV
0.9
1.5
V
CLOAD = 1 nF
35
Output fall time(1)
CLOAD = 1 nF
35
Output peak current(1)
CLOAD = 10 nF
1.0
ns
A
(1) Ensured by design. Not production tested.
(2) Gain constant. (K) +
I IAC
ƪ ǒV
ǒVVAO * 1.5 VNj
VRMS
Ǔ
2
I MOUT
ƫ
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5
SLUS329B − JUNE 1998 − REVISED FEBRUARY 2005
TERMINAL FUNCTIONS
TERMINAL
PACKAGES
I/O
DESCRIPTION
4
O
Output of the wide bandwidth current amplifier and one of the inputs to the PWM duty-cycle
comparator. The output signal generated by this amplifier commands the PWM to force the correct
input current. The output can swing from 0.1 V to 7.5 V.
14
18
I
Capacitor from CT to GND sets the PWM oscillator frequency
ENA
10
13
I
A nominal voltage above 2.65 V on this pin allows the device to begin operating. Once operating,
the device shuts off if this pin goes below 2.15 V nominal.
GND
1
2
−
All bypass and timing capacitors connected to GND should have leads as short and direct as
possible. All voltages are measured with respect GND.
O
Output of the PWM is a 1.5-A peak totem-pole MOSFET gate driver on GTDRV. This output is
internally clamped to 15 V so that the device can be operated with VCC as high as 35 V. Use a
series gate resistor of at least 5 Ω to prevent interaction between the gate impedance and the
GTDRV output driver that might cause the GTDRV output to overshoot excessively. Some
overshoot of the GTDRV output is always expected when driving a capacitive load.
NAME
J/N/DW
Q/L
CAO
3
CT
GTDRV
20
IAC
6
8
I
Current input to the multiplier, proportional to the instantaneous line voltage. This input to the
analog multiplier is a current. The multiplier is tailored for very low distortion from this current input
(IAC) to MOUT, so this is the only multiplier input that should be used for sensing instantaneous
line voltage. The nominal voltage on IAC is 6 V, so in addition to a resistor from IAC to rectified
60 Hz, connect a resistor from IAC to VREF. If the resistor to VREF is one-fourth of the value of the
resistor to the rectifier, then the 6-V offset is cancelled, and the line current has minimal cross-over
distortion.
ISENSE
4
5
I
Switch current sensing input. This is the inverting input to the current amplifier. This input and the
non-inverting input MOUT remain functional down to and below GND. Care should be taken to
avoid taking these inputs below −0.5V, because they are protected with diodes to GND.
MOUT
5
7
I/O
Multiplier output and current sense plus. The output of the analog multiplier and the non-inverting
input of the current amplifier are connected together at MOUT. The cautions about taking ISENSE
below −0.5V also apply to MOUT. As the multiplier output is a current, this is a high-impedance
input similar to ISENSE, so the current amplifier can be configured as a differential amplifier to reject
GND noise.
PKLMT
2
3
I
Peak limit. The threshold for PKLMT is 0.0 V. Connect this input to the negative voltage on the
current sense resistor. Use a resistor to REF to offset the negative current sense signal up to GND.
RSET
12
15
I
Oscillator charging current and multiplier limit set. A resistor from RSET to ground programs
oscillator charging current. Multiplier output current does not exceed 3.75V divided by the resistor
from RSET to ground.
17
I
Soft-start. SS remains at GND as long as the device is disabled or VCC is too low. SS pulls up to
over 8 V by an internal 14-mA current source when both VCC becomes valid and the device is
enabled. SS acts as the reference input to the voltage amplifier if SS is below VREF. With a large
capacitor from SS to GND, the reference to the voltage regulating amplifier rises slowly, and
increase the PWM duty cycle slowly. In the event of a disable command or a supply dropout, SS
will quickly discharge to ground and disable the PWM.
SS
6
16
13
VAO
7
9
I
Voltage amplifier output
VCC
15
19
I
Positive supply rail
VREF
9
12
O
Used to set the peak limit point and as an internal reference for various device functions. This
voltage must be present for the device to operate.
VRMS
8
10
I
One of the inputs into the multiplier. This pin provides the input RMS voltage to the multiplier
circuitry.
VSENSE
11
14
I
This pin provides the feedback from the output. This input goes into the voltage error amplifier and
the output of the error amplifier is another of the inputs into the multiplier circuit.
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SLUS329B − JUNE 1998 − REVISED FEBRUARY 2005
FUNCTIONAL DESCRIPTION
The UC3854A and UC3854B family of products are designed as pin compatible upgrades to the industry
standard UC3854 active power factor correction circuits. The circuit enhancements allow the user to eliminate
in most cases several external components currently required to successfully apply the UC3854. In addition,
linearity improvements to the multiply, square and divide circuitry optimizes overall system performance.
Detailed descriptions of the circuit enhancements are provided below. For in-depth design applications
reference data refer to the application notes, UC3854 Controlled Power Factor Correction Circuit Design
(SLUA144) and UC3854A and UC3854B Advanced Power Factor Correction Control ICs (SLUA177).
Multiply/Square and Divide
The UC3854A/B multiplier design maintains the same gain constant
ǒK + *V1Ǔ as the UC3854. The
relationship between the inputs and output current is given as:
I MOUT + I iAC
ǒVVAO * 1.5 VǓ
K
ǒVVRMSǓ
2
(1)
This is nearly the same as the UC3854, but circuit differences have improved the performance and application.
The first difference is with the IAC input. The UC3854A/B regulated this pin voltage to the nominal 500 mV over
the full operating temperature range, rather than the 6.0 V used on the UC3854. The low offset voltage
eliminates the need for a line zero crossing compensating resistor to VREF from IAC that UC3854 designs
require. The maximum current at high line into IAC should be limited to 250 µA for best performance.
Therefore, if VVAC(max) = 270 V,
R IAC + 270 1.414 + 1.53 MW
250 mA
(2)
The VRMS pin linear operating range is improved with the UC3854A/B as well. The input range for VRMS
extends from 0 V to 5.5 V. Since the UC3854A squaring circuit employs an analog multiplier, rather than a linear
approximation, accuracy is improved, and discontinuities are eliminated. The external divider network
connected to VRMS should produce 1.5 V at low line (85 VAC). This puts 4.77 V on VRMS at high line (27 VAC)
which is well within its operating range.
The voltage amplifier output forms the third input to the multiplier and is internally clamped to 6.0 V. This
eliminated an external zener clamp often used in UC3854 designs. The offset voltage at this input to the
multiplier has been raised on the UC3854A/B to 1.5 V.
The multiplier output pin, which is also common to the current amplifier non-inverting input, has a −0.3 V to 5.0 V
output range, compared to the −0.3 V to 2.5 V range of the UC3854. This improvement allows the UC3854A/B
to be used in applications where the current sense signal amplitude is very large.
Voltage Amplifier
The UC3854A/B voltage amplifier design is essentially similar to the UC3854 with two exceptions. The first is
with the internal connection. The lower voltage reduces the amount of charge on the compensation capacitors,
which provides improved recovery form large signal events, such as line dropouts, or power interruption. It also
minimizes the dc current flowing through the feedback. The output of the voltage amplifier is also changes. In
addition to a 6.0 V temperature compensated clamp, the output short circuit current has been lowered to 2 mA
typical, and an active pull down has replaced the passive pull down of the UC3854.
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7
SLUS329B − JUNE 1998 − REVISED FEBRUARY 2005
Current Amplifier
The current amplifier for an average current PFC controller needs a low offset voltage in order to minimize AC
line current distortion. With this in mind, the UC3854A/B current amplifier has improved the input offset voltage
from ±4 mV to 0 V to ±3 mV. The negative offset of the UC3854A/B guarantees that the PWM circuit will not drive
the MOSFET is the current command is zero (both current amplifier inputs zero.) Previous designs required an
external offset cancellation network to implement this key feature. The bandwidth of the current amplifier has
been improved as well to 5 MHz typical. While this is not generally an issue at 50 Hz or 60 Hz inputs, it is
essential for 400 Hz input avionics applications
Miscellaneous
Several other important enhancements have been implemented in the UC3854A/B. A VCC supply voltage clamp
at 20 V allows the controller to be current fed if desired. The lower startup supply current (250 mA typical),
substantially reduces the power requirements of an offline startup resistor. The 10.5 V/10 V UVLO option
(UC3854B) enables the controller to be powered off of an auxiliary 12 V supply.
The VREF GOOD comparator guarantees that the MOSFET driver output remains low if the supply of the 7.5 V
reference are not yet up. This improvement eliminates the need for external Schottky diodes on the PKLMT and
Mult Out pins that some UC3854 designs require. The propagation delay of the disable feature has been
improved to 300 ns typical. This delay was proportional to the size of the VREF capacitor on the UC3854, and
is typically several orders of magnitude slower.
8
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SLUS329B − JUNE 1998 − REVISED FEBRUARY 2005
TYPICAL CHARACTERISTICS
GATE DRIVE TIMING
vs
LOAD CAPACITANCE
800
GATE DRIVE MAXIMUM DUTY CYCLE
vs
OSCILLATOR CHARGING RESISTANCE
100
700
95
Fall Time
Duty Cycle − %
t− Time − ns
600
500
400
Rise Time
300
90
85
80
200
75
100
0
0
0.01
0.02
0.03
0.04
70
1000
0.05
CLOAD − Load Capacitance − µF
10 k
100 k
RSET − Oscillator Charging Resistance − Ω
Figure 1
Figure 2
MULTIPLIER GAIN CONSTANT
vs
SUPPLY CURRENT
1.20
MULTIPLIER GAIN CONSTANT
vs
SUPPLY CURRENT
1.20
VA Out = 3.5 V
VA Out = 5 V
1.16
1.12
1.12
VRMS = 1.5 V
K− Multiplier Gain Constant− V
K− Multiplier Gain Constant− V
1.16
1.08
VRMS = 5 V
1.04
1.00
0.96
0.92
VRMS = 3 V
0.88
VRMS = 1.5 V
1.08
1.04
1.00
0.96
VRMS = 5 V
0.92
VRMS = 1.5 V
0.88
0.84
0.84
0.80
0.80
0
50
100
150
IAC − Supply Current − µA
200
250
Figure 3
0
50
100
150
IAC − Supply Current − µA
200
250
Figure 4
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9
SLUS329B − JUNE 1998 − REVISED FEBRUARY 2005
140
120
PHASE
100
−90
80
−45
60
−0
Phase − °
100
Gain − dB
Gain − dB
120
40
20
0
VOLTAGE AMPLIFIER GAIN
vs
FREQUENCY
PHASE
120
100
80
80
60
60
40
40
20
20
0
0
−20
GAIN
fCO = 5.992 MHz
−40
−60
10 k
100 k
1M
−20
100
10 M
OSCILLATOR FREQUENCY
vs
LIMIT SET RESISTANCE AND
TIMING CAPACITANCE
1k
fOSC − Oscillator Frequency − kHz
200 pF
100 pF
1 nF
100
500 pF
3 nF
10 nF
2 nF
0
1
10
100
RSET − Multiplier Limit Set Resistance − kΩ
Figure 7
10
GAIN
100
k
Figure 6
Figure 5
5 nF
10 k
f − Frequency − Hz
f − Frequency − Hz
10
1000
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1M
−20
10 M
Phase − °
CURRENT AMPLIFIER GAIN
vs
FREQUENCY
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
8
14
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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