TMC57253 DRIVER SOCS040A – MARCH 1994 – REVISED NOVEMBER 1994 • • • • • • HSOP TYPE-B (TOP VIEW) TTL-Compatible Inputs CCD-Compatible Outputs Adjustable Clock Levels High-Speed Clear Serial-Gate Midlevel for CDS Operation Solid-State Reliability VAB VCC GND EN ABIN ABMIN IA1IN IA2IN SAIN SRIN SRMIN GND description The TMC57253 is a monolithic CMOS integrated circuit designed to drive image-area gates (IAG1, IAG2), antiblooming gate (ABG), storage-area gate (SAG), and serial-register gate (SRG) of the Texas Instruments (TI) TC255 CCD image sensor. The TMC57253 interfaces the CCD image sensor to the TI TMC57751 ASIC or user-defined timing generator; it receives TTL-input signals from the timing generator and outputs levelshifted signals to the image sensor. ABOUT follows ABIN and ABMIN and switches between VABL, VAB, and VABM. IA1OUT and IA2OUT follow IA1IN and IA2IN, respectively, and switch between GND and VIA. The SAOUT output follows the SAIN and switches GND and VS. SROUT follows SRIN and SRMIN and switches between GND, VSM, and VS. The TMC57253 is available in a 24-pin HSOP-B surface-mount package and is characterized for operation from – 20°C to 45°C. 1 2 3 24 23 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VABM ABOUT VABL GND IA1OUT VIA IA2OUT GND SAOUT VS SROUT VSM logic symbol Φ TTL/CCD EN ABIN ABMIN VABM SRIN SRMIN VSM IA1IN IA2IN SAIN 4 5 6 23 ABOUT 24 10 11 14 SROUT 13 7 20 8 18 9 16 IA1OUT IA2OUT SAOUT This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. TI is a trademark of Texas Instruments Incorporated. Copyright 1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TMC57253 DRIVER SOCS040A – MARCH 1994 – REVISED NOVEMBER 1994 Terminal Functions TERMINAL NAME ABIN 5 DESCRIPTION I Antiblooming input ABMIN 6 I Antiblooming midlevel input ABOUT 23 O Antiblooming output EN 4 I Enable control input GND 2 I/O NO. 3, 12, 17, 21 Ground IA1IN 7 I Image area 1 input IA1OUT 20 O Image area 1 output IA2IN 8 I Image area 2 input IA2OUT 18 O Image area 2 output SAIN 9 I Storage area input SAOUT 16 O Storage area output SRIN 10 I Serial register input SRMIN 11 I Serial register mid input SROUT 14 O Serial register output VAB VABL 1 High-level antiblooming supply voltage 22 Low-level antiblooming supply voltage VABM VCC 24 Midlevel antiblooming supply voltage 2 Supply voltage VIA VS 19 Image supply voltage 15 Serial and storage-gate supply voltage VSM 13 Midlevel serial-gate supply voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMC57253 DRIVER SOCS040A – MARCH 1994 – REVISED NOVEMBER 1994 functional block diagram VAB VCC 1 24 Level Shift 2 Level Shift 23 HV_BUF and Driver 20 IA1IN IA1OUT 5 19 ABMIN VABL 4 Level Shift ABIN ABOUT HV_BUF and Driver 22 EN VABM VIA 6 Level Shift HV_BUF and Driver Level Shift HV_BUF and Driver 7 18 IA2OUT Logic IA2IN SAIN 8 9 16 15 SRIN 10 Level Shift SRMIN 11 Level Shift 14 • DALLAS, TEXAS 75265 VS SROUT HV_BUF and Driver 13 POST OFFICE BOX 655303 SAOUT VSM 3 TMC57253 DRIVER SOCS040A – MARCH 1994 – REVISED NOVEMBER 1994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 20 V Continuous total power dissipation at (or below) TA = 25°C: Unmounted device (see Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1990 mW Mounted device (see Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2754 mW Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20°C to 45°C Storage temperature range, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C Lead temperature: 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C 1,6 mm (1/16 inch) from case for 3 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to GND. POWER DISSIPATION vs FREE-AIR TEMPERATURE 3000 PD – Power Dissipation – mW 2800 Mounted Device (see Note A) 2600 2400 2200 2000 1800 1600 Unmounted Device 1400 1200 1000 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 TA – Free-Air Temperature – °C NOTE A: The mounted-device derating curve of Figure 1 is obtained under the following conditions: The board is 50 mm by 50 mm by 1.6 mm thick. The board material is glass epoxy. The copper thickness of all the etch runs is 35 microns. Etch-run dimensions – All twenty etch runs are 0.4 mm by 22 mm. Each chip is soldered to the board. An aluminum cooling fin 10 mm by 10 mm by 1 mm thick is coupled to the chip with thermal paste. Figure 1 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMC57253 DRIVER SOCS040A – MARCH 1994 – REVISED NOVEMBER 1994 recommended operating conditions Supply voltage, VCC MIN NOM MAX 4.5 5 5.5 UNIT V 18 V Antiblooming supply voltage, VAB 8 Low-level antiblooming supply voltage, VABL 0 3 V Midlevel antiblooming supply voltage, VABM 3 10 V Image-gate supply voltage, VIA 8 14 V Serial and storage-gate supply voltage, VS 8 14 V Serial-gate midlevel supply voltage, VSM 3 7 V High-level input voltage, VIH 2.5 V Low-level input voltage, VIL 0.9 V 25 MHz IA1OUT, IA2OUT (transfer) 12.5 MHz SAOUT (transfer) 12.5 MHz ABOUT 12.5 MHz SROUT 12.5 MHz IA1OUT, IA2OUT (fast clear) Frequency, fclock IA1OUT, IA2OUT, SAOUT Drive mode (on ratio) 1% ABOUT 23% SROUT 85% Operating free-air temperature, TA – 20 45 °C electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH VOL High-level output voltage IIH IIL High-level input current ICC IIA Supply current IAB IABL Antiblooming supply current IABM ISM Midlevel antiblooming supply current IS Serial-gate supply current TEST CONDITIONS IOH = 0.5 mA IOL = 0 Low-level output voltage Low-level input current Midlevel serial-gate supply current ABOUT SROUT ± 10 IO = 10 mA, VI = VCC, GND VIA = 8 V IO = 10 mA, VSM = 4 V, VI = VCC, GND IO = 10 mA, VSM = 4 V, VAB = 8 V, VABM = 4 V VABL = 0 V VS= 8 V, VI = VCC, GND POST OFFICE BOX 655303 V ± 10 VS = 12 V • DALLAS, TEXAS 75265 UNIT V 0 VAB = 12 V Low-level antiblooming supply current MAX 12 VCC = 5 V VIA = 12 V Image-gate supply current Output resistance TYP VIH = 5 V VIL = 0 IA1OUT, IA2OUT, SAOUT ro MIN µA µA 0.1 mA 5 mA 15 mA 15 mA 0.5 mA 2 mA 2 mA 5 10 Ω 50 5 TMC57253 DRIVER SOCS040A – MARCH 1994 – REVISED NOVEMBER 1994 switching characteristics for ABOUT, IA1OUT, IA2OUT, SAOUT, and SROUT, VAB = 13 V, VABI = 1.5 V,VABM = 6.5 V, VIA = 11 V, VSM = 5 V, VS = 11 V, TA = 25°C (unless otherwise noted)† PARAMETER tpd Propagation delay time FROM (INPUT) TO (OUTPUT) IA1IN IA1OUT IA2IN IA2OUT SAIN SAOUT SRIN SRMIN ABIN ABMIN TEST CONDITIONS MIN See Figure 3 MAX UNIT 85 40 80 ns SROUT See Figure 4 ABOUT See Figure 5 90 See Figure 6 1 ns See Figure 6 1 ns IA1OUT IA2OUT tPLZ Disable time EN SAOUT SROUT ABOUT IA1OUT IA2OUT tPZH Enable time EN SAOUT SROUT ABOUT IA1OUT Duty cycle‡ IA2OUT ABOUT † The load is a Texas Instruments TC255 CCD image sensor. ‡ twH Duty cycle 100 (t w H t w L) + 6 See Figure 3, tc = 80 ns 40% 60% See Figure 3, tc = 160 ns 40% 60% SAOUT ) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMC57253 DRIVER SOCS040A – MARCH 1994 – REVISED NOVEMBER 1994 PARAMETER MEASUREMENT INFORMATION VIH 90% 10% VIL tf tr 5 ns MAX 5 ns MAX Figure 2. Rise and Fall Time Requirements for Input Signals VCC 50% IA1IN, IA2IN, SAIN GND tPLH tPHL VIA or VS IA1OUT, IA2OUT, SAOUT 50% GND twL twH NOTE A: tpd = tPLH or tPHL Figure 3. Duty Cycle and Propagation Delay 26 ns MIN SRIN 54 ns MIN VCC 50% GND 5 ns MAX† SRMIN VS 50% GND tPHL tPLH SROUT 26 ns MIN† tPHL VS VSM 50% VS 50% VSM GND † If SRIN and SRMIN are both high, SROUT follows SRIN. NOTE A: tpd = tPLH or tPHL Figure 4. Serial-Register-Driver Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TMC57253 DRIVER SOCS040A – MARCH 1994 – REVISED NOVEMBER 1994 PARAMETER MEASUREMENT INFORMATION 166 ns MIN 80 ns MIN 80 ns MIN VCC ABIN 50% GND tPHL VCC 50% GND ABMIN tPLH tPLH tPHL VAB VABM 50% VABM VABL NOTES: A. VAB and VABM are in a short-circuit condition if ABIN and ABMIN are held high at the same time. This short-circuit condition can destroy the device. B. tpd = tPLH or tPHL ABOUT 50% 50% Figure 5. Antiblooming-Driver Waveforms VCC EN 50% 50% GND tPZH IA1OUT, IA2OUT, SAOUT, SROUT tPLZ VIM or VS 50% 50% GND tPLZ tPZH VAB or VABM ABOUT 50% 50% GND Figure 6. Enable Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMC57253 DRIVER SOCS040A – MARCH 1994 – REVISED NOVEMBER 1994 MECHANICAL DATA HSOP-B plastic small-outline package This small-outline package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high-humidity conditions. Leads require no additional cleaning or processing when used in soldered assembly. 0,50 0,30 1,27 24 0,13 M 13 6,65 6,35 7,60 10,80 7,40 10,00 0,30 0,20 1 12 15,40 15,20 19,50 18,90 0°– 10° 1,20 0,40 Seating Plane 0,15 0,10 MIN 2,65 MAX 7/94 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TMC57253 DRIVER SOCS040A – MARCH 1994 – REVISED NOVEMBER 1994 MECHANICAL DATA 15,3 0,76 1,7 0,51 24 13 7,8 7,0 1 12 1,27 ALL LINEAR DIMENSIONS ARE IN MILLIMETERS Figure 7. 24-Pin/375-mil HSOP Land Design 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10,8 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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