× SOCS062B – JANUARY 2001 – REVISED MAY 2002
D Very Low Noise, High Sensitivity,
D
D
D
D
D
D
D
D
D
DUAL-IN-LINE PACKAGE
(TOP VIEW)
ODB 1
12 IAG1
IAG2 2
11 SAG1
SAG2 3
10 SUB
SRG1 4
9 ADB
SRG2 5
8 NC
CMG 6
7 Vout
D High Photoresponse Uniformity from
Deep Ultraviolet (DUV) to Near Infrared
(NIR)
D Solid State Reliability With No Image
Burn-In, Residual Imaging, Image
Distortion, Image Lag, or Microphonics
description
The TC253SPD device is a frame-transfer, CCD image sensor designed for use in black and white NTSC TV,
computer, and special-purpose applications that require high sensitivity, low noise, and small size.
The TC253SPD sensor is a new device of the IMPACTRONt family of very low noise, high sensitivity image
sensors that multiply charge directly in the charge domain before conversion to voltage. The charge carrier
multiplication (CCM) is achieved by using a low-noise, single-carrier, impact ionization process that occurs
during repeated carrier transfers through high field regions. Applying multiplication pulses to specially designed
gates activates the CCM. The amount of multiplication is adjustable, depending on the amplitude of the
multiplication pulses. The device function resembles the function of image intensifiers implemented in solid
state.
This MOS device contains limited built-in gate protection. During storage or handling, the device leads should be shorted together
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to VSS. Under no
circumstances should pin voltages exceed absolute maximum ratings. Avoid shorting OUT to VSS during operation to prevent
damage to the amplifier. The device can also be damaged if the output terminals are reverse-biased and an excessive current is
allowed to flow. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling
Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IMPACTRON is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
Copyright 2002, Texas Instruments Incorporated
!"#$ % $& '(!)%* !!"#$% !&' + ",)!($- &''$%$% "'$' '" $&
!%+%'$% ' #./$ $ &'* %$&#$ $%-
POST OFFICE BOX 655303
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1
ADVANCE INFORMATION
D
Electronically Variable
High Resolution, 1/3-in Format, Solid State
Charge-Coupled Device (CCD) Frame
Transfer Image Sensor for Black and White
National Television and Standard
Committee (NTSC) and Computer
Applications
340,000 Pixels per Field
Frame Memory
656 (H) × 496 (V) Active Pixels in Image
Sensing Area Compatible With Electronic
Centering
Multimode Readout Capability
– Progressive Scan
– Interlace Scan
– Line Summing
Fast Single-Pulse Clear Capability
Continuous Electronic Exposure Control
from 1/60 s to 1/5,000 s
7.4 µm Square Pixels
Advanced Lateral Overflow Drain
Low Dark Current
× SOCS062B – JANUARY 2001 – REVISED MAY 2002
description (continued)
The image-sensing area of the TC253SPD sensor is configured into 500 lines with 680 pixels in each line.
Twenty-two pixels are reserved in each line for dark reference. The blooming protection is based on an
advanced lateral overflow drain concept that does not reduce NIR response. The sensor can be operated in
the interlaced or progressive scan modes and can capture full 340,000 pixels in one image field. The frame
transfer from the image-sensing area to the memory area is accomplished at a very high rate that minimizes
image smear. The electronic exposure control is achieved by clearing unwanted charge from the image area
using a short positive pulse applied to the antiblooming drain. This pulse marks the beginning of the integration
time, which can be arbitrarily shortened from its nominal length. After charge is integrated and stored in the
memory it is available for readout in the next cycle. This is accomplished using a unique serial register design
that includes special charge multiplication pixels.
ADVANCE INFORMATION
The TC253SPD sensor is built using TI-proprietary advanced split-gate virtual-phase CCD (SGVPCCD)
technology, which provides devices with wide spectral response, ranging from DUV to NIR, high quantum
efficiency (QE), low dark current, and high response uniformity. The TC253SPD sensor is characterized over
an operating free-air temperature range of TA= –10°C to 45°C.
2
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× SOCS062B – JANUARY 2001 – REVISED MAY 2002
functional block diagram
1
ODB
Dark Reference Pixels
Image Sensing Area
with Blooming Protection
3
12
IAG1
11
Image Storage Area
SAG2
ADVANCE INFORMATION
2
IAG2
4
SAG1
10
SRG1
SUB
Serial Readout Register
9
ADB
5
Clearing Drain
SRG2
7
Charge Multiplier
VO
6
CMG
Output Amplifier
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3
× SOCS062B – JANUARY 2001 – REVISED MAY 2002
sensor topology diagram
24 Dark
Reference
Pixels
656 Active Pixels
Dark Reference Pixels
ADVANCE INFORMATION
496 Active Lines
Image Sensing Area
with Blooming Protection
4 Dark
Isolation Lines
Image Storage Area
500 Lines
Optical Black Pixels (OPB)
24
656 Active Pixels
98
400 Multiplication Pixels
Dummy Pixels
4
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188
× SOCS062B – JANUARY 2001 – REVISED MAY 2002
Terminal Functions
TERMINAL
ADB
NO.
I/O
DESCRIPTION
9
I
Supply voltage for amplifiers and clearing drain
CMG
6
I
Charge multiplication gate
IAG1
12
I
Image area gate 1
IAG2
2
I
Image area gate 2
NC
8
–
No connection
ODB
1
I
Supply voltage for antiblooming drain
VOUT
SAG1
7
O
Output signal, multiplier channel
11
I
Storage area gate 1
SAG2
3
I
Storage area gate 2
SRG1
4
I
Serial register gate 1
SRG2
5
I
Serial register gate 2
SUB
10
Chip substrate
detailed description
The TC253SPD sensor consists of four basic functional blocks: the image-sensing area, the image storage
area, the serial register, and the charge multiplier. The location of each of these blocks is identified in the
functional block diagram.
image-sensing and storage areas
Figure 1 and Figure 2 show cross sections with potential-well diagrams and top views of the pixels in the
image-sensing and storage areas. As light enters silicon in the image-sensing area, electrons are generated
and collected in potential wells of the pixels. Applying a suitable dc bias to the antiblooming drain provides
blooming protection. Electrons that exceed a specified level, determined by the ODB bias, are drained away
from the pixels. If it is necessary to remove all previously accumulated charge from the wells, a short positive
pulse must be applied to the drain. This marks the beginning of the new integration period. After the integration
cycle is completed, charge is quickly transferred into the memory where it waits for readout. The lines can be
read out from the memory in a sequential order to implement progressive scan, or two lines can be summed
together to implement the pseudo-interlace scan.
Twenty-two columns at the left edge of the image-sensing area are shielded from incident light. These pixels
provide the dark reference used in subsequent video-processing circuits to restore the video black level. An
additional four dark lines located between the image-sensing area and the image storage area were added for
isolation.
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5
ADVANCE INFORMATION
NAME
× SOCS062B – JANUARY 2001 – REVISED MAY 2002
IAG2/SAG2
IAG1/SAG1
Polysilicon Gates
p+
Virtual Phase
ÎÎÎÎÎÎÎÎÎ
+++++++++++++++++++++++++
n – Buried Channel
p – Substrate
ADVANCE INFORMATION
Pixel Cross Section
X
Integrated
Charge
Ø
Channel Potential
Figure 1. Image Area and Storage Area Pixel Cross Section with Channel Potential
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× SOCS062B – JANUARY 2001 – REVISED MAY 2002
7.4 µm
IAG1
IAG2
7.4 µm
Image Area Pixel
Antiblooming
ADVANCE INFORMATION
Drain
Channel Stops
SAG1
SAG2
7.0 µm
Storage Area Pixel
7.4 µm
Figure 2. Image Area and Memory Area Pixel Topologies
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7
× SOCS062B – JANUARY 2001 – REVISED MAY 2002
advanced lateral overflow drain
The advanced lateral overflow drain structure is shared by two neighboring pixels in each line. Varying the dc
bias of the antiblooming drain can control the blooming protection level and trade it for well capacity. Applying
a pulse (approximately 10 V above the nominal level for a minimum of 1 µs) to the drain removes all charge from
the pixels. This feature permits a precise control of the integration time on a frame-by-frame basis. The
single-pulse clearing capability also reduces smear by eliminating accumulated charge in the pixels before the
start of the integration period (single-sided smear). The application of a negative 1-V pulse to the antiblooming
drain during the parallel transfer is recommended. This pulse prevents creation of undesirable artifacts caused
by the on-chip crosstalk between the image area gate clock lines and the antiblooming drain bias lines.
ADVANCE INFORMATION
serial register and charge multiplier
The serial register is used to transport charge stored in the pixels of the memory to the output amplifier. However,
the TC253SPD device has a serial register with twice the standard length. The first half has a conventional
design that interfaces with the memory and the clearing drain as it would in any other CCD sensor (for example
the TC237 sensor). The second half, however, is unique and includes 400 charge multiplication stages with a
number of dummy pixels that are needed to transport charge between the active register blocks and the output
amplifier. Charge is multiplied as it progresses from stage to stage in the multiplier toward the charge detection
node. The charge multiplication level depends on the amplitude of multiplication pulses (approximately 11 V ~
17 V) applied to the multiplication gates. Due to the double length of the registers, the first line in the field or frame
scan does not contain valid data and must be discarded.
readout and video processing
The last element of the charge readout and detection chain is the charge detection node. Charge detection
nodes use standard floating diffusion (FD) concepts followed by dual-stage source followers as buffer
amplifiers. The reset gate is internally connected to SRG1. This connection results in a simultaneous FD reset
when the SRG1 gate is clocked high. To achieve the ultimate sensor performance, it is necessary to eliminate
the detection node kTC noise using CDS processing techniques. The IMPACTRONt devices can detect single
photons when cooling or when sufficiently short integration times are used.
8
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VSS: ADB (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUB to SUB + 15 V
Supply voltage range, VSS: ODB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUB to SUB + 22 V
Input voltage range, VI: IAG1, IAG2, SAG, SRG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to 10 V
Input voltage range, VI: IAG1, SAG, SRG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –8 V to 8 V
Input voltage range, VI: SRG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to 8 V
Input voltage range, VI: CMG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to 15 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10°C to 45°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30°C to 85°C
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10°C to 55°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to SUB.
MIN
Substrate bias, VSS
MAX
0
ADB
ODB
IAG1
IAG2
SAG1
SAG2
SRG1
SRG2
Load capacitance
5.5
High
2.4
Low
–3.2
High
4.5
Low
–6.2
High
2.4
Low
–2.4
High
3.1
Low
–4.2
High
4.2
Low
–4.6
High
5.7
Low
–3.4
7
Low
V
13.6
–2
IAG1, IAG2
3.125
SAG1, SAG2
3.125
SRG1, SRG2
12.5
CMG
12.5
OUT
Operating free-air temperature, TA
V
13
High
CMG
Clock frequency,
freq enc fclock
V
6
For clearing
For transfer
Input voltage
voltage, VI†
UNIT
12
For blooming control
S ppl voltage,
Supply
oltage VDD
NOM
ADVANCE INFORMATION
recommended operating conditions
–10
MH
MHz
6
pF
45
°C
† Fine tuning of input voltages is required in order to obtain good charge transfer.
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× SOCS062B – JANUARY 2001 – REVISED MAY 2002
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
Charge multiplication gain
MIN
TYP†
1
30
MAX
(100)‡
1
1.2
1.4
Charge multiplication gain temperature coefficient
%/°C
Excess noise factor for typical CCM gain (see Note 2)
τ
Dynamic range without CCM gain
58
Dynamic range with typical CCM gain (see Note 3)
50
dB
Charge conversion gain without CCM (see Note 4)
10
µV/e
Signal-response delay time (see Note 5)
9
ns
Ω
Amplifier noise-equivalent signal without CCM gain §
42
e
Amplifier noise-equivalent signal with typical CCM gain §
1.5
e
Response linearity with no CCM gain
1
Response linearity with typical CCM gain
ADVANCE INFORMATION
dB
320
Output resistance
1
Charge-transfer efficiency (see Note 6)
0.9998
Supply current
Ci
UNIT
2
Inp t capacitance
Input
0.9999
3
IAG-1
2.95
IAG-2
3.22
IAG-1–IAG2
1.98
SAG-1
3.04
SAG-2
3.62
SAG-1–SAG2
2.22
SRG-1
40
SRG-2
40
4
mA
nF
SRG-1–SRG2
CMG
30
pF
CMG–SRG1
ODB
Pulse amplitude rejection ratio
1,000
ADB high (see Note 7)
20
SRG-1, 2 high (see Note 7)
45
SRG-1, 2 low (see Note 7)
45
CMG high (see Note 7)
45
CMG low (see Note 7)
45
ODB low (see Note 7)
dB
45
† All typical values are at TA = 25°C.
‡ Maximum CCM gain is not ensured.
§ The values in this table are quoted using correlated double sampling (CDS), which is a signal processing technique that improves performance
by minimizing undesirable effects of reset noise.
NOTES: 2. Excess noise factor F is defined as the ratio of noise sigma after multiplication divided by M times the noise sigma before
multiplication where M is the charge multiplication gain.
3. Dynamic range is –20 times the logarithm of the mean noise sigma divided by the saturation output signal amplitude.
4. Charge conversion factor is defined as the ratio of output signal to input number of electrons.
5. Signal-response delay time is the time between the falling edge of the SRG2 pulse and the output signal valid state.
6. Charge transfer efficiency is 1 minus the charge loss per transfer in the CCD register. The test is performed in the dark using either
electrical or optical input.
7. Rejection ratio is –20 times the logarithm of the output referenced to the reset level divided by the 1 V of amplitude change of the
corresponding gate or terminal signal.
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optical characteristics, TA = 40°C (unless otherwise noted)
PARAMETER
MIN
No IR filter
Sensitivity with typical CCM gain (see Note 8)
MAX
UNIT
240
With IR filter
V/Lux
33
No IR filter
Sensiti it without
Sensitivity
itho t CCM gain (see Note 8)
TYP
8
With IR filter
V/L
V/Lux
1.1
Vsat
Vsat
Saturation signal output no CCM gain (see Note 9)
260
mV
Saturation signal output with typical CCM gain (see Note 9)
440
mV
Voff
Zero input offset output (see Note 10)
200
mV
Blooming overload ratio (see Note 11)
1000:1
26k
Smear (see Note 12)
Dark current (see Note 13)
0.15
0.90
66
dB
nA/cm2
Dark signal (see Note 14)
0.08
0.50
mV
Dark-signal uniformity (see Note 15)
Dark-signal shading (see Note 16)
Dark
Spurious nonuniformity
Illuminated
Column uniformity (see Note 17)
0.3
mV
0.4
mV
0.8
mV
–20%
20%
0.2
Electronic-shutter capability
1/5000
mV
1/60
s
NOTES: 8. Light source temperature is 2856°K. The IR filter used is CM500 1 mm thick.
9. Saturation is the condition in which further increase in exposure does not lead to further increases in output signal.
10. Zero-input offset is the residual output signal measured from the reset level with no input charge present. This level is not caused
by the dark current and remains approximately constant, independent of temperature. This level can vary with the amplitude of
SRG2.
11. Blooming is the condition in which charge induced by light in one element spills over to the neighboring elements.
12. Smear is the measure of error signal introduced into the pixels by transferring them through the illuminated region into the memory.
The illuminated region is 1/10 of the image area height. The value in the table is obtained for the integration time of 16.66 ms and
3.125 MHz vertical clock transfer frequency.
13. Dark current depends on temperature and approximately doubles every 8°C. Dark current is also multiplied by the CCM operation.
The value given in the table is with the multiplier turned off, and it is a calculated value.
14. Dark signal is actual device output measured in darkness.
15. Dark signal uniformity is the sigma of difference of two neighboring pixels taken from all the image area pixels.
16. Dark signal shading is the difference between maximum and minimum of a 5-pixel median taken anywhere in the array.
17. Column uniformity is obtained by summing all the lines in the array, finding the maximum of the difference of two neighboring columns
anywhere in the array, and dividing the result by the number of lines.
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11
ADVANCE INFORMATION
Image area well capacity
× SOCS062B – JANUARY 2001 – REVISED MAY 2002
Clear
Integrate
Transfer to Memory
Readout
Pulse Position
Determines Exposure
ODB
IAG1
IAG2
ADVANCE INFORMATION
501 Cycles
SAG1
SAG2
685 Pulses Line 0 {
685 Pulses Line 500
SRG1
686 Pulses Line 500
686 Pulses Line 0 {
686 Pulses Line 500
686 Pulses Line 0 {
SRG2
CMG
Expanded Section of Parallel Transfer
500 Pulses
Expanded Section of Serial Transfer
Expanded Section of Serial Transfer
IAG1
IAG2
SRG1
SRG1
SAG1
SRG2
SRG2
SAG2
CMG
CMG
{ Line 0 does not contain valid data.
Figure 3. Progressive Scan Timing
12
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× SOCS062B – JANUARY 2001 – REVISED MAY 2002
Clear
Integrate
Transfer to Memory
Readout
Pulse Position
Determines Exposure
ODB
IAG1
IAG2
ADVANCE INFORMATION
251 Cycles
SAG1
SAG2
685 Pulses Line 0 {
685 Pulses Line 250
SRG1
686 Pulses Line 250
686 Pulses Line 0 {
686 Pulses Line 250
686 Pulses Line 0 {
SRG2
CMG
Expanded Section of Parallel Transfer
500 Pulses Even Field, 501 Pulses Odd Field
Expanded Section of Serial Transfer
Expanded Section of Serial Transfer
IAG1
IAG2
SRG1
SRG1
SAG1
SRG2
SRG2
SAG2
CMG
CMG
{ Line 0 does not contain valid data.
Figure 4. Interlace Timing for Line Summing Mode
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13
× SOCS062B – JANUARY 2001 – REVISED MAY 2002
CMG
SRG1
ADVANCE INFORMATION
SRG2
V OUT 1,2
Output Signal{
Reset Level
S/H
Clamp
{ Output signal may not be zero for zero-input charge. Offset level up to 100 mV may be present.
Figure 5. Detail Serial Register Clock Timing for CDS Implementation
14
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× SOCS062B – JANUARY 2001 – REVISED MAY 2002
SAT
VO [mV]
V
10*M µV/e
Zero Offset
Ith
ADVANCE INFORMATION
Built-In Threshold Level
Input Light Intensity [Lux]
Figure 6. Photon Transfer Characteristic of CCD Outputs
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15
× SOCS062B – JANUARY 2001 – REVISED MAY 2002
APPLICATION INFORMATION
–Vsrg2 +Vsrg2 –Vsrg1 +Vsrg1 –Viag2 +Viag2 –Viag1 +Viag1
Vcc
–Vsag2+Vsag2–Vsag1+Vsag1Vodb Vcl
ODB1
SAG2
–Vsag2
EL7156CS
0.1
ADVANCE INFORMATION
+Vsag2
1 VS+ VH 8
2 OE OUT 7
3 IN
VL 6
4 GND VS– 5
Vcc 10 k
Vcc 10 k
–Vsag2
0.1
IAG2
–Viag2
0.1
EL7156CS
0.1
EL7156CS
IAG1
1 VS+ VH 8
2 OE OUT 7
3 IN
VL 6
–Viag1
4 GND VS– 5
Vcc 10 k
4 GND VS– 5
0.1
0.1
+Viag2
–Viag2
ODB2
0.1
0.1
EL7156CS
Vodb
ODB2
GND
–Vsag1
ODBout
ODB Driver
4 GND VS– 5
–Vsag1
1 VS+ VH 8
2 OE OUT 7
3 IN
VL 6
Vcc 10 k
SAG1
+Vsag1
1 VS+ VH 8
2 OE OUT 7
3 IN
VL 6
ODB1
0.1
0.1
+Viag1
10
10
–Viag1
10
10
0.1
10
0.1
10
12
1 ODB
IAG1
2 IAG2 SAG1 11
3 SAG2 SUB 10
4 SRG1
5 SRG2
ADB 9
NC 8
6 CMG
Vout 7
10
0.1
TC253
OUT
+Vsrg2
1 VS+ VH 8
2 OE OUT 7
3 IN
VL 6
Vcc 10 k
SRG2
Vcc 10 k
–Vsrg2
4 GND VS– 5
EL7156CS
SRG1
+Vsrg1
1 VS+ VH 8
2 OE OUT 7
3 IN
VL 6
Vcmdh Vcmdl
–Vsrg1
CMG
4 GND VS– 5
0.1
EL7156CS
0.1
0.1
CMG
Vcmgh
Vcmgl
0.1
GND CMGout
CMG Driver
Vcc
Vcc
+
0.1
Oscillator
33
CLK
IAG1
IAG2
SAG1
SAG2
SRG1
SRG2
CMG
ODB1
ODB2
CLMP
S/H
SYNC
GND LCLMP
CLEAR
User Defined Timer
NOTES: A.
B.
C.
D.
DC Voltages (Typ.)
Vcl
12 V
+Viag1
2.4 V
–Vsrg2
–3.4 V
Vodb
15 V
–Viag1
–3.2 V
Vcmgh
13.6 V
Vcc
5V
+Viag2
4.5 V
Vcmgl
1.5 V
+Vsag1
2.5 V
–Viag2
–6.2 V
–Vsag1
–2.5 V
+Vsrg1
4.2 V
+Vsag2
3.5 V
–Vsrg1
–4.6 V
–Vsag2
–4.0 V
+Vsrg2
5.7 V
All values are in Ω and µF unless otherwise noted.
TI recommends ac coupled system for coupling to the next video processing circuits.
IAG and SAG signal from user defined timer must be shifted its GND level to –V before the driver IC (EL7156CS) input.
The value of the CCD external capacitors (on IAG and SAG) were recommended with 2000 pF ~ 5000 pF.
Figure 7. Typical Application Circuit
16
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× SOCS062B – JANUARY 2001 – REVISED MAY 2002
APPLICATION INFORMATION
Vcmgh
0.1
1SS226
2200p
10 k
1SS193
TP2104N3
CMG
0.1
10 k
CMGout
0.1
TN2106N3
2200p
1SS193
1SS226
ADVANCE INFORMATION
10 k
0.1
Vcmgl
CMG Driver Circuit
Vodb = 24 V
2.7 k
VR
2.0 k
5.6 k
0.1
Q1
10
2.7 k
1.5 k
ODBout
1.5 k
Q2
ODB1
3.3 k
3.3 k
Q3
ODB2
3.3 k
ODB Driver Circuit
NOTE A: All values are in Ω and µF unless otherwise noted.
Figure 8. Example of CMG Driver Circuit
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17
× SOCS062B – JANUARY 2001 – REVISED MAY 2002
MECHANICAL DATA
The package for the TC253SPD image sensor consists of a ceramic base, a glass window, and a 12-lead frame.
The glass window is sealed to the package by an epoxy adhesive. The package leads are configured in a
dual-in-line arrangement and fit into mounting holes with 1,78 mm center-to-center spacing.
TC253 (12 pin)
1 pin Index Mark
1.78
0.76
11.85
11.75
Opticle Center
0.51
0.41
4.45
4.15
1 pin
12.40
12.00
ADVANCE INFORMATION
12 pin
5.94
5.64
6 pin
7 pin
Package Center
11.50
11.10
3.65
3.35
11.05
10.95
2.08
1.48
3.298
2.798
3.998
3.398
Focal Plane
0.33
0.17
11.68
11.18
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS
10/00
18
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